abstract - tokyo metropolitan universitysharc adsp21062 piggy pack ws9002 construction of a compact...

Abstract　We have developed a DSP based data-acquisition syustem(DAQ) system, based on the SHARC DSP. The system utilizes SHARC VME boards with one or two SHARCs. Our intension was to consturct a compact DAQ framework which is adequate to a subdetector DAQ system in a detector complex for a large collider experiment. 　　The system consists of five VME crates; one(control crate) is used for the local event builder as well as a run-controller, which is the master in the system, and others(FADC crate) for the readout from the several FADC modules. We install one SHARC board with one SHARC each in each FADC crate and two SHARCboards with two SHARCs each in the control crate. Data transfer between the control crate and each FADC crate is performed using the SHARC link with a transfer rate of about 40 MB/s, routed to the VME board front panel by the SHARC IO piggy pack module.

In this paper, we report system design and development of the compact DAQ system using SHARC board and introduce an application example of this system to the BELLE SVD DAQ system.

Construction of a compact DAQ-system using DSP-based VME modules

RT99 Santa-Fe, New-Mexico ,USA June 14-18,1999



measuement of e+(3.5 GeV) e-(8 GeV) collisionto study CP violation in B-decay via reaction ofY(4S) B0,B0 pair decays

Life Time of B0 is about 1.5 ps Measurement of vertex positions is important

Silicon Vertex Detector(SVD)81920 si microstrips readout channels

e

e

-

+BELLE Detector



DSSD ladders

Layer 1

Layer 2

Layer 3

Hybrid boardVA1 chip

Silicon detector

R=20mm

R=

30.0mm

R=

45.5mm

R=

60.5mm

d=9.5m

md=

8.5mm

d=12m

m

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8

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45

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8 11

2

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Mechanican Structure of BELLE Silicon Vertex Detector

3 layer structure to form3 barrels around e+e- beam lines

e- e+

30cm

Outer layer of the SVD



Concept of BELLE SVD DAQ System Preampilifier Chip(VA1) (S&H, 128 ch. mulx.single output)

FADCs(Halny) (Home made of Cracow Inst. of NP for SVD)

Crate processors (SHARC)

SPARC CPU-7V (UNIX) BELLE Central DAQ (Global Mode)

SHARC links Local Control Crate (Local Mode)

Common operation in an FADC crate

VME connection Structure of the BELLE SVD DAQ

FADC Crates

CDAQ

SHARC Link

Local Control Crate

FADCModules

WS

2126

CP

U-7V

CEBTX(CPU-7V + CDAQ I/F)

Detector

WS

2126

WS

2126

Each FADC crate connects to CDAQ independently

Data of all four FADC crates are merged in the local crate

WS2126(SHARC board) with 2 SHARCSWS2126 with 1 SHARC

WS2126 with 1 SHARC

WS2126 with 1 SHARC

WS2126 with 1 SHARC



WS2126 SHARC Board (SHARC DSP VME cluster)produced by Wiese GmbH, Germany

SHARC IO-Pack

SHARC IO-Pack

SHARC IO-Pack

SHARC IO-Pack

SHARC IO-Pack

SHARC IO-Pack

SHARCJTAG

ConnectorControl Logic

andRegister Set

SH

AR

C B

us (

48

bit d

ata

wid

th )

Loca

l Bus

VM

E B

us

SHARCADSP2106x

SHARCADSP2106x

SHARCADSP2106x

SHARCADSP2106x

SHARCADSP2106x

SHARCADSP2106x

Link

Bus

Linkable expansion connectors for- 0 WS-Memory, DMA engines, ...- VME P2 access- Customized Logic

FIFOup to

64 K x 16

Memoryup to

3 Mbyte

1. Up to six SHARCS can be mounted.2. Each SHARC can work synchronously with SHARC bus or independently.3. VME master/slave4. VME DMA/BLK transfer5. SHARC link with IO piggy pack(WS9002)6. SHARC link = 40 MB/s(DMA & Sngl Word)

2 x WS2126 with 2 SHARCs mounted installed in the Local Control Crate1 WS2126 with 1 SHARC mounted installed in each FADC crate as CORE processor

WS2126 with two SHARCs mounted amd one IO piggy pack on one of the SHARC

ALTERA MAX9000 CPLDfor VME operation logic

SHARC ADSP21062 piggy packWS9002



FADC Crates

CDAQ

SHARC Link

Local Control Crate

FADCModules

WS

2126

CP

U-7V

CEBTX(CPU-7V + CDAQ I/F)

Detector

WS

2126

WS

2126

Force CPU-5VReadout program

WS2126(2 SHARC DSPs)

WS2126 in FADC crate(1 SHARC DSPs)

FADC modules of FADC crate # 1




DMA

VME bus

SHARCSRAM

Linkbuffers

On-boardSRAM

WS2126(2 SHARC DSPs)

SHARCSRAM

Linkbuffers

On-boardSRAM

Local control crate

Time

SHARC link

DM

A

Data & Control flow in the DAQ systemData flow in a Single FADC crate(1) WS2126 Master to accumulate FADC data via VME BLK xfer.(2) CPU-7V Master and WS2126 Slave and CPU-7V reads WS2126 Memory, formats data and sends toCDAQ via CEBTX(Global).(3) Timing of the Master switching is scanned by polling.(2') WS2126 setups SHARC link and send them via DMA mode(Local)

.....

...

FADCs SHARC board (Wiese WS2126)

CEBRXSHARC Link

VME bus

CPU-7V

CEBTX

S-bus

(1)(2)

(3) (2')Data Flow in the Local Control Crate in the local run mode



0

1

2

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5

6

7

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9

10

10 102

103

Length (byte)

Spee

d (M

B/s

)

WS2126 single wordWS2126 DMA single wordCPU-5V single wordCPU-5V DMA single word

Basic Performance TestVME transfer rates versus Data Transfer Length(Byte)

SHARC link Transfer(Nominal rate will be expected as 40 MB/s)

Rate OverheadNormal in Core Process 9.69 MB/s 1 usDMA Process 33.7 MB/s 1.9 us

Bandwidth(MB/s) Overhead(us)Normal transfer in core procs. 9.69 1DMA transfer 33.7 1.9

WS2126 VME capability Rate at 1 KByte (MB/s) Overhead(us)Normal single word transfer 3.8 DMA single word transfer 8.5 4.6



CP

U-7

V Modulesfor timing control

CP

U-7

V

. . . .

Hal

ny F

AD

C m

od

ule

s

Repeater SystemDSSD Ladders

4 x FADC crates

Ethernet Local Control Crate

Scintillation trigger counter

Scintillation trigger counter

CP

U-7

V

. . . .

Hal

ny F

AD

C m

od

ule

s

Repeater System

. . . . .

. . . . .

SHARC Link

Control Signals

WS

2126

WS

2126

WS

2126

WS

2126

SYSTEM Test with Cosmic RaySpecial setup of SVD for Cosmic ray obervation test

We have made a special setup for the SVD to observe the cosmic rays after whole SVD barrel has been constructed but before we installed it to the BELLE. The main purpose of the test it to get rid off bugs hidden in the hardware/software of the readout system.The DAQ system are examined with the preformance and stability. For the sability test, we made a special program to check parity/checksums before the SHARC links. And no bit transfer failure has been observed in few days operation.

Cosmic ray

Numbers in the display means the pulse height in unit of 1000 e-

SVD Cosmic-ray Event Display



Summary We have constructed the SHARC DSP-based compact DAQ system. To minimize the processing time in the readout operation, we selected to use the WS2126(produced by Wiese GmbH, Germany) as a core processor module in the system. The VME performance of the WS2126 was greater than that of a CPU-5V(, which is almost identical as CPU-7V as far as the VME processing ability is concerned). We could have fast enough VME transfer rate of 3.8 MB/s and 8.5 MB/s for single word and DMA singlw word, respectively. The SHARC link is an essential facility in the multi-mode DAQ system. We have observed the bandwidth of this link as 9.69 MB/s and 33.7 MB/s for single word and DMA transfer, respectively. In the system test with cosmic ray, we could observe and reconstruct cosmic ray tracks from hit position information. This means that we could collect whole data from each FADC crate synchronously. Through the system test for the SVD DAQ system, we can confirm that the DAQ system can give enough performance in the real DAQ system eventually if the SVD and its DAQ system are integrated in the BELLE frame work.

abstract - tokyo metropolitan universitysharc adsp21062 piggy pack ws9002 construction of a compact...

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