IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 8, AUGUST 2003 481

Transactions Brief___________________________________________________________________

Absolute-Value Circuit Using JunctionField-Effect Transistors

Alexandru A. Ciubotaru

Abstract—A novel configuration for an absolute-value circuit (full-waverectifier with zero threshold) using two matched junction field-effect tran-sistors is proposed and experimentally demonstrated. The zero-thresholdrectification is accompanied by a scaling of the input signal by a theoret-ical factor of 1 2, and is achieved by mathematically exploiting the non-linear characteristics of the transistors. The circuit operates with comple-mentary input signals and requires a dc bias voltage for the transistor gates.Negative or positive output voltages can be obtained by using either - orp-channel devices.

Index Terms—Circuit functions, JFET analog integrated circuits, JFETs,nonlinear circuits, rectifiers.

I. INTRODUCTION

Absolute-value circuits (sometimes known as full-wave rectifiers)are widely used in analog electronics in applications such as acmeasurements, function fitting, providing inputs to single-quadrantdevices, triangular-wave frequency doubling, error measurements,average envelope detection, and clock recovery [1]–[3]. For theseand other analog signal processing circuits there is a continuousreduction in supply voltage and power consumption, driven primarilyby portability requirements. The ever-shrinking headroom available tothe active devices causes important mutations in the circuit topology,such as the absence of Darlington pairs, cascodes, and even emitterfollowers [4]. Thus, it becomes increasingly difficult to avoid thedegradation of performance due to these topological changes, and newcircuit configurations capable of high performance with low supplyvoltages must be invented.

Although there exists a wide variety of absolute-value circuits, mostof the proposed topologies to date are either not suitable for operation inlow supply voltage environments (on the order of 1 V), or are not veryaccurate. Examples of circuits in the former category can be found in[5]–[14], where relatively large supply voltages are required typicallybecause of complementary devices, current mirrors, or the need to ac-commodate logic signals for switches; an example in the latter categoryis [15], where relatively inaccurate transfer characteristics are acceptedas approximations for the absolute-value function.

There are also other implementations of the absolute-value functionusing current-mode circuits [16]–[19]. Although one of the circuits pro-posed in [16] does have the potential of operating with low supply volt-ages, the schematic is relatively complicated and requires three opera-tional amplifiers. The CMOS circuits described in [17]–[19] are com-paratively simple but require a current input, and a transconductor mustbe used in case the input is a voltage; moreover, a current mirror (whichfurther limits the minimum acceptable supply voltage) must be used fortrue absolute-value operation.

Manuscript received May 7, 2002. This paper was recommended by AssociateEditor L. Trajkovic

The author is with the Maxim Integrated Products, Melbourne Design Center,Melbourne, FL 32934 USA (e-mail: alexc@mxim.com).

Digital Object Identifier 10.1109/TCSII.2003.813587

Fig. 1. Proposed absolute-value circuit.

This brief presents a simple and novel absolute-value circuit whichuses two matched symmetrical junction field-effect transistors (JFETs)to eliminate the disadvantages associated with low supply voltages.The zero-threshold rectification takes place indirectly at the transistorlevel, as a mathematical consequence of the JFET nonlinearities. Inthis way, the circuit works with low supply voltages that accommodateonly two complementary input voltages without any headroom for ad-ditional circuitry, being very attractive for use in portable systems. Thepresent circuit also uses a dc bias voltage for the gates of the JFETs,which is very easy to generate and requires only a small bias current.If n-channel devices are used, the output of the circuit is a negativevoltage; a positive output is generated forp-channel devices. The the-oretical scaling factor between input and output is1=

p2, and is not a

function of the JFET parameters (notably the drain saturation currentand the pinch-off voltage). The circuit is somewhat related to severalother nonlinear JFET circuits that use complementary input voltages[20]–[24], and can easily be realized in monolithic form or be inte-grated in more complex systems.

II. PRINCIPLE OFOPERATION

The proposed circuit is shown in Fig. 1, whereQ1 andQ2 are iden-tical and symmetricaln-channel JFETs (the drain and source of a sym-metrical JFET can be interchanged without affecting the characteris-tics of the transistor). For an input voltagevIN > 0 and assuming asufficiently large load resistanceRL such thatiL � iD1; iD2 (i.e.,iD1 �= iD2); Q1 operates in saturation andQ2 operates in the trioderegion (vice versa forvIN negative). These operating conditions are notevident at this point, but will be confirmed by computingvOUT and thetransistor voltages using the appropriate saturation- and triode-regionexpressions for the drain currents. Thus, if the dc bias voltage is setequal to the JFET pinch-off voltageVP, currentsiD1 andiD2 can bewritten as [25]

iD1 = IDSS 1� vGS1VP

2

(1)

iD2 = IDSS 2 1� vGS2VP

vDS2�VP

� vDS2VP

2

(2)

wherevGS1 = VP�vOUT; vGS2 = VP+vIN andvDS2 = vOUT+vIN.After a few manipulations that are not shown, fromiD1 �= iD2 andusing (1) and (2), it follows that

v2IN � 2v2OUT �= 0 (3)

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482 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 8, AUGUST 2003

Fig. 2. Circuit for accurately generating the dc bias voltage in Fig. 1.

which yieldsvOUT �= � 1=p2 jvINj. The positive solution is not

valid because it turns offQ1(vGS1 < VP ; iDS1 = 0); the correct solu-tion is then

vOUT �= � 1p2jvINj: (4)

With the output voltage given by (4) it is easy to verify the initialassumption thatQ1 andQ2 operate in saturation and in the triode re-gion, respectively. Thus, inequalityvDS1 > (vGS1 � VP ), which isthe necessary and sufficient condition for the operation ofQ1 in satu-ration, reduces tovIN > 0, which is true; in the same way, conditionvDS2 < (vGS2 � VP ) ensures the operation ofQ2 in the triode regionand is true because it also reduces tovIN > 0.

If vIN < 0, due to the symmetry of the transistors and the comple-mentary input signals which revert polarity, the same expression (4) isobtained forvOUT; thus, the circuit of Fig. 1 is an absolute-value cir-cuit with negative output, whose gain is independent of the transistorparameters.

The circuit operates correctly as long as the JFET break-down voltages are not exceeded and the transistor junctions(gate–source and gate–drain) are not in strong forward bias.In mathematical form, these conditions can be expressed asjvINj < min VGSon + jVP j;

p2=

p2 + 1 VBR , whereVGSon

is the threshold voltage of the gate-source or gate-drain junction(typically 0.6 V for silicon devices) andVBR is the JFET breakdownvoltage.

It is easy to show that ifp-channel JFETs are used in Fig. 1 instead ofn-channel devices, then the absolute-value circuit has positive output,the same input voltage range, andvOUT is

vOUT �= 1p2jvINj: (5)

One approach for generating the dc bias voltage in Fig. 1 is illustratedin Fig. 2, where the JFET matchesQ1 andQ2, and a low-power op-erational amplifier can be used in portable applications for low-powerdissipation. The operational amplifier can be relatively rudimentary be-cause it does not have to drive any load and needs to provide only a dcvoltage for the JFET gates, but must have low input offset voltage anddrift. If the bias currentI0 is sufficiently small (e.g.,I0 = 0:001IDSS[26]), then the operational amplifier output voltage is practically equalto the pinch-off voltageVP of the JFETs in Fig. 1, and will track thisvalue over temperature and fabrication process. In this way, the tem-perature drift of the JFET pinch-off voltage (which can be as large as2 mV/�C [27]) or of the JFET drain saturation currentIDSS will haveno effect on the circuit’s output voltage, which will still be given by(4).

III. EXPERIMENTAL RESULTS AND DISCUSSION

In order to validate the proposed technique for obtaining the abso-lute value of a signal, the circuit of Fig. 1 was constructed using anNPDS402 n-channel dual JFET [28]. The measured parameters of theJFETs wereIDSS = 2 mA andVP = �0:94 V. The gate bias of thecircuit was externally generated and set to 0.94 V(VP ).

Fig. 3. Measured dc transfer characteristic (v againstv ) of circuit ofFig. 1, forR = 10 k (symbols); line was obtained by nonlinear fitting,v = �0:643jv j.

Fig. 4. Circuit for simulating the high-frequency response of absolute-valuecircuit.

The measured dc transfer characteristic of the absolute-value circuit(vOUT againstvIN; RL = 10 k) is shown in Fig. 3, and was obtainedusing 121 equally spacedvIN values in the range [�1:2 V, 1.2 V].

Using the nonlinear fitting feature available in a software package[29], a function of the formKjvINj with K as a variable was fittedto the curve of Fig. 3. The value returned by the fitting package wasK = �0:643, in good agreement with�0.707 (or�1=p2) predictedby (4). The fitting rms error was 1.29%, a very small number whichindicates that the characteristic of the circuit is well approximated byan ideal absolute-value function, the rms error being calculated as

"rms =

121

i=1

[KjvINij � vOUTi]2 =

121

1

v2OUTi

� 100% (6)

wherevINi are the input voltages andvOUTi are the measured outputvoltages. Thus, the circuit works well even with very small signals, hasvirtually no threshold, and the output voltage of the circuit is accuratelypredicted by (4).

It is also of interest to investigate the operation of the proposed ab-solute-value circuit at high frequencies. Due to a combination of highfrequency and nonlinear effects, the dynamic operation is best illus-trated by simulation, using a high-speed setup such as the one shownin Fig. 4, where the JFET capacitive parasitics are shown explicitly(CGS = CGD for symmetrical JFETs). Also explicitly shown in Fig. 4

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 8, AUGUST 2003 483

Fig. 5. High-frequency response of absolute-value circuit.

are series resistancesRS (primarily accounting for the signal sources,RS = 25 in this case), and the load capacitanceCL. It is interestingto note that, forVP ideally decoupled (short to ground at ac frequen-cies), the total capacitance seen by the output node is approximately(CL + 2CDS + CGS + CGD), and it is this capacitance that is pri-marily responsible for the degradation of the high-frequency response.

Using sinusoidal complementary inputs�vIN of amplitude 0.7 V,and catalog values for the capacitances of the NPDS402 devices(CGS = CGD = 11 pF,CDS = 6 pF [28]), the output voltage of thecircuit at different frequencies is shown in Fig. 5. With no intentionaloutput capacitanceCL, the high-frequency response of the circuitstarts degrading at input frequencies around 1 MHz, and becomesclearly distorted at 10 MHz. An interesting effect, however, is that theaverage value of the output(VAVG �= �VIN

p2=�) is not affected by

the input frequency or the transistor capacitances. Fig. 5 also shows theresponse of the circuit for an intentionalCL = 220 pF, which suggestsits potential use as an average-value detector at high frequencies.

The dynamic response illustrated in Fig. 5 (without an external ca-pacitanceCL) is expected to extend to much higher frequencies in amonolithic circuit, where, depending on the process technology, theparasitic device capacitances can be reduced to a fraction of a pF. Theoutput resistanceRL (allowed to assume the negligibly large valueof 10 k in the simulation shown in Fig. 5) also plays a role in thehigh-frequency operation of the circuit, and can be reduced to moderatevalues for improving the dynamic response; this improvement, how-ever, comes at the price of reducing the low-frequency accuracy, andcomputer simulation and optimization must be used for determiningthe best tradeoff.

IV. CONCLUSION

A simple and novel absolute-value circuit has been presented andexperimentally demonstrated. The circuit uses two matched junctionfield-effect transistors, and produces negative or positive output volt-ages according to the type (n- or p-channel) of the transistors. Thetransfer characteristic of the circuit is a good approximation of the ab-solute-value function and has an embedded scaling factor of1=

p2.

ACKNOWLEDGMENT

The contribution of two anonymous reviewers toward improving thequality of the original manuscript is gratefully acknowledged.

REFERENCES

[1] Nonlinear Circuits Handbook, D. H. Sheingold, Ed., Analog Devices,Inc., Norwood, MA, 1976, p. 23.

[2] K. K. Clarke and D. T. Hess,Communication Circuits: Analysis andDesign. Melbourne, FL: Krieger, 1994, p. 478.

[3] J. D. Gibson,Principles of Digital and Analog Communications. NewYork: Macmillan, 1989, p. 199.

[4] A. Matsuzawa, “Low-voltage and low-power circuit design for mixedanalog/digital systems in portable equipment,”IEEE J. Solid-State Cir-cuits, vol. 29, pp. 470–480, Apr. 1994.

[5] W. E. Hearn and D. J. Rondeau, “Precision Absolute Value Amplifierfor a Precision Voltmeter,” U.S. Patent 4 518 877, May 21, 1985.

[6] C. R. Keate, “High-speed analog multiplier-aAbsolute value detector,”U.S. Patent 4 833 639, May 23, 1989.

[7] R. A. Neidorff, “Absolute value differential amplifier,” U.S. Patent 4 899064, Feb. 6, 1990.

[8] B. Abdi, “Voltage to Absolute value current converter,” U.S. Patent 4906 915, Mar. 6, 1990.

[9] Z. Wang, “Full-wave precision rectification that is performed in currentdomain and very suitable for CMOS implementation,”IEEE Trans. Cir-cuits Syst., vol. 39, pp. 456–462, June 1992.

[10] G. Shou, S. Takatori, and M. Yamamoto, “Absolute value circuit,” U.S.Patent 5 394 107, Feb. 28, 1995.

[11] P. D. Walker and M. M. Green, “CMOS half-wave and full-wave preci-sion voltage rectification circuits,” inProc. 38th Midwest Symp. CircuitsSyst., vol. 2, Rio de Janeiro, Brazil, Aug. 13–16, 1995, pp. 901–904.

[12] S. Yamamoto, “Absolute value circuit capable of providing full-waverectification with less distortion,” U.S. Patent 5 703 518, Dec. 30, 1997.

[13] C. Kuratli and Q. Huang, “A fully integrated self-calibrating trans-mitter/receiver IC for an ultrasound presence detector microsystem,”IEEE J. Solid-State Circuits, vol. 33, pp. 832–841, June 1998.

[14] W. Surakampontorn, K. Anuntahirunrat, and V. Riewruja, “Sinusoidalfrequency doubler and full-wave rectifier using translinear current con-veyor,” Electron. Lett., vol. 34, pp. 2077–2079, Oct. 29, 1998.

[15] K. Kimura, “Some circuit design techniques for bipolar and MOS pseu-dologarithmic rectifiers operable on low supply voltage,”IEEE Trans.Circuits Syst., vol. 39, pp. 771–777, Sept. 1992.

484 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 8, AUGUST 2003

[16] F. J. Lidgey, K. Hayatleh, and C. Toumazou, “New current-mode preci-sion rectifiers,” inProc. IEEE Int. Symp. Circuits Syst., vol. 2, Chicago,IL, May 3–6, 1993, pp. 1322–1325.

[17] C.-C. Chang and S.-I. Liu, “Current-mode full-wave rectifier and vectorsummation circuit,”Electron. Lett., vol. 36, pp. 1599–1600, Sept. 14,2000.

[18] J. Ramírez-Anguloet al., “Very low-voltage class AB CMOS andbipolar precision current rectifiers,” inElectron. Lett., vol. 35, Oct. 28,1999, pp. 1904–1905.

[19] , “Very low-voltage class AB CMOS precision voltage and cur-rent rectifiers,” inProc. IEEE Int. Symp. Circuits Syst., vol. 3, Geneva,Switzerland, May 28–31, 2000, pp. 5–8.

[20] A. A. Ciubotaru, “Square-law circuit using junction field-effect transis-tors,” Electron. Lett., vol. 33, pp. 544–545, Mar. 1997.

[21] , “Four-quadrant multiplier using junction field-effect transistors,”Electron. Lett., 17, 1997.

[22] , “Cube-law circuit using junction field-effect transistors,”Elec-tron. Lett., vol. 34, pp. 1175–1176, June 1998.

[23] , “4th power-law circuits using junction field-effect transistors,”Electron. Lett., vol. 35, pp. 469–471, Mar. 1999.

[24] , “Fifth power-law circuits using junction field-effect transistors,”Electron. Lett., vol. 36, pp. 1442–1443, Aug. 2000.

[25] A. S. Sedra and K. C. Smith,Microelectronic Circuits. New York:Holt, Rinehart, Winston, 1987, pp. 268–269.

[26] “Field Effect Transistors in Theory and Practice,” Motorola, Inc.,Phoenix, AZ, Application Note AN211A, 1993.

[27] L. J. Sevin Jr,Field-Effect Transistors. New York: McGraw-Hill, 1965,p. 35.

[28] “Discrete Semiconductor Products—Diode, Bipolar Transistor, andJFET Products Databook,” National Semiconductor Corp., Santa Clara,CA, 1996. National Semiconductor Corp..

[29] “Mathematica,” Wolfram Research, Inc., Champaign, IL, 1993. Wol-fram Research, Inc., Version 2.2.

A Neural Network for Constrained Optimization WithApplication to CDMA Communication Systems

R. Fantacci, M. Forti, M. Marini, D. Tarchi, and G. Vannuccini

Abstract—This brief proposes a neural network for the solution in realtime of a class of quadratic optimization problems with equality and in-equality constraints arising in code-division multiple access (CDMA) com-munication systems. The network, which is derived via a nonobvious mod-ification of the circuit for nonlinear programming introduced by Kennedyand Chua, is shown to be globally asymptotically stable, and as such is ableto compute the global optimal solution in real time, without the risk of spu-rious responses. Computer simulations are presented to verify the neuralnetwork optimization capabilities and speed, and the performance in theapplication to CDMA communication systems.

Index Terms—Code-division multiple access (CDMA) communicationsystems, constrained optimization problems, neural networks.

I. INTRODUCTION

One of the most promising techniques for simultaneous transmissionof multiple users in wireless communication systems, is code-divisionmultiple access (CDMA) [1]. The performance of a CDMA system is

Manuscript received June 6, 2001; revised September 19, 2002. This paperwas recommended by Associate Editor P. Kennedy.

R. Fantacci, M. Marini, D. Tarchi, and G. Vannuccini are with the Diparti-mento di Elettronica e Telecomunicazioni, Università di Firenze, Firenze 50139Italy.

M. Forti is with the Dipartimento di Ingegneria dell’Informazione, Universitàdi Siena, 53100 Siena, Italy.

Digital Object Identifier 10.1109/TCSII.2003.814805

essentially degraded by the multiple-access interference (MAI) causedby the presence of simultaneous users. Hence, methods for MAI attenu-ation are of fundamental importance [1]–[4]. Also, MAI is rapidly timevarying, due to the time variation of both the number of transmittingusers and channel propagation conditions (i.e., transmission multipathand fading) [3], [4].

A basic approach to mitigate MAI effects in CDMA systems is blindadaptive interference suppression [2], which relies on the use within thereceiver of an adaptive filter for MAI attenuation. From a mathemat-ical viewpoint, the adaptive filter proposed in [2] is designed via theoptimization of the mean energy at the filter output, subject to suitableconstraints. Such an optimization problem is convex (see [2, Sec. II]),and the commonly employed algorithms for solving the problem arethose based on the stochastic gradient descendent rule [1], [3]. How-ever, as it was pointed out in [3], the main drawback of these sequentialalgorithms is that their convergence is too slow with respect to the timevariations of MAI. This in turn impairs their practical applicability toactual wireless CDMA communication systems. One could also applyother methods [5] for solving convex optimization problems, such asinterior point algorithms. However, it is expected that those algorithmsare too complex to implement on mobile user terminals, due to the strin-gent limitations on the hardware.

In this brief, we theoretically investigate the possible use of a neuralnetwork approach to solve the constrained optimization problemarising in blind adaptive interference suppression. The goal is toexploit the real time optimization capabilities of neural networks inorder to significantly improve the optimization speed with respect toexisting sequential algorithms.

To achieve the previous goal, a special neural network is introduced,which derives from a nonobvious modification of the neural networkfor nonlinear programming proposed by Kennedy and Chua in [6]. Theproposed neural network is realizable as a relatively simple analog cir-cuit [6], and can be implemented in principle on mobile user terminalsin CDMA systems.

More specifically, the optimization problem at hand involves bothinequality and equality constraints. We recall that the neural networkin [6] was conceived for optimization in the presence of inequalityconstraints, only. Though an equality constraint can be mathematicallybrought back to a pair of simultaneous inequalities, there are technicalproblems for the implementation. In fact, this would require the use oftwo inverted diodes, which could not work properly in practice [7]. Anoriginal technique is thus proposed in this paper to exactly satisfy therequired equality constraints, which is based on projecting the gradientof the energy function onto the space where the equality constraints aresatisfied. This leads to the definition of a new class of neural dynamicalsystems which has potential applications also to solve other optimiza-tion problems. We refer the reader to [8] and [9], and their references,for other applications in the telecommunications field where the use ofneural networks has already proven effective.

II. OPTIMIZATION PROBLEM FORMULATION

The theory of blind interference suppression has been developed in[2], see also [1]. From a mathematical point of view, the optimal adap-tive filter coefficients in a blind CDMA receiver are obtained via theminimization of the mean energy at the filter output. If the mean isevaluated over a window of bits of lengthL, in the genericith bit it isrequired to minimize the function [2]

E(x) =1

L

L�1

j=0

hy[i� j]; x+ si2 (1)

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