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978-1-4244-2332-3/08/$25.00 © 2008 IEEE

A Wide Band CMOS Differential Voltage-Controlled Ring Oscillator

Luciano Severino de Paula1, Sergio Bampi2, Eric Fabris1, Altamiro Amadeu Susin1,2

Federal University of Rio Grande do Sul - 1 DELET, 2 PGMICRO – Porto Alegre – Brazil

lspaula, bampi, fabris@inf.ufrgs.br, susin@eletro.ufrgs.br

Abstract — This paper presents the design of a wide band two-stage CMOS voltage-controlled ring oscillator based on the Maneatis cell. The VCO is designed for a frequency synthesizer module that generates local oscillation (LO) frequencies over a large bandwidth, targeting a multi-band acquisition system. The goal is a wide operating frequency tuning range of 400MHz – 1.4GHz in the VCO with low power consumption, -80 dBc/Hz@600KHz phase-noise performance and a good linearity for the frequency and control voltage characteristics. Simulation results verify the theoretical development and measurement results validate the design. The symmetric load transistor operation region controls the frequency behavior achieved by the VCO, which shows a monotonic relation with the control voltage when the loads are operated in saturation. The prototype chip was fabricated using a 0.18µm IBM CMOS technology.

Index Terms — Wide-band oscillators, Frequency Synthesizer, SSB Mixer, Voltage-Controlled Oscillator.

I. INTRODUCTION

One of the key blocks in a communication system is the frequency synthesizer; which is done mostly by using phase-locked loop (PLL) systems. A PLL system is composed of a phase detector, low pass filter and a voltage-controlled oscillator, as in Fig. 1.

Fig. 1. A typical PLL system

The action of the feedback in the loop causes the output frequency to be N times the reference input frequency of In(t) , usually a very stable, lower-frequency crystal oscillator. The spectral purity of the synthesized signal will largely depend on the quality of the VCO signal [1].

In actual communication systems there is a clear trend towards the full integration of the system into a single die for reasons of low cost and power consumption [2]-[5]. Since most of the CMOS transceivers incorporate the VCO active circuitry on the die, they are designed in a frequency range for which an external LC tank is avoided. On the other hand, large time constants required for the

loop filter generally lead to large external capacitors. As an alternative, a ring oscillator can be integrated in a standard CMOS process without any extra processing steps because it does not require any passive resonant element. In addition, when the ring oscillator is employed for a VCO, the desired wide operating-frequency range can be easily obtained but with the drawback of poorer phase-noise performance than the LC tank oscillator because of its low effective quality factor [6].

This paper describes the design and measurement of a CMOS ring VCO. It was designed and fabricated for an IBM 180 nm CMOS 7RF process, and it oscillates from 394 MHz to 1.417 GHz with a single 1.8V supply.

The paper is organized as follows: in section II the detailed circuit of the proposed delay cell is presented, while in section III the design is stated. The simulation and measurement results of the VCO are described in section IV and concluding remarks follow in section V.

II. CIRCUIT DESCRIPTION

For the delay cells proposed in this work we provide the necessary bias condition for the circuit to oscillate by means of positive partial feedback [7] generated by M1f and M2f, as depicted in Fig. 2.

In the upper portion of the circuit, we have M3 and M4 or M5 and M6, that implement a voltage controlled symmetrical load modifying the delay when the control voltage 'cV is changed, thus controlling the frequency. The use of this type of load allows reducing the sensitivity to variations in common mode and also the phase-noise of the circuit [8]. In the proposed VCO, the operating frequency is determined by the number of delay cells in the loop. The total capacitance and resistance associated to the output nodes depends on the operating regions of the transistors in the delay stages.

The biasing scheme composed by transistors M8 to M13 provides a controlled bias current and a controlled voltage 'cV in such a way that the transistors M4 and M5 stay in the saturation region for the whole control voltage range. This arrangement also avoids the cells to loose gain by maintaining a linear relation between the control

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voltage cV and the tail current provided to the cells by M7. Transistor M10 allows a minimum to be established current for the delay cells even if the control voltage leaves its nominal values of +0.9V to -0.9V.

Fig. 2. Proposed VCO circuit

Considering transistors M4 and M5 in their saturation region, the small signal model of the transistors can be used to analyze the circuit, as stated in Fig. 3.

Fig. 3. Small signal model of the circuit

From Fig. 3 one can derive the resistance and capacitance at the output node of the circuit, as shown in equation (1) and (2).

1243

1//1//1//1gdsgmgdsgm

Rf

OUT −= (1)

fgbfgdfgsfdbfgd

bsgsbsgsdbgdOUT

CCCCC

CCCCCCC

11122

443311

+++++

+++++= (2)

To Cout should be added the buffer capacitances C1, C2, C3, C4. The frequency behavior of the VCO is determined by the inverse relationship to the delay of each cell, which is CR ⋅=τ . In this case, the control acts on R variable, modifying the output conductances of transistor M4 and M5 through the variation of voltage Vc’.

III. DESIGN METHODOLOGY

A large frequency range and large supply noise immunity were considered for the design of the VCO. We sized the transistors according to the gm/ID methodology [9]. In this method, the relationship between the gm/ID ratio and the normalized drain current ID/(W/L) is taken as a fundamental design relationship to explore the design space.

The design procedure is as follows:

• The physical parameters of the VCO to be found in the design flow are the sizes of the PMOS and NMOS transistors. It is important to consider the parasitics related to the signal lines and output load capacitance of the VCO; • The characteristic of the transconductance-to-current ratio is obtained through electrical simulation using Cadence Spectre™, and by test devices we measured. The plot showed in Fig. 4 compares simulated and measured (for L=180nm devices). This curve is a characteristic curve that depends mainly on the technology, and covers all MOSFET regimes (strong, moderate and weak inversion);

Fig. 4. PMOS and NMOS gm/ID curve – Measured vs. simulated. W=1µm L=0.18µm

• Considering a Slew Rate of 10% of the total period of the maximum generated frequency, the calculated bias current is mAI 27 = . As the ring oscillators are very noisy, a design setting M7 and M8 transistors in moderate inversion is proposed. In this case, the influence of the noise is diminished increasing the flat band as power consumption increases a little. Thus, the choice

is 108,7=⎟

⎠⎞⎜

⎝⎛

Dm

Ig ;

• As the current through M7 is divided equally between the two sides of the delay cell and considering that the gain of the delay cell must be more than the unary to satisfy the Barkhausen criteria, the mg of the transistors M1 and M2 can be obtained as pgm Cg ω⋅= 2,12,1 . The result is

42,1=⎟

⎠⎞⎜

⎝⎛

Dm

Ig ;

• The symmetric load transistors should operate in strong inversion to minimize the influence of source noise,

therefore 46,5,4,3=⎟

⎠⎞⎜

⎝⎛

D

mI

g ;

• The aspect ratio of the current mirrors composed by M7-M8 and M9-M12 are 10 and 3 respectively.

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Considering the currents in each mirror and the bandwidth, all other transistors are sized; • In this design we sized appropriately an output buffer (shown in layout Fig. 5) to have an output impedance of 25Ω and a driver current of 20mA; • All the transistor lengths are set to minL to minimize thermal noise; • Finally, manual corrections after parametric simulations were made to fine-tune the VCO into the specified target parameters.

The final sizes of the VCO devices obtained using the method above are shown in Table I.

TABLE I. MOS DEVICE SIZES FOR THE VCO

Device W/L M1, M2 40 M3 – M6, M13 55.56 M7 555.6 M8,M10 27.78 M9 83.33 M11 444.44 M12 138.89 M1f, M2f 38.89

IV. SIMULATION AND MEASUREMENT RESULTS

The circuit was simulated, providing preliminary results, and laid out for IBM 180nm rules. The layout of the VCO is shown in Fig. 5. In this figure, MB1 to MB6 are the buffer transistors and CBxy (x=1,2 y=e,d) are the stages coupling capacitors of the buffer circuit. The use of minimum channel length to minimize the associated capacitances to the output nodes is important. Also the metal tracks that connect the VCO to the buffer have balanced and symmetrical sizing for the differential outputs.

Fig. 5. VCO layout

A test chip with the VCO and other modules of the mixed-signal interface proposed by [6] was fabricated. The PCB shown in Fig. 6 is a test-bed for the necessary test setup to measure the VCO, including balloon isolation, power provided by batteries, and impedance matching of micro-strips to the measurement instruments.

Fig. 6. PCB photograph

Fig. 7. Output VCO Frequency Spectrum

Fig. 7 shows the output spectrum at 1.424Ghz measured with a Rhode & Schwarz analyzer. All the signals in the vicinity of the center frequency, considering the whole bandwidth of the signal, have amplitudes lower than the center frequency. The phase noise behavior of the VCO simulated by SPECTRE® is shown in Fig. 8, where the VCO is operating at a frequency of 1.41GHz. In the same figure, the predicted results obtained through analytical model proposed by [10] is shown. In the model calculation, the parameters inside the left bottom square of fig. 8 were used.

Fig. 8. Phase noise of the VCO as a function of the off-set frequency.

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Fig. 9 shows the relationship of the operation frequency of the VCO and the control voltage cV . The simulated data is plotted against the measured data obtained from three chip samples manufactured and packaged through MOSIS.

Also in Fig. 10 the power consumption of the VCO (excluding the buffer) related to the control voltage is shown against the measured data. The simulation results show that if the transistors M4 and M5 are equal in size to M3 and M6, the whole voltage control range is restricted to operate in the saturation region, because of the bias scheme we designed.

Fig. 9. Frequency of the VCO vs. control voltage Vc

Fig. 10. Power consumption of VCO vs. control voltage Vc

Table II shows the simulation and measured results for the VCO.

V. CONCLUSIONS

The design of a wide frequency range VCO was detailed in this work. The maximum power consumption

of the circuit is 12.5mW with good linearity over the tuning range. The gm/Id design methodology was employed to adequately size the devices.

TABLE II. SIMULATION AND MEASUREMENT RESULTS

Parameter Specs Simulation Measurement Output Frequency

(GHz) .44 – 1.34 .39 – 1.41 .4 – 1.5

Phase Noise (dBc/Hz@600KHz)

<-80 -89,79 -

Central Frequency (MHz)

890 ≅900 ≅900

Tunning range (%) >101,1 113 118 Power Consumption

(mW) <20 <16 <12.5

ACKNOWLEDGEMENT

The support of CNPq and CAPES Brazilian agencies with scholarships and PDI-TI Program grant are gratefully acknowledged, as well as the valuable MOSIS support.

REFERENCES [1] W. F. Egan, “Frequency Synthesis by Phase Lock,” New York:

Wiley, 1981. [2] K. Irie, H. Matsui, T. Endo, K. Watanabe, T. Yamawaki, M.

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[4] G. C. Dawe, J.-M. Mourant, and A. P. Brokaw, “A 2.7-V DECT RF transceiver with integrated VCO,” in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 1997, pp. 308–309.

[5] R. G. Meyer, W. D. Mack, and J. J. Hageraats, “A 2.5-GHz BiCMOS transceiver for wireless LAN,” in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 1997, pp. 310–311.

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[7] E. Wang and R. Harjani, “Partial Positive Feedback for gain Enhancement of Low-Power CMOS OTAs”, Analog Integrated Circuits and Signal Processing, 8, pp21-35, 1995.

[8] J. Maneatis and M. Horowitz, “Precise delay generation using coupled oscillators,” IEEE J. Solid-State Circuits, vol. 28, No. 12, pp. 1273-1282, Dec 1992.

[9] F. Silveira, D. Flandre, P. G. A. Jespers. A gm/ID Based Methodology for the Design of CMOS Analog Circuits and Its Application to the Synthesis of a Silicon-on-Insulator Micropower OTA. IEEE Journal of Solid-State Circuits, vol. 31, no. 9, September 1996.

[10] A. Abidi, “Phase noise and jitter in CMOS ring oscillators,” IEEE J. Solid-State Circuits, v. 41, n. 8, pp. 1803-1816, Aug 2006.