ISOCC 2016

“This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MSIP) (No.2015R1A2A1A13001751).”

A Test Methodology to Screen Scan-Path Failures

Junghwan Kim, Young-woo Lee, Minho Cheong, Sungyoul Seo and Sungho Kang Department of Electrical & Electronic Engineering

Yonsei University Seoul, Korea

{kjhcz, roberto, cmh9292, sungyoul}@soc.yonsei.ac.kr and shkang@yonsei.ac.kr

Abstract— It is important to screen scan-path failures because scan-path failures affect product yield even though these are not related to the device functional operations. However, the additional efforts such as diagnosis are required to screen scan-path failures. In this paper, we propose a new test methodology to screen scan-path failures under the Automatic-Test-Pattern-Generation (ATPG) constraints and the multi-capture-clock condition without diagnosis. Experimental results show that the proposed methodology efficiently screens scan-path failures with high test coverage.

Keywords; scan-path failure; diagnosis

I. INTRODUCTION

Nowadays, a scan-based testing is a widely used methodology for the higher test coverage and the faster test time. The number of scan chains in Very-Large-Scale-Integrated (VLSI) circuits increases proportionally to gate counts and it is reported that 10% to 30% of all defects cause the scan chains to fail, the scan chain failures account for almost 50% of chip failures [1]. However, if there are scan chain failures, these are not always related to the device functional operations. It depends on the fault location such as the internal of flip-flop or the scan-path; scan-path failures are defined as the scan chain failures but not the functional failures, as shown in Figure 1. In order to screen scan-path failures, the detection of the fault location is required. Many diagnosis techniques have been researched to find the fault locations efficiently. Commonly, the diagnosis techniques are classified into the hardware-assisted, the software-based and the signal profiling [2]. However, these have the following drawbacks. The hardware-assisted diagnosis requires the additional hardware overhead, and the software-based diagnosis needs the additional simulation time. Lastly, the signal profiling diagnosis can find the most accurate the fault location, but it requires the high cost equipment and the long analysis time. Therefore, the objective of this paper is to screen scan-path failures without diagnosis.

II. PROPOSED METHODOLOGY

Normally, a scan-capture vector is not executed, if the scan chain has a failure, because a capture operation is affected by the shift operations in any scan chains. In the proposal, in order to screen scan-path failures, a specific capture vector is executed even though the scan chain has a failure. Furthermore, a test flow with the specific capture vector is proposed.

A. Concept of the proposed vector

For the proposed vector, the first step is to find the failed scan chain. It is reasonable to assume that there is only a failed scan chain at a time. There is a simple way to find it with the chain-check vector. Most of ATPG tools support to generate the chain-check vector without the scan-capture operation. Each scan chain has its own scan-in/out pins, respectively. So it is possible to detect which scan chain is failed by analyzing the test result from the scan-out pin using the Automatic-Test-Equipment (ATE). After finding the failed scan chain, it is stored in the ATE memory. Next, it is necessary to generate the specific capture vector called the screening vector using the ATPG tool in order to distinguish scan-path failures from the scan chain failures; the state of flip-flops of the failed scan chain can be observed even though the scan-path is not tested by the screening vector. The scan-in data cannot be loaded into all the flip-flops of the failed scan chain under the SI-Mask constraints. The definition of SI-Mask constraints is that all values of the Q-to-SI path replace with the “X” value. D-ports and Q-ports should not have any constraints to make capture operation free. Normally, a capture vector is generated by the ATPG tool under the single-capture-clock condition. However, the state of flip-flops of the failed scan chain cannot be observed because of the SI-Mask constraints under the single-capture-clock condition. In contrast, the multi-capture-clock vector can solve this problem. Figure 2 represents the comparison of the data route between two vectors when the chain-2 is failed, as an example. The value of the 2-C (flip-flop) is captured from the 1-B at a capture-clock. After the capture operation, the value of the 2-C is shifted to the 2-D and it is changed to the “X” value because of the SI-Mask constraints. So it is not possible to observe the state of 2-C under the single-capture-clock condition. Under the multi-capture-clock condition, the value of 2-B which is captured from the 1-A sequentially transfers to the 3-C at the second-capture-clock. Therefore, it is possible to observe the state of 2-B through the chain-3 although the chain-2 has the SI-Mask constraints.

Figure 1. Scan failure according to the fault location

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ISOCC 2016

B. Concept of the proposed test flow

The proposed test flow is shown in Figure 3. At first, the screening vector sets which correspond to all of the scan chains are required before the test. Initially, the chain-check vector set is executed. If the chain-check vector set is passed, the normal capture vector set is executed. If the chain-check vector set is failed, the failed scan chain is detected through the failed scan-out pin using the ATE. After that, the screening vector set which corresponds to the failed scan chain is executed. If the screening vector set is passed, it means the failure location is in the scan-path and it does not affect the functional operations. Conversely, if the screening vector set is failed, the fault location is in the internal of flip-flops and it affect the functional operations.

III. EXPERIMENTAL RESULTS

In the proposed vector, long scan chain needs more the number of SI-Mask constraints. Normally, test coverage decreases if the vector has too many constraints. Therefore, the test coverage of the proposed vector according to the scan chain length is confirmed in this experiment. Table 1 shows the experimental results using the benchmark circuit B19 by Synopsys TetraMAX. The columns of each constraint show the test coverage. When the scan chain length decreases, the test coverage increases because the number of flip-flops of the failed scan chain decreases. When the number of flip-flops under these constraints is less than 1.4% of total flip-flops counts, and the test coverage is reached to 98%.

In order to confirm the number of cycles, additional experiment is performed. The proposed vector set needs more test cycles than normal vector set in general. There are two reasons. First the ATPG tool makes more vectors than the normal vector set to satisfy the higher test coverage. Secondly, the addition of multi-capture cycles into a test vector causes a slight increase in test cycles [3]. Table 2 shows the comparison of test cycles between two kinds of vectors.

The proposed vector needs 2.4% more test cycles than normal vector. Also, all of test cycles can be wasted because the proposed methodology cannot salvage all of the scan chain failures. Although the proposed requires more test cycles as shown in Table 2, the main advantage is that some failed chips can turn into optional good chips without the extra diagnosis time. For the case of 70 scan chains and 95 scan chain length, 9.5 % of total area is accounted for by the scan-path. Assuming that there are the uniformly defects, 9.5% of failed chips can be usually turned into optional good chips. For example, if there are 100 failed chips, 9.5 chips can be salvaged and if there are 1000 failed chips, 95 chips can be salvaged. In other words, the more scan chain failures increase, the more the proposed methodology can be effective.

IV. CONCLUSION

In this paper, a new test methodology that can screen scan-path failures without diagnosis is proposed. The experimental results show that as the scan chain length decreases and the number of scan chain failures increases, the proposed methodology becomes more efficient. It can be a practical solution if the diagnosis time is taken into consideration.

REFERENCES [1] Y. Huang, R. Gui, W-T. Cheng and J. C-M. Li, “Survery of Scan Chain

Diagnosis.” IEEE Trans. Design and Test of Computers, vol.25, no.3, pp. 240–248, 2008.

[2] Helen-Maria Dounavi and Yiorgos Tsiatouhas, “Stuck-at Fault Diagnosis in Scan Chains,” in Proc. Design & Technology of Integrated Systems In Nanoscale Era (DTIS), pp.1-6, 2014.

[3] Gaurav Bhargava, Dale Meehl and Jamse Sage, “Acheving serendiptous N-detect mark-offs in Multi-Capture-Clock scan patterns,” in Proc. International Test Conference, pp. 1-7, 2007.

Figure 2. Data route of the two vectors

Figure 3. Test flow of the proposed methodology

TABLE II. THE COMPARISON OF TEST CYCLES

Normal vector

No constraintChain-1 SIconstraint

Chain-2 SIconstraint

Chain-10 SIconstraint

Chain-20 SIconstraint

Average

4/1649 2,020,391 1,889,905 1,808,970 - - 1,849,43810/660 794,271 837,375 775,084 1,037,633 - 883,36420/330 397,932 397,282 404,631 427,582 478,525 427,00530/220 271,164 274,526 269,196 268,060 278,989 272,69340/165 203,277 209,682 204,133 208,166 199,759 205,43550/132 163,750 165,791 165,929 161,349 176,462 167,38360/110 137,743 140,471 139,453 140,132 143,077 140,78370/95 118,576 122,325 127,023 125,751 128,809 125,977

The numberof chains /

Chain length

The number of test cyclesProposed vector (multi-capture-clock)

TABLE I. THE COMPARISON OF TEST COVERAGE

Normal vector

No constraintChain-1 SIconstraint

Chain-2 SIconstraint

Chain-10 SIconstraint

Chain-20 SIconstraint

Average

4/1649 74.11% 70.50% - - 72.31%10/660 87.62% 87.19% 80.51% - 85.11%20/330 93.44% 87.94% 90.35% 87.79% 89.88%30/220 93.73% 92.38% 94.59% 94.96% 93.92%40/165 97.10% 94.03% 93.93% 94.05% 94.78%50/132 97.47% 94.13% 93.50% 96.26% 95.34%60/110 97.68% 94.19% 95.31% 98.46% 96.41%70/95 97.83% 97.81% 98.91% 98.57% 98.28%

The numberof chains /

Chain length

Test coverage (%)Proposed vector (multi-capture-clock)

99.40%

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