a single-chip 802.11a mac/phy with a 32-b risc processor ...chong/290n-f07/80211a.pdf · the newly...

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 11, NOVEMBER 2003 2001

A Single-Chip 802.11a MAC/PHYWith a 32-b RISC Processor

Toshio Fujisawa, Jun Hasegawa, Koji Tsuchie, Tatsuo Shiozawa, Tetsuya Fujita, Toshitada Saito, and Yasuo Unekawa

Abstract—An 802.11a compliant medium access control (MAC)and physical layer (PHY) processing chip has been successfullyfabricated in 0.18- m CMOS. Thirty million transistors areintegrated on a 10 91 10 91 mm2 die housed in a 361-pinPFBGA. The MAC functions are fully implemented by firmware onan embedded 32-b RISC processor, 4-Mb SRAM, and hardwareacceleration logic. The PHY supports a complete set of datarates up to 54 Mb/s. Immediate PS-Poll response is realized bythe hardware-centric architecture, which can reduce the powerconsumption of the baseband chip and external RF/IF chips by29% in power-save mode. The newly developed hybrid automaticgain control circuit can adjust receive signal strength to 1 dBwithin 2 s. Required carrier-to-noise ratio is lower than 4.9 dBat 6-Mb/s data rate and 21.7 dB at 54-Mb/s data rate.

Index Terms—Adaptive equalizers, carrier sense multiaccess,gain control, orthogonal frequency division multiplexing, signalprocessing, wireless LAN.

I. INTRODUCTION

M OBILE computing using wireless LAN is becomingincreasingly popular. Since the 2.4-GHz band is used

by the IEEE 802.11b, Bluetooth, and consumer productssuch as microwave ovens, it is presumed that the popularityof the 2.4-GHz band will soon result in intolerable levels ofinterference for users. Consequently, demand for the IEEE802.11a using the 5-GHz clear band is increasing.

The 802.11a enables high-speed data links up to 54 Mb/s [1],[2]. However, one of the main disadvantages of 802.11a is itshigh peak-to-average-power ratio. The transmitters, therefore,require very linear output amplifiers with wide dynamic range,which shortens battery life. In addition, multipath is anotherproblem peculiar to mobile communication. Multipath causesfrequency selective distortion in the receive signal. The distor-tion increases packet error rate and, therefore, reduces the datarate for communication.

Several attempts have been made so far to cope with theseproblems concerning power consumption and receive per-formance. For example, the physical layer (PHY) is partlydisabled while it is not in the transmit or receive states to reducethe power consumption [3]. Though disabling other functionalblocks such as the medium access control (MAC) or RF/IFmodule at the same time would be more effective, it becomesunable to detect incoming signals while the RF/IF module isdisabled. This means that the RF/IF module, analog-to-digital

Manuscript received April 11, 2003; revised July 8, 2003.The authors are with the SoC Research and Development Center,

Toshiba Corporation, Kawasaki 212-8520, Japan (e-mail: [email protected]).

Digital Object Identifier 10.1109/JSSC.2003.818135

Fig. 1. Block diagram of the 802.11a MAC/PHY LSI.

(A/D) converters, digital-to-analog (D/A) converters, PHY, andMAC should not be considered separately in order to achievelower power consumption.

In another example, phase noise caused by frequency differ-ence between transmitter and receiver is compensated to im-prove receive performance [4], where all four pilot subcarriersare employed to estimate frequency offset and clock phase error.However, in the case where part of the pilot subcarriers aredistorted severely, phase errors cannot be measured accurately.Consequently, packet error rate is increased.

In this paper, three new techniques, which are the power-saving architecture, fast and accurate automatic gain control(AGC), and correct channel estimation and equalization, forsolving these problems will be proposed.

II. A RCHITECTURE

A. Block Diagram

Fig. 1 illustrates the block diagram of the 802.11a MAC/PHYLSI. It contains a CPU block, a 2-Mb program memory,MAC/PHY hardware, and a 2-Mb frame memory. The programmemory stores instructions that the CPU uses for processingdata. The program memory is also used as a stack area, bufferarea, or statistical information area. The CPU manages theconnections, statistical information, power-saving state, and soon. The frame memory is used by the MAC hardware, which

0018-9200/03$17.00 © 2003 IEEE

2002 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 11, NOVEMBER 2003

Fig. 2. Block diagram of the Tx-MAC.

stores transmitting and received frames. Large-size framememory is adopted so that the MAC hardware can buffer dataframes for stations in power-saving mode. Since the CPU andthe MAC hardware have their own memory for program andframe buffering separately on chip, they can efficiently accessthe memories. This architecture realizes a 54-Mb/s data ratewhen the MAC hardware operates at 40 MHz.

B. Tx-MAC

A block diagram of the transmit (Tx) MAC is shown in Fig. 2.The Tx-MAC implements the power-save mode specified in802.11. Stations in power-save mode are “dozing” while they donot have data to be transmitted, and become “awake” at inter-vals of several hundred milliseconds to receive beacons whichare sent from an access point (AP). The beacon includes a trafficindication map (TIM), which indicates the existence of buffereddata in the AP. When the power-save mode station realizes nobuffered data addressed to itself by analyzing the TIM, it returnsinto doze state immediately.

When a power-save mode station is notified that dataframes for the station are stored at an AP, the station willsend a power-save-poll (PS-Poll) frame to request that the APdeliver the buffered data frame. The station is kept waiting infull-power operation until the arrival of the data frame. Thismeans that quick delivery of data is required in order to reducethe station’s power dissipation. The Tx-MAC stores dataframes separately for each destination address. When receivinga PS-Poll frame from a station, the AP immediately releasesthe data frame addressed to the station. This hardware-centricarchitecture enables the AP to quickly respond and, therefore,shortens the time during which the power-save mode stationshould be awake.

C. Implementing Immediate PS-Poll Response

The 802.11 standard specifies two types of frame sequencesconcerning PS-Poll, which are referred to as a deferred PS-Pollresponse and an immediate PS-Poll response. In the deferredPS-Poll response, an AP first responds with an acknowledgment

(ACK) frame and then responds with a buffered data frame afterperforming a backoff procedure. In the immediate PS-Poll re-sponse, an AP responds to the PS-Poll frame with a buffereddata frame in a minimum interframe space. The minimum inter-frame space specified in 802.11a is 16s. The conventional ar-chitecture is not able to realize the immediate PS-Poll responsebecause it takes over 50s for the CPU to respond to the arrivalof the PS-Poll frame.

The developed hardware-centric architecture realizes im-mediate PS-Poll response. As Fig. 3 illustrates, the frameexchange sequence using immediate PS-Poll response is atleast 29% faster than that using deferred PS-Poll response. Indoze state, the baseband chip disables external RF/IF chips,internal A/D converters, and D/A converters. The currentdesign of the baseband chip also allows the gating of the mostpart of the functional blocks except for a timer circuit. The nextawake time is determined by the timer circuit instead of bymonitoring incoming signals. Because the power consumptionin the baseband chip and external RF/IF chips is negligible indoze state, 29% power reduction can be achieved by shorteningthe length of the awake state by 29%. The values of randombackoff written in Fig. 3 are obtained in the no-contention case.The backoff value increases exponentially after each failedretransmission, therefore, the difference between “deferred”and “immediate” increases with the number of stations in thenetwork. The quick response reduces the power consumptionof every power-save mode station in the network.

III. AGC CIRCUIT

A. Conventional AGC Approach

An 802.11a receiver should receive signals whose dynamicrange is over 50 dB. To correctly receive these wide dynamicrange signals, an A/D converter with large bit width is needed.Because of cost and power dissipation, however, the A/D con-verter with adequate bits is used in combination with a gain con-trol circuit. To adjust the receiver amplifier’s gain, an analog re-ceive signal strength indicator (RSSI) circuit is used convention-

FUJISAWA et al.: SINGLE-CHIP 802.11a MAC/PHY WITH A 32-b RISC PROCESSOR 2003

Fig. 3. Two types of PS-Poll response.

Fig. 4. Conventional AGC approach.

ally as shown in Fig. 4. One problem of the analog RSSI circuitis that it does not provide precise outputs. To precisely controlthe gain, a large time constant capacitor is needed. The 802.11apreamble duration is 16s, which is used for various receiveprocess such as signal detect, AGC, diversity selection, timingsynchronize, and channel and frequency offset estimation. Only5 s is allowed for the first three processes. When receive signalstrength is measured twice for antenna diversity selection, AGCand antenna selection should be conducted twice within 5s.For these reasons, it is necessary to conduct precise AGC within2 s.

B. Hybrid AGC Circuit

The developed AGC circuit achieves quick and precise AGCby controlling the gain in two steps. First, the analog RSSI cir-cuit operates as shown in Fig. 5(a). The analog RSSI circuit de-tects the signal and then informs the ripple cancellation com-

parator of the strength. The ripple cancellation comparator clas-sifies them into four classes of intensities. The intensities areinput to the D/A converter in the AGC signal generator and thenthe gain control signal for the IF amplifier is generated. Thecoarse-grained gain control has finished.

Second, the digital RSSI circuit operates as illustrated inFig. 5(b). The digital filter removes unnecessary frequencyingredients from the signal output from the A/D converters.Then the integrator integrates the signal and precisely calculatesthe average signal strength. The signal strength is input tothe D/A converter in the AGC signal generator and then thegain control signal for the IF amplifier is generated again. Thefine-grained gain control has finished. Thus, quick and preciseAGC is realized by using both analog and digital RSSI circuits.

An I/O macro including the ripple cancellation comparatoris newly designed. Fig. 6 depicts the block diagram and theschematic of the ripple cancellation comparator. The referencevoltages are given to REF1, REF2, and REF3 pins in decreasing


(a)

(b)

Fig. 5. (a) Coarse-grained gain control with analog RSSI measurement. (b) Fine-grained gain control with digital RSSI measurement.

Fig. 6. Ripple cancellation comparator.

order. The analog RSSI circuit output is connected with A1, A2,and A3 pins. Three comparators output “high” when the input

signal is above each threshold setting. The comparator outputsshould be kept constant until the fine-grained gain control has


Fig. 7. Hybrid AGC circuit measurement.

Fig. 8. Block diagram of a conventional equalizer.

finished, because comparator output’s instability affects the op-eration of the fine-grained AGC. Therefore, the comparator hasthe hysteresis characteristic that is 100-mV wide, and it preventsthe ripples from entering the internal circuits.

C. Measured Result

Fig. 7 shows a measured result of the developed hybrid AGCcircuit. The figure plots the variations in the A/D converter’soutputs as a function of the receive signal strength. The opencircles represent the A/D converter’s outputs after the coarse-grained AGC. The A/D converter output increases linearly andthe values are on four slanting lines. The receive signal strengthis divided into four regions and the range is limited to 18 dB bythe coarse-grained gain control using the analog AGC circuit.The closed circles represent the A/D converter’s outputs afterthe fine-grained AGC. The A/D converter’s output is flat this

time. As shown here, the range of receive signal strength is ad-justed within 1 dB to a target level after the fine-grained gaincontrol using the digital AGC circuit.

The coarse-grained AGC takes 0.7s and the fine-grainedAGC takes 1.3 s (in total, 2.0 s). If the coarse-grained AGCis eliminated from this design, the fine-grained AGC shouldbe conducted four times in the worst case to cover the widedynamic range of the 802.11a signals. By combining the twotypes of AGC circuits, 2.0-s convergence time is achieved,which is small enough to complete antenna diversity selectionfor every incoming frame.

IV. A DAPTIVE EQUALIZER

A. Conventional Adaptive Equalizer

Fig. 8 shows a block diagram of a conventional equalizer,which consists of four functional blocks: a channel estimator,a channel equalizer, a phase-error detector, and a phase-error


Fig. 9. Block diagram of the developed equalizer.

Fig. 10. Means of estimating phase errors.

Fig. 11. PER versus CNR curves.

compensator. The channel estimator models a channel responseby comparing a preamble in a receive signal with a predeter-mined value. The channel equalizer equalizes the receive signalsby dividing them by the estimated channel response. The phase-error detector detects phase errors using the received four pilotsubcarriers. The phase-error compensator removes the phase

error from the receive signals by inversely rotating them by thequantity of the detected phase errors.

B. Developed Adaptive Equalizer

Fig. 9 illustrates the block diagram of the developed adaptiveequalizer, which has a feedback loop at the phase-error compen-


Fig. 12. Chip micrograph.

sator. The phase-factor calculator memorizes the ingredients ofthe phase error and applies them to the next symbol. Thus, thephase detector detects the difference from the previous phaseerror. This equalizer can accurately compensate phase errors be-cause it deals with a smaller range than the conventional equal-izer.

C. Method of Estimating Phase Error

Fig. 10 shows the method of estimating a phase error. A phaseerror contains the frequency offset and the clock phaseerror . rotates equally the phase of all subcarriers. Onthe other hand, rotates the phase in proportion to the sub-carrier frequency. Therefore, is obtained by averaging thephase errors of four pilot subcarriers and is determined bythe slope of a least-square straight line. A phase error is rectifiedby inversely rotating the signal by the quantities of estimated

and .The phase errors of all four pilot subcarriers are ideally put on

a straight line. However, the phase error may actually step outthe line if the pilot subcarrier is distorted severely in the wire-less transmission path. This affects accuracy of the phase-errorestimation and increases packet-error rates. The conventionalequalizer always uses all four pilot subcarriers. The developedequalizer removes obstructed subcarriers adaptively. Case 2 inFig. 10 illustrates the case where two pilot subcarriers are dis-torted severely. The pilot subcarrier with small intensity is notused for calculation of and . As shown in case 3,even when three pilot subcarriers are distorted severely, a mostlikely phase error can be estimated. Since this equalizer selectsthe pilot subcarriers for phase-error estimation, it provides higherror-correction ability in the radio environment.

D. Simulated Result

Fig. 11 plots the dependence of packet-error rates (PER) oncarrier-to-noise ratio (CNR). The table in Fig. 11 lists the CNRat 10% PER required by 802.11a standard and this chip, respec-tively. The chip requires smaller CNR at every data rate.

The required CNR in a typical office channel (ETSI-A model)has been also examined. Compared with the conventional equal-

TABLE ICHIP FEATURES

izer, the CNR required by the developed equalizer has been im-proved by 1.0 dB at 36-Mb/s, 1.3 dB at 48-Mb/s, and 0.4 dB at54-Mb/s data rates.

V. IMPLEMENTATION AND RESULTS

The chip micrograph is shown in Fig. 12. A 32-b CPU, 4-MbSRAM, PLL, double 10-b A/D converters for the receiver,double 10-b D/A converters for the transmitter, double 7-bD/A converters for the Tx and Rx AGC, and 1.3-million-gaterandom logics are integrated in 119 mm. Chip features aresummarized in Table I. The chip is fabricated with 0.18-msix-layer metal CMOS process and housed in a 361-pin plasticfine pitch BGA (PFBGA) package. The clock speeds are 20,40, and 80 MHz. It consumes 958 mW in total from 1.5-V,2.5-V, or 3.3-V supplies.

Fig. 13 shows constellation diagrams observed at the re-ceiver side chip. The constellation of binary phase shift keying(BPSK), quaternary phase shift keying (QPSK), 16 quadratureamplitude modulation (16-QAM), and 64 quadrature amplitudemodulation (64-QAM) are observed by using a test functionof the chip. The distance between the measured and the idealsymbol is called error vector magnitude (EVM). EVM encom-passes the effects caused by magnitude and phase distortions,which is the figure of merit for modulation accuracy in wirelesscommunications systems. The measured EVM in the receiverside chip at 64-QAM modulation is 28.1 dB, which is 3-dBbetter than the 802.11a requirement.

VI. CONCLUSION

A single-chip 802.11a MAC/PHY with a 32-b RISC pro-cessor has been successfully implemented in 0.18-m CMOS.The hardware-centric architecture can reduce the power con-sumption of the baseband chip and external RF/IF chips by morethan 29%. The hybrid AGC circuit adjusts the receive signalstrength to 1 dB within 2 s. The adaptive equalizer properlyestimates channel and compensates errors. The required CNRis 4.9 dB at 6-Mb/s data rate and 21.7 dB at 54-Mb/s data rate.These results show that the chip has the potential of being akey component of the various wireless communications systemsusing the 5-GHz band.


Fig. 13. Constellation diagrams at receiver side chip.

ACKNOWLEDGMENT

The authors wish to thank K. Toshimitsu, K. Sato,M. Namekata, T. Aikawa, and T. Furuyama for their en-couragement, suggestions, and support.

REFERENCES

[1] Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY)Specifications, Sept. 1999.

[2] Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY)Specifications: High-Speed Physical Layer in the 5 GHz Band, Sept.1999.

[3] P. Ryanet al., “A single chip PHY COFDM modem for IEEE 802.11awith integrated ADC’s and DAC’s,” inIEEE Int. Solid-State CircuitsConf. Dig. Tech. Papers, Feb. 2001, pp. 338–339.

[4] J. Thomsonet al., “An integrated 802.11a baseband and MAC pro-cessor,” inIEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb.2002, pp. 126–127.

Toshio Fujisawa was born in Kanagawa, Japan, onJanuary 3, 1969. He received the B.S. and M.S. de-grees in electronic engineering from the Tokyo Insti-tute of Technology, Tokyo, Japan, in 1993 and 1995,respectively.

In 1995, he joined the Microelectronics Engi-neering Laboratory, Toshiba Corporation, Kawasaki,Japan, where he was engaged in the research anddevelopment of ATM switch access LSI. Since 2000,he has been working on the design of basebandprocessors for wireless communications at the SoC

Research and Development Center.

Jun Hasegawa was born in Gunma, Japan, onNovember 28, 1968. He received the B.S. andM.S. degrees in physics from Shizuoka University,Shizuoka, Japan, in 1992 and 1994, respectively.

In 1994, he joined the Microelectronics Engi-neering Laboratory, Toshiba Corporation, Kawasaki,Japan, where he was engaged in the developmentof ATM switch access LSI. Since 2000, he has beeninvolved in the design of baseband processors forwireless communications at the SoC Research andDevelopment Center.

Koji Tsuchie received the B.S. and M.S. degrees inphysics from the University of Tokyo, Tokyo, Japan,in 1997 and 1999, respectively.

He joined the SoC Research and DevelopmentCenter, Toshiba Corporation, Kawasaki, Japan, in1999, where he is working on the research anddevelopment of VLSI design.

Tatsuo Shiozawawas born in Nagano, Japan, onSeptember 14, 1973. He received the B.S. and M.S.degrees in electronic engineering from HokkaidoUniversity, Sapporo, Japan, in 1998 and 2000,respectively.

In 2000, he joined the System ULSI Researchand Development Center, Toshiba Corporation,Kawasaki, Japan, where he has been engaged in theresearch and development of the design of basebandprocessors for wireless communications at the SoCResearch and Development Center.

Tetsuya Fujita was born in Tokyo, Japan, on August30, 1963. He received the B.S. degree in electronicengineering from Hosei University, Tokyo, Japan, in1986.

In 1986, he joined Toshiba Corporation, Kawasaki,Japan, where he was engaged in the establishment ofCMOS and ECL gate array libraries. Since 1996, hehas been with the Microelectronics Engineering Lab-oratory, Toshiba Corporation, where he has been in-volved in the research and development of commu-nication LSIs at the SoC Research and Development

Center. His current research interests include low-power low-voltage techniquesin CMOS.


Toshitada Saitowas born in Niigata, Japan, on Feb-ruary 11, 1961. He received the B.S., M.S., and Ph.D.degrees in electrical engineering from Keio Univer-sity, Yokohama, Japan, in 1983, 1985, and 1988, re-spectively. His Ph.D. work was on the transmissionsystem of the Acknowledging Ethernet.

From 1988 to 1990, he was a Research Assistantat Fukui University, Japan. In 1991, he joined theSemiconductor Device Engineering Laboratory,Toshiba Corporation, Kawasaki, Japan, where hewas engaged in the research and development of the

Token Ring network controller LSI, 155-Mb/s ATM SONET/SDH framingLSI, and 622-Mb/s ATM switch LSI chipset. Since 2000, he has been involvedin the design of baseband processors for wireless communications at the SoCResearch and Development Center.

Yasuo Unekawawas born in Hiroshima, Japan, onDecember 10, 1963. He received the B.S., M.S., andPh.D. degrees in electronic engineering from Univer-sity of Tokyo, Tokyo, Japan, in 1986, 1988, and 1991,respectively. His Ph.D. work was on thin-film fabri-cation process of high-Tc superconducting oxide.

In 1991, he joined the Semiconductor DeviceEngineering Laboratory, Toshiba Corporation,Kawasaki, Japan, where he was engaged in theresearch and development of 1-Mb synchronousTagRAM, 155-Mb/s ATM SAR (Segmentation And

Reassembly) chip, and 155/622-Mb/s ATM switch chipset. He is currentlymanaging wireless LAN LSI development in the SoC Research and Develop-ment Center.

a single-chip 802.11a mac/phy with a 32-b risc processor ...chong/290n-f07/80211a.pdf · the newly...

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