a self-aligned epitaxial regrowth process for subfor sub
TRANSCRIPT
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2010 Materials Research Society Spring Meeting, April 7, San Francisco
A Self-Aligned Epitaxial Regrowth Process for Sub 100 nm III V FETsfor Sub-100-nm III-V FETs
Mark Rodwell
A. D. Carter, G. J. Burek, M. A. Wistey*, B. J. Thibeault, A. Baraskar, U. Singisetti, J C S St A C G d C P l t
Mark. Rodwell, University of California, Santa Barbara
J. Cagnon, S. Stemmer, A. C. Gossard, C. PalmstrømUniversity of California, Santa Barbara*Now at Notre DameB Shi E Ki P C M I tB. Shin, E. Kim, P. C. McIntyreStanford UniversityY.-J. LeeI t lIntelB. Yue, L. Wang, P. Asbeck, Y. TaurUniversity of California, San Diego
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III-V MOS: What is needed ?
True MOS device structures at 10 nm gate lengths10nm gate length, < 10nm electrode spacings, < 10nm contact widths
True MOS device structures at ~10 nm gate lengths
< 3 nm channel, < 1 nm gate-channel separation, < 3nm deep junctions, g p , p jFully self-aligned processes: N+ S/D, S/D contacts
D i t >> 1 A/ i @ 1/2 V lt VDrive currents >> 1 mA/micron @ 1/2-Volt Vdd.Low access resistances. Density-of-states limits.
Dielectrics: < 0.6 nm EOT , Dit < 1012 /cm2-eV y
impacts Ion, Ioff , ...
...and the channel must be grown on SiliconLow dielectric Dit must survive FET process.
pacts on, off ,
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FET FETs
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FET Scaling Laws GL
Changes required to double device / circuit bandwidth.
laws in constant voltage limit:
g q
laws in constant-voltage limit: GW widthgateFET parameter change
gate length decrease 2:1current density (mA/m), gm (mS/m) increase 2:1channel 2DEG electron density increase 2:1electron mass in transport direction constantelectron mass in transport direction constantgate-channel capacitance density increase 2:1
dielectric equivalent thickness decrease 2:1channel thickness decrease 2 1channel thickness decrease 2:1channel density of states increase 2:1
source & drain contact resistivities decrease 4:1
Current densities should doubleCharge densities must double
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Semiconductor Capacitances Must Also Scale
)( VV motion)onalunidirecti(
oxc)( thgs VV )(
inversiondepth /Tc
2*2 2/
qEE wellf /)(
22 2/ gmqcdos
)2/()()(chargechannel 2* gmEEqVVcqn llfllfd )2/()()(charge channel gmEEqVVcqn wellfwellfdoss
scale. both alsomust states ofdensity & thicknessInversion
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Calculating Current: Ballistic LimittoappliedvoltagevoltageFermiChannel c
vv )3/4(velocityelectronmean
2/* through velocity Fermidetermines
toapplied voltagevoltageFermiChannel2ffff
dos
vmqVEv
c
fvv )3/4(velocity electronmean
thgsequivdos
cfdos VVcc
ccVVc
s :charge Channel
minima band of # theis where, )/*(2/* ,22 gmmgcgmqc oodosdos
dosequiv cc
2/3
2/3,
2/1
V 1)/*()/(1)/*(
mmA 84
thgs
ooxodos
o VVmmgcc
mmgJ
Do we get highest current with high or low mass ?
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2/1*2/3A VV
Drive Current Versus Mass, # Valleys, and EOT
2/3*
,
*
)/()/(1 where,
V 1mmA84
oequivodos
othgs
mmgccmmgK
VVKJ
0 35
0 25
0.3
0.35g=2g=1
InGaAs <--> InP Si
)/c/c(c 111
0.15
0.2
0.25
K
0.4 nm0.3 nm
/EOTε)/c/c(c oxequiv
2SiO
depth
11
0.05
0.1
0.15
EOT 1 0EOT i l d th f ti d th t
0.6 nm
0.4 nm
0
0.05
0.01 0.1 1m*/m
EOT=1.0 nmEOT includes the wavefunction depth term (mean wavefunction depth*
SiO2 /
semiconductor )
Standard InGaAs MOSFETs have superior Id to Si at large EOT.Standard InGaAs MOSFETs have inferior Id to Si at small EOT.
m /mo
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2/12/12/1 L
Transit Delay versus Effective Mass
,
0272
*1* whereVolt1cm/s 1052.2
oeq
odos
thgs
gch m
mgcc
mmK
VVL
K
1 5EOT=1.0 nm 0.6 nm
1.5
elay
K2
0.6 nm
1 nm0.4 nm
1
d tra
nsit
de 0.4 nm
)/c/c(c oxequiv1
depth11
0.5
norm
aliz
ed
EOT i l d f ti d th t
g=1, isotropic bands
g=2, isotropic bands
/EOTεoxequiv
2SiO
dept
00 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
m*/m
EOT includes wavefunction depth term (mean wavefunction depth*
SiO2 /
semiconductor )
m*/mo
Low m* gives lowest transit time, lowest Cgs at any EOT.
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III-V MOSFETs for VLSI: Why and Why Not.
Lower mass → Higher Carrier Velocity→ lower input capacitanceimproved gate delay in transistor-capacitance-limited gatesnot relevant in wiring-capacitance-limited gates (i.e. most of VLSI)
More importantly: potential for higher drive currentimproved gate delay in wiring-capacitance-limited gates (VLSI)
But this advantage is widely misunderstood in community
improved gate delay in wiring-capacitance-limited gates (VLSI)
But this advantage is widely misunderstood in communityInGaAs channels→ higher Id / Wg than Si only for thick dielectrics
....LOWER Id / Wg than Si for thin dielectricsbreak-even point is at ~0 5 nm EOTbreak-even point is at ~0.5 nm EOT
We will introduce (DRC2010) candidate III-V channel designsproviding higher Id / Wg than Si even for small EOT
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Contacts: Low Resistivity, High Current Density
sidewall
metal gategate dielectric
source contact drain contact
b t t
barrier
quantum well / channelN+ source N+ drain
10)/( current, drive onimpact 10% For
hDDSD VVRI
substrate
V3.0)(@mmA/5.1~/Target
1.0)/(
thDDgD
thDDSD
VVWI
VVRI
m 20)(@g
gs
thDDgD
WR
)(!20t tid10 2 )(!m2.0contact widenm 10 2 c
contacts refractorymmA/ 150contact indensity current 2
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F h 2 1 d ti i t l th
FET: Key Regions, Key Challenges
For each 2:1 reduction in gate length: gate dielectric:2:1 reduction in thicknesslimit: tunneling→high-Klimit: tunneling→high Klimit (high-K): defects
contacts:4:1 reduction in contact resistivity channel :
2:1 increase in electron density @ same voltage 2:1 shallower4:1 higher J
2:1 increase in electron density @ same voltage limit: # available electron states / area / energy"density of states bottleneck"; perceived to be fundamental
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Hi hl S l d FETHighly Scaled FETP FlProcess Flows
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Scalable nm III-V MOSFET: what is needed
True MOS device structures at 10 nm gate lengths10 nm gate length, < 10nm electrode spacings, < 10nm contact widths
True MOS device structures at ~10 nm gate lengths
< 3 nm channel, < 1 nm gate-channel separation, < w nm deep junctions, g p , p jFully self-aligned processes: N+ S/D, S/D contacts
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InGaAs MOSFET with N+ Source/Drain by MEE Regrowth1
HAADF-STEM1*
InGaAsregrowth
Interface
InGaAs
regrowth
2 nm
* TEM by J. Cagnon, Susanne Stemmer Group, UCSB
Self-aligned source/drain defined by MBE regrowth2
Self aligned in situ Mo contacts3Self-aligned in-situ Mo contacts3
Process flow & dimensions selected for 10-30 nm Lg design;1Singisetti, ISCS 20082Wistey, EMC 20083Baraskar, EMC 2009
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Regrown S/D process: key features
Self-aligned & low resistivitySelf aligned & low resistivity...source / drain N+ regions...source / drain metal contacts
Vertical S/D doping profile set by MBEno n+ junction extension below channelabrupt on few-nm scaleabrupt on few-nm scale
Gate-firstgate dielectric formed after MBE growth uncontaminated / undamaged surface
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Process flow* * Singisetti et al, 2008 ISCS, September, FrieburgSingisetti et al; Physica Status Solidi C, vol. 6, pp. 1394,2009
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Key challenge in S/D process: gate stack etch
R i t id d i i d t fRequirement: avoid damaging semiconductor surface:Approach: Gate stack with multiple selective etches*
SiO2
FIB Cross-section
Damage free channel
Cr
W
P l bl t 10 t l thProcess scalable to ~10 nm gate lengths* Singisetti et al; Physica Status Solidi C, vol. 6, pp. 1394,2009
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Challenge in S/D process: dielectric sidewallsidewall
2 1019
2.4 1019
2.8 1019
ratio
n (c
m-3
)
gate source
8 1018
1.2 1019
1.6 1019
10nm SiNctro
n co
ncen
tr
4 1018
0 10 20 30 40 50 60 70 80
20 nm SiN30 nm SiNel
ec
distance (nm) spillover
ns under sidewall:electrostatic spillover from source gateelectrostatic spillover from source, gate
Sidewall must be kept thin:avoid carrier depletion, p ,avoid source starvation
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MBE Regrowth→ Gap Near Gate→ Source Resistance
SEMMo+InGaAs
Ti/Au PadSiO2 cap
W / Cr / SiO2 gate
W/Cr gateg
SEM
gGap in regrowth
W / Cr / SiO2 gate
SEM
• Shadowing by gate: No regrowth next to gate
• Gap region is depleted of electronsHigh source resistance because of electron depletion in the gap
MBE growth by Dr. Mark Wistey, device fabrication and characterization by U. Singisetti
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Migration Enhanced Epitaxial (MEE) S/D Regrowth*
High T migration enhancedEpitaxial (MEE) regrowth*
No Gap
45o tilt SEM
gateNo Gap Top of SiO2 gate
Side of gate
regrowth interfaceNo Gap
High temperature migration enhanced epitaxial regrowthHigh temperature migration enhanced epitaxial regrowth
*Wistey, EMC 2008Wistey, ICMBE 2008
MBE growth by Dr. Mark Wistey, device fabrication and characterization by U. Singisetti
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Regrown S/D III-V MOSFET: Images
SiO2SiO2
WCr
InGaAsregrowth
SiNx
WCr
InGaAsregrowth
SiNx
W
Originalinterface
W
Originalinterface Ti/Au Pad
Mo+InGaAs
Ti/Au Pad
Mo+InGaAs
Cross-section after regrowth, Top view of completed devicebut before Mo deposition
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Source Resistance: electron depletion near gate
SiOSiOSiO2
InGaAsregrowth
SiNx
SiO2
InGaAsregrowth
SiNx
WCr
Originalinterface
g
WCr
Originalinterface
g
R1 interfaceinterfaceR1R2
• Electron depletion in regrowth shadow region (R1 )
• Electron depletion in the channel under SiNx sidewalls (R2 )
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Regrowth profile dependence on As flux*
SiO2
InGaAsInAlAs
Cr
InGaAs
InGaAsincreasing As flux
W
InGaAs
InGaAs
regrowth f uniform filling
multiple InGaAs regrowths with InAlAs marker layers
surface uniform filling
Uniform filling with lower As flux* Wistey et al, EMC 2009
Wistey et al NAMBE 2009
MBE growth by Dr. Mark Wistey, device fabrication and characterization by U. Singisetti
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InAs source/drain regrowth
InAsregrowth
Gateregrowth
side of gate
top of gate
M S/D t l ith Mo S/D metal with N+ InAs underneath
Improved InAs regrowth with low As flux for uniform filling1p g gInAs less susceptible to electron depletion: Fermi pinning above Ec
2
1 Wistey et al, EMC 2009 Wistey et al NAMBE 2009.
2Bhargava et al , APL 1997
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In-Situ Refractory Ohmics on MBE Regrown N-InGaAs
4
5
)
In-situ Mo on n-InAs In-situ Mo on n-InGaAs6
8
)
2
3
esis
tanc
e (
2
4
esis
tanc
e (
0
1
0 0.5 1 1.5 2 2.5 3 3.5
Re
ρc = 0.6 ± 0.4 Ω·µm2
n = 1×1020 cm-3
ρc = 1.0 ± 0.6 Ω·µm2
n = 5×1019 cm-3
0
2
0 0.5 1 1.5 2 2.5 3 3.5
Re
Gap Spacing (m) Gap Spacing (m)HAADF-STEM*
InGaAsth
Interface
InGaAs
regrowth
2 nm
InGaAs
TEM by Dr. J. Cagnon, Stemmer Group, UCSB
A. Baraskar
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Benefits of refractory contacts
100 nm InGaAs grown in MBE
15 nm Pd/Ti diffusion
30 nm Mo
After 250°C anneal, Pd/Ti/Pd/Au diffuses 15nm into semiconductordeposited Pd thickness 2 5nmdeposited Pd thickness: 2.5nm
Refractory Mo contacts do not diffuse measurablyRefractory Mo contacts do not diffuse measurablyRefractory, non-diffusive metal contacts for thin semiconductor layers
A.. Baraskar
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Resistivity of MEE Regrowth
15 m TLM width
(mV)
Volta
ge (m
V
~50 nm InAs regrowth has ~22 sheet resistivity50 nm InAs regrowth has 22 sheet resistivityContact resistivity is ~1.2 -m2.
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Self-Aligned Contacts: Height Selective Etching*
Mo PR
PR PR
InGaAs
Dummy gateNo regrowth
* Burek et al, J. Cryst. Growth 2009
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Fully Self-Aligned III-V MOSFET Process
0 5
0.6
0.7
0.8
mA/m
)
Lg = 200 nm W
g = 8 m
Vgs
: 0 to 4 V in 0.5 V steps
0.2
0.3
0.4
0.5
rain
cur
rent
, ID
(m
0
0.1
0 0.2 0.4 0.6 0.8 1
d
VDS
(V)
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Subthreshold characteristics
Lg=0.35 m
10-3
10-2
Lg=1.0 m
325 mV/decade10-5
10-4
290 mV/decadeI d(A)
Vds
=0.1V10-7
10-6
Vd
=0.1V
290 mV/decade
-1 0 1 2 3 4 5
ds
Vds
=1.0 V
10-9
10-8
-1 0 1 2 3 4 5
ds
Vds
=1.0V
1 0 1 2 3 4 5V
gs(V)
1 0 1 2 3 4 5V
gs(V)
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10-30 nm Process Development
SiO2 + SiNx Field: SiNx
Cr + SiNx
W + SiNx
Excellent structural yield in sub-100nm process flow
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27 nm Self-Aligned InGaAs MOSFETSelf-aligned N+ S/D regrowthg g
shallow , high doping , low sheet Self-aligned Mo in-situ S/D contacts:
lo refractor shallolow , refractory → shallow
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HAADF TEM
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HAADF TEM
STEM is chemical contrast imaging -> Is the regrowth sinking?
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C l iConclusion
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III-V MOS
With appropriate design III-V channels can provide > current than Si With appropriate design, III-V channels can provide > current than Si ...even for highly scaled devices
But present III-V device structures are also unsuitable for 10 nm MOSl i l t d iti d j tilarge access regions, low current densities, deep junctions
Raised S/D regrowth process is a path towards a nm VLSI III-V device
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(end)