a second-order multi-bit rd modulator with on-line
TRANSCRIPT
A second-order multi-bit RD modulator with on-line calibrationand digital correction of the digital-to-analog convertermismatches
Andrea Fornasari Æ Fausto Borghetti ÆPiero Malcovati Æ Franco Maloberti
Received: 11 May 2009 / Revised: 26 June 2009 / Accepted: 3 July 2009 / Published online: 15 July 2009
� Springer Science+Business Media, LLC 2009
Abstract This paper presents a novel technique for on-
line calibration and digital correction of the mismatches
among the elements of the digital-to-analog converter
(DAC) used in the feedback loop of multi-bit sigma–delta
(RD) modulators. The proposed method, with an extremely
limited amount of additional circuitry, allows the mis-
matches among the elements of the DAC to be accurately
measured and corrected in the digital domain, thus
improving the linearity performance of the modulator. A
switched capacitor (SC) 4-bit second-order RD modulator
has been implemented to validate the proposed solution.
The experimental results confirm that the proposed tech-
nique allows us to achieve an improvement in the spurious-
free dynamic range of the RD modulator as large as 26 dB.
Keywords Sigma–delta modulator � A/D converter �Digital-to-analog converter � On-line calibration
1 Introduction
Sigma–delta (RD) modulators can be realized using single-
bit or multi-bit digital-to-analog converters (DACs) in the
feedback loop. When a single-bit DAC is used, the RDmodulator is inherently linear and therefore the DAC ele-
ment matching is not important at all. The use of a multi-bit
DAC in the feedback loop allows the modulator resolution
to be increased without requiring a higher oversampling
ratio or modulator order. In this case, however, the linearity
of the whole RD modulator is limited by the linearity of
the DAC used. Therefore, for multi-bit RD modulators the
correction of the mismatches among the elements of the
DAC to achieve high linearity becomes one of the major
design issue.
Several techniques have been proposed in the literature
to tackle this problem [1]. The most straightforward solu-
tion is to improve the matching of the individual elements.
Methods of this type can generally be divided into two
different groups: one-time trims, which are part of the
manufacturing process, and repeated trims, which are
continuously carried out during the DAC operation. These
techniques are however typically expensive and difficult to
implement. The most widely used solution is the dynamic
element matching (DEM) technique [2–11]. With this
method the DAC elements used for each conversion are
selected randomly. The result is that the mismatches
among the DAC elements, instead of degrading the mod-
ulator linearity, lead to a wide-band noise. In some
implementations this mismatch noise is high-pass filtered,
thus diminishing the contribution that falls in the baseband
A. Fornasari � F. Maloberti
Department of Electronics, University of Pavia, Pavia, Italy
e-mail: [email protected]
F. Maloberti
e-mail: [email protected]
Present Address:A. Fornasari
National Semiconductor, Milano, Italy
F. Borghetti � P. Malcovati (&)
Department of Electrical Engineering, University of Pavia,
Pavia, Italy
e-mail: [email protected]
F. Borghetti
e-mail: [email protected]
Present Address:F. Borghetti
FBK-irst, Trento, Italy
123
Analog Integr Circ Sig Process (2010) 62:193–204
DOI 10.1007/s10470-009-9338-2
(noise-shaping DEM). Since the DEM techniques are not
actually correcting the DAC element mismatches, but rely
on the transformation of the mismatch effects into noise,
when under particular conditions this result is only partially
achieved, distortion tones appear, causing a degradation of
the spurious-free dynamic range (SFDR) as well as of the
signal-to-noise and distortion ratio (SNDR).
This paper describes a technique for actually measuring
on-line the mismatches among the DAC elements. The
obtained errors are stored in a memory and fully corrected
in the digital domain, thus obtaining the same effect of
repeated trimming methods (i.e. actual cancellation of the
mismatch errors). The experimental measurements on a
4-bit second-order RD modulator validate this method. The
proposed approach reduces the harmonic distortion caused
by the mismatch among the DAC elements by more than
26 dB. The area penalty for the implementation of this
method is very limited and comparable with the area
required for implementing a DEM technique for a 4-bit
DAC.
The paper is organized as follows. In Sect. 2 we describe
in general the proposed technique, which is then applied to
a second-order 4-bit RD modulator in Sect. 3. Section 4
reports the implementation details of the modulator and of
the most important building blocks. Finally, the experi-
mental results are described in Sect. 5.
2 Proposed technique
The on-line calibration of the unity elements of a DAC
requires the use of an extra element in the DAC and a
reference element. While the circuit operates regularly one
element of the DAC is selected and compared with the
reference element. At the end, another element is selected
and measured until all the elements are calibrated [12]. For
this approach to be effective, the measurement process
must not interfere with the normal operation of the RDmodulator. Since a RD modulator is based on oversam-
pling, there is a wide range of the spectrum between the
edge of the baseband and the Nyquist frequency which is of
no interest and could be exploited for measuring the mis-
match. However, this frequency range is affected by sig-
nificant quantization noise.
The basic idea behind the proposed technique is to
create a noise-free frequency region outside the band of
interest and use this part of the spectrum, through a suitable
modulation, for measuring the mismatch [13]. In the pro-
posed implementation we selected a region around half of
the sampling frequency (fS/2). This means that the noise
transfer function (NTF) of the RD modulator has to include
a notch at fS/2. An important point for the circuit realization
is the minimization of the hardware penalty. Typically, in
order to add a notch in the NTF an additional operational
amplifier is required in the modulator. In the proposed
implementation, we achieved this results for a second-order
RD modulator without using any additional active device,
thus making the hardware penalty negligible.
Figure 1 illustrates the proposed method used to mea-
sure the mismatch in a capacitor-based DAC. The capaci-
tive array consists of M ? 1 unity capacitors. While M
capacitors perform the normal digital-to-analog conver-
sion, one of them (Cj) is under calibration. The switched-
capacitor (SC) structure including Cj injects in the
feedback capacitor of the integrator a charge equal to
Cj � Vref every clock cycle, while the SC branch including
the reference element (Cref) injects a charge Cref � Vref. If
Cj = Cref, the injected charge represents a common mode
signal that does not affect the differential output of the
integrator. In fact, a suitable compensation network cancels
this common-mode term. On the other hand, a mismatch
between Cj and Cref determines a differential contribution.
A mixer, driven by a binary signal bsc, controls the injec-
tion of the mismatch signal. In this case, the mixer mod-
ulates the mismatch signal at fS/2. Since the region of the
spectrum around fS/2 is free from the quantization noise, it
is possible to extract the mismatch information from the
output bitstream, without affecting the input signal. This is
achieved by placing a second identical mixer in the digital
domain at the output of the RD modulator, thus down-
converting at DC the mismatch error.
The value of the error is then extracted with a simple
digital low-pass filter. The desired accuracy in the error
measurement can be achieved by reducing the bandwidth
of the filter used. In practical cases, a digital integrate-and-
dump circuit with a long integration period is sufficient.
The calibration operation, of course, has to be repeated (if
wished periodically in time) for all the DAC elements. The
information on the mismatch between each DAC element
and the reference element is stored in a look-up table. To
calibrate the RD modulator, canceling the effect of the
DAC element mismatch, the stored error values have to be
subtracted in the digital domain from the modulator output
bitstream. This could be performed directly at the output of
DACM Elements
in+
in-
bsc
Mod
ulat
or
1 1
2 2
1 1
2 2
Vref Vref
Cj Cref
Compensation
Fig. 1 Modified RD modulator for capacitor mismatch measurement
194 Analog Integr Circ Sig Process (2010) 62:193–204
123
the modulator before the decimation filter. However, in
order to achieve high resolution, the mismatch measure-
ment must be very accurate, thus strongly increasing the
word-length of the bitstream after the subtraction and
hence the complexity of the decimation filter itself. Instead,
it is more effective to filter the two signals (RD modulator
output bitstream and mismatch error) independently, and to
combine the results after decimation, as illustrated in
Fig. 2.
3 A/D converter implementation
The implementation of the proposed technique requires the
design of a RD modulator including a term (z ? 1) in the
numerator of the NTF, in order to introduce the additional
transmission zero at fS/2. Moreover, the noise shaping at
low frequency must remain unmodified. Finally, the signal
transfer function (STF) must be flat in the signal band. All,
the above features must be obtained without increasing the
number of operational amplifiers used. The following STF
and NTF fulfill the above mentioned constraints for a
second-order RD modulator:
STF zð Þ ¼ 3:5z� 1:5
z3 þ 0:4z2 þ 0:5zþ 0:1; ð1Þ
NTF zð Þ ¼ z� 1ð Þ2 zþ 1ð Þz3 þ 0:4z2 þ 0:5zþ 0:1
: ð2Þ
In addition to a notch at fS/2, these RD modulator transfer
functions show, at low frequency (z = 1), the same noise
shaping of a conventional second-order modulator:
NTFid zð Þ ¼ z� 1ð Þ2; ð3Þ
as illustrated in Fig. 3.
The RD modulator architecture that implements the
STF and the NTF given by (1) and (2) is shown in
Fig. 4. In this modulator the second integrator has been
replaced with a biquadratic cell, in order to realize the
additional zero in the NTF. Even if in literature [14, 15]
several ways to implement a biquadratic transfer function
using only one operational amplifier are available, we
chose to use an N-path filter, as shown in Fig. 5. This
circuit has to implement the transfer function in the
z-domain
H zð Þ ¼ 1:4z�1 � 0:6z�2
1� z�2; ð4Þ
which in the time domain corresponds to
1OutDecimator Filter
Decimator Filter
Tabl
eG
ener
ator
SquareWaveat fS/2
Selector
Reset Generator
Gain
1 – D T[k]
T
Look-Up Table
u
R
zz – 1
AcumulatorResettable
1/STF(–1)
1
In
Fig. 2 Principle scheme of the
proposed digital correction
circuit
10-4
10-3
10-2
10-1
-120
-100
-80
-60
-40
-20
0
20
40
Normalized Frequency
Mag
nit
ud
e [d
B]
NTF(z)NTFid (z)
Fig. 3 NTF of a traditional second-order modulator and of the
proposed one
Analog Integr Circ Sig Process (2010) 62:193–204 195
123
Vout nTð Þ ¼ Vout n� 2ð ÞT½ � þ 1:4Vin n� 1ð ÞT½ �� 0:6Vin n� 2ð ÞT½ �: ð5Þ
The implementation of (5) requires to delay by two
clock periods both the input and the output signals of the
circuit. This is achieved by realizing the feedback branch
as well as one of the input branches of the filter with two
capacitors, which are alternatively used every second clock
period. Thanks to the position of this block in the
modulator loop, any non-ideality associated with it
benefits of a first-order shaping provided by the transfer
function ETF from node U to the output, as shown in
Fig. 6, thus making the path-mismatch (i.e. the mismatch
between the two capacitors implementing each branch),
which is the most relevant drawback of this kind of filter
[15], negligible. For the same reason only the errors caused
by the first DAC (DAC1) are important: the errors
introduced by the second DAC (DAC2), in fact, become
irrelevant, because of the first-order shaping provided by
ETF. Therefore, we chose to use the proposed calibration
method only for DAC1.
During the calibration phase the data converter output is
indeed
Out ¼ In � STF zð Þ þ EDAC1 � STF zð Þ þ EDAC2 � ETF zð Þþ NQ � NTF zð Þ þMis� � STF zð Þ; ð6Þ
where EDAC1 and EDAC2 are the errors introduced by DAC1
and DAC2, respectively, NQ is the quantization noise and
Mis* is the DAC mismatch modulated by bsc produced by
(-1)N mismatchEDAC1 E
DAC2
NQ
1.4z-0.6
z -12z-1
2.5
DAC2
DAC1
ADC1In
1Out
U
Fig. 4 RD modulator
architecture implementing the
desired transfer functions
ph1A CfA
ph1BCfB
_
+
ph2
S<15:0>ph2
ph1C1
ph2A
S1An<15:0>ph2A
ph1AC2A
ph2B
ph2B
ph1BC2B
+
_
ph1A CfA
ph1B CfB
ph2
ph2
ph1C1
ph2A
ph2A
ph1AC2A
ph2B
ph2B
ph1BC2B
ph1
ph2
ph1A
ph1B
ph2A
ph2B
Cf1
_
ph2*
ph2
ph1CS<15:0>
+
In+
+VREF
-VREF
P<
15:0>
G<
15:0>
N<
15:0>
ph2*
ph2
ph1In-
P<
15:0>
G<
15:0>
Cf1
+ _
AGND
AGND
AGND
AGND
AGND
AGND
S1Bn<15:0>
S1B<15:0>
S1A<15:0>
Sn<15:0>
Vtap<15:0>
Vtap<15:0>
Vtap<15:0>
Vtap<15:0>
Vtap<15:0>
Vtap<15:0>
ph1 ph2 ph1 ph2
P<16:0>
N<16:0>
G<15:0>
S<15:0>
S1Bn<15:0>
S1An<15:0>
Sn<15:0>
S1B<15:0>
S1A<15:0>
Bit<3:0>
CS<15:0>
AGNDph2
Cr
N<
16>
P<
16>
+V
ref
–Vref
AGND
ph2Cr
N<
16>
P<
16>
+V
ref
–Vref * bootstrap switch
N<
15:0>
B<14:0>
Bn<14:0>
Fig. 5 Schematic of the proposed RD modulator
196 Analog Integr Circ Sig Process (2010) 62:193–204
123
the calibration network. Since the input signal is band-
limited, the output spectrum contains two components: one
due to In � STF(1) ? EDAC1 � STF(1) in the baseband and
one caused by Mis* � STF(-1) at high frequency, as shown
in Fig. 7. As already discussed, the mismatch can be
extracted multiplying the output bitstream by ±1 (Fig. 2).
We achieve mismatch correction in the digital domain
by subtracting from the output the estimated mismatch
hEDAC1i divided by STF(-1). Assuming that the estimation
differs from the real error by QhEDAC1i we have
In � STF zð Þ þ EDAC1 � STF zð Þ � hEDAC1i � STF zð Þ¼ In � STF zð Þ þ QhEDAC1i � STF zð Þ: ð7Þ
Therefore, if we want to make the residual error smaller
than the quantization contribution it is necessary to use a
very accurate estimation of EDAC1. The word-length in the
look-up table used for error correction (Fig. 2) depends on
the expected mismatch between elements. In order to
optimize the look-up table dimension it is useful to have,
for the technology used, an estimation of the expected
accuracy. Considering that the presented implementation
uses 4-bit DACs and assuming a mismatch of 0.2%, only 4
bits words are required for achieving an accuracy of 14
bits, as shown in Fig. 8. Therefore, the size of the used
memory is pretty small. The expected matching also
determines the integration time of the digital integrator
with reset used for low-pass filtering the mismatch error.
Simulation results show that using 217 clock periods is
more than adequate for the implemented system.
Therefore, we complete an entire calibration cycle within
221 clock periods.
4 A/D converter building blocks
Extensive behavioral simulations of the proposed RDmodulator, carried out with MATLAB/Simulink using a
specifically developed toolbox which models also the non-
idealities of basic the building blocks [16, 17], allowed us
to determine the specifications of the components of the
circuit shown in Fig. 5. The obtained parameter values are
summarized in Table 1. The most important building
blocks, namely operational amplifier, comparator, boot-
strapped sampling switch and reference voltage buffer are
described in detail in the following paragraphs.
4.1 Operational amplifier
The operational amplifier topology used in the proposed
RD modulator is derived from the circuit presented in [18,
19]. The schematic of the amplifier is shown in Fig. 9.
Assuming unity gain for all the current mirrors and mat-
ched transistors M1, M2, as well as M3, M4, M5, M6, the
internal poles of this operational amplifier (at nodes A and
B), considering R = 0 are approximately given by [20]
fPA;B ¼gm3;4
2pCA;B; ð8Þ
where gm3,4 denotes the small signal transconductance gain
of M3,4 and CA,B is the parasitic capacitance associated to
nodes A and B. The main contribution to this capacitance is
given by the gate-source parasitic capacitance of M3,4 and
M5,6, as well as the drain-bulk parasitic capacitance of M1
and M2: CA,B = Cgs3,4 ? Cgs5,6 ? Cdb1,2 and can be
substantial, thus limiting the maximum bandwidth of this
amplifier.
Considering R = 0, for a common mode input signal
(i.e. an input signal without differential components) the
current IR flowing in resistors R is zero because the drain
current of transistors M1 and M2 is the same and nodes A
and B are at the same voltage. For common-mode signals
these transistors perform as a low impedance load (diode
connection) with value 1/gm3,4. In the presence of a dif-
ferential signal, the signal component (IR) of Id1,2 flows
through resistors R (Id1 = Ibias/2 ? IR, Id2 = Ibias/2 - IR,
10-3
10 -2
10 -1
-70
-60
-50
-40
-30
-20
-10
0
10
20
Normalized frequency (1S
)
Mag
nit
ud
e [d
B]
f
Fig. 6 ETF of the proposed modulator
0.38 0.4 0.42 0.44 0.46 0.48 0.5-160
-140
-120
-100
-80
-60
-40
-20
0
Normalized Frequency
Mag
nitu
de [d
B]
Fig. 7 Calibration tone located at half of the sampling frequency
Analog Integr Circ Sig Process (2010) 62:193–204 197
123
-160
-140
-120
-100
-80
-60
-40
-20
0
Normalized frequency (1Nyquist
)
Mag
nit
ud
e [d
B]
f
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-160
-140
-120
-100
-80
-60
-40
-20
0
Normalized frequency (1Nyquist
)
Mag
nit
ud
e [d
B]
f
sdrow tib-1 noitcerroc oN (a) (b)
-160
-140
-120
-100
-80
-60
-40
-20
0
Normalized frequency (1Nyquist
)
Mag
nit
ud
e [d
B]
f
-160
-140
-120
-100
-80
-60
-40
-20
0
Normalized frequency (1Nyquist
)
Mag
nit
ud
e [d
B]
f
sdrow tib-3 (d)(c)
(e) (f)
sdrow tib-2
-160
-140
-120
-100
-80
-60
-40
-20
0
Normalized frequency (1Nyquist
)
Mag
nit
ud
e [d
B]
f
-160
-140
-120
-100
-80
-60
-40
-20
0
Normalized frequency (1Nyquist
)
Mag
nit
ud
e [d
B]
f
sdrow detimilnU sdrow tib 5
Fig. 8 Effect of the correction technique as a function of the look-up table word-length
198 Analog Integr Circ Sig Process (2010) 62:193–204
123
IR = gm1,2vin) while the drain currents in M3 and M4
remain unchanged. In fact, the gates of M3 and M4 are
shorted (node C). The current IR generates differential
complementary voltage changes at nodes A and B. Given
that the common gate of M3,4 has a constant voltage (vir-
tual ground for signal), the differential signal impedance at
nodes A and B is given by
RA;B ¼ Rk 1=gm3;4
� �; ð9Þ
and the open loop gain of the operational amplifier is
A ¼ gm1;2RA;Bgm5;6Rout; ð10Þ
Rout being the output impedance. The pole due to nodes A
and B becomes
fPA;B ¼1
2pC0A;BRA;B; ð11Þ
where
C0A;B � CA;B=2 ¼ Cgs5;6 þ Cdb1;2: ð12Þ
In fact, being node C a virtual ground, the parasitic
capacitance at node A and B does not include the gate-
source capacitance of transistors M3 and M4, thus
improving the frequency performance of the amplifier.
Resistors R are realized with high-resistivity polysilicon
(1 kX/h). The performance of the operational amplifier are
not much sensitive to the value of R, as long as R �1/gm3,4, thus allowing process spread as large as ±25%
to be tolerated.
4.2 Comparator
Fifteen fully-differential comparators are needed to per-
form the internal A/D conversion (four bits). In the pro-
posed RD modulator they are realized by employing a
charge summation circuit. The comparator consists of a
latch stage preceded by coupling capacitors that perform
the difference between the input signal and the different
reference voltages. The adopted capacitive differential pair
comparator topology, derived from the circuit used in
[21, 22], is shown in Fig. 10.
The comparator core consists of a single, switched dif-
ferential amplifier with a CMOS latch load and requires a
two-phase clock. During the phase latch, one coupling
capacitor pair is pre-charged to Vin = Vin? - Vin
- and the
other pair to Vref = Vref? -Vref
- . The comparator core is
inactive and the switch transistors M6 and M9 are resetting
the complementary outputs to Vdd, thus forcing M4 and M5
to conduct and also forcing the drains of the input pair to
Vdd, while the dynamic tail current source M3 is switched
off. When the signal latch is released, the differential pair
amplifier becomes active, the outputs are disconnected
from the supply voltage, and the bottom plates of the
capacitors are grounded, allowing the charges stored in the
input (Cin) and reference capacitors (Cref) to be transferred
between their top plates. The differential pair amplifies the
voltage difference and the latch regenerates accordingly.
According to the preservation of the charge, the output of
the comparator changes state when
Vþin � V�in ¼Cref
CinVþref � V�ref
� �: ð13Þ
This equation implies that the threshold voltage of the
comparator can be adjusted linearly with the capacitance
Table 1 Specifications of the building blocks of the proposed RDmodulator
Parameter Value
Operational amplifier open-loop gain 76 dB
Operational amplifier closed-loop bandwidth 280 MHz
Operational amplifier phase margin 60�Total input capacitances CsCr 2.5 pF
Capacitance Cf1 1 pF
Capacitance C1 700 fF
Capacitances C2A and C2B 300 fF
Capacitances CfA and CfB 500 fF
R
Fig. 9 Schematic of the operational amplifier used
Vin-
Vref+ Vref
-
M1 M2
M5M4
M7 M8
M3
+Vout
-Vout
M6 M9
+Vin
latch
Cref
Cin
latchlatchlatch
Cin
Cref
Vdd
latchlatch
latch
latch
latch
latchlatch
latch
latch
Fig. 10 Schematic of the comparator used
Analog Integr Circ Sig Process (2010) 62:193–204 199
123
ratio. Anyway, in the proposed RD modulator, we preferred
to keep this ratio constant (equal to one) and set thresholds
using several reference voltages. The comparator offset,
originated by the mismatch between the differential pair
transistors (threshold voltage, load resistance and dimen-
sions) and by the mismatch between the capacitors Cin and
Cref, is not a relevant issue due to the beneficial effect of
noise shaping (the errors introduced by the comparators are
filtered by NTF).
4.3 Bootstrapped sampling switch
In high-speed low-voltage designs, the MOS transistor on-
resistance is a significant limitation on the tracking speed
and the settling time. Moreover, the on-resistance has a
nonlinear voltage dependence, which produces distortion
when tracking continuous time signals [23]. To reduce the
on-resistance, a voltage higher than the power supply can
be used to control the switches. In a typical realization, the
switch transistor gate is locally boosted with a charge pump
circuit. It is also possible to use a switch gate voltage which
tracks the switch input voltage with some offset (typically
Vdd). This gives two advantages. First, the circuit long-term
reliability is improved since the gate-drain voltage of the
switch transistor never exceeds Vdd. Second, the on-resis-
tance becomes almost constant, which significantly reduces
the distortion. The employed switch circuit [24, 25] is
shown in Fig. 11. Since the circuit is quite complex, it has
been used only where really needed (i.e. at the RD mod-
ulator input).
4.4 Reference voltage buffer
In a RD modulator, reference voltages are required for the
internal DACs and for the A/D conversion performed
by the internal flash ADC. Inaccuracy in the voltage ref-
erence used for the ADC (Vcm, ±Vref,0,…,±Vref,6) adds to
the offset voltage of the comparators, deteriorating its
performance. In RD modulators, the comparator accuracy
requirement is relaxed by noise shaping (NTF). By con-
trast, the reference voltages of the DAC on the first inte-
grator (±Vref) have high accuracy specifications. They
must charge a variable capacitance formed by the unit
elements of the internal DAC and settle within the accuracy
of the whole RD modulator during half of a clock cycle (the
errors experiment the same transfer function of the signal
STF). Especially in high-speed converters, this implies
inevitably buffering of the references with large bandwidth,
in order to achieve the accuracy and settling time specifi-
cations. In the proposed RD modulator, the feedback on the
second stage is realized in the voltage domain using 16
voltage levels ±Vtap,0,…,±Vtap,7. This choice was made to
reduce the pseudo N-path filter capacitor size. In fact, even
using the minimum capacitor size permitted by the tech-
nology, this would have determined a total capacitor size
far larger than that we used (total capacitance would be
determined by sixteen times the minimum capacitor size
allowed by technology). Note that accuracy constraints on
this feedback path (and then on voltage references) are
relaxed by the ETF (first-order shaping).
A resistor string, dimensioned to provide proper tap
voltages, is a straightforward solution for a voltage refer-
ence. In the proposed circuit, the potential of both edges of
the resistor string are produced off-chip to keep the tap
voltages constant, independently of any variation of the
power supply voltage. To minimize power dissipation, the
total resistance of the string should be maximized, which is
limited by the settling requirement of the reference volt-
ages; the R C time constant of each capacitively loaded
node of the string must be well below the settling time. The
schematic of the used reference voltage buffer is shown in
Fig. 12. We chose this solution since the most accurate
references voltages produced are ±Vref which are used in
the DAC of the first stage, while Vcm, ±Vref,0,…,±Vref,6
and ±Vtap,0,…,±Vtap,7, which are used in the DAC of the
second stage and in the ADC, respectively, are less accu-
rate. Capacitors Cc are required to compensate the buffer,
ensuring stability under any operating conditions, while
capacitors Cf are used for decoupling.
5 Experimental results
The proposed RD modulator has been implemented in a
0.35lm CMOS technology. A microphotograph of the
6 mm2 chip, including the analog RD modulator and a
digital block implementing the calibration algorithm, is
shown in Fig. 13. The core area of the RD modulator is
1.9 mm2 (1.4 mm2 for the analog section and 0.5 mm2 for
the digital section). Figure 14 shows the superimposition of
the results of ten different complete cycles of calibration
M9
M8
M7M6
M5
M4
M3
M2 M1
C1
Vdd
ph2
ph1
Vss
Vout
ph1
VinVss
Fig. 11 Schematic of the bootstrapped sampling switch used
200 Analog Integr Circ Sig Process (2010) 62:193–204
123
performed on the same chip. Each calibration cycle con-
sists of sixteen steps, in each of them a capacitor is cali-
brated (compared with the reference capacitor) and the
other fifteen perform the digital-to-analog conversion.
Once the calibration phase is terminated (after 217 clock
periods in the example of Fig. 14) another capacitor is
placed in the calibration section. The measured mismatch
is greater than supposed, but the proposed technique is able
to correct these errors.
For dynamic measurements of the proposed RD modu-
lator we used a universal source for generating the
differential input voltage and a logic analyzer to acquire
the output bits. The power spectral density of the modu-
lator output before and after calibration is shown in
Fig. 15. An improvement of more than 30 dB on the third
harmonic has been obtained, leading to a spurious-free
dynamic range (SFDR) improvement as large as 26 dB.
After calibration, the dominant spur becomes the second
harmonic. The proposed technique has no effect on the
even harmonics because they are not introduced by the
DAC (completely fully differential) but by the signal
source. The additional hardware in the analog section
_
+
R
Vdd
_
+
Vdd
Vbiasn
Vbiasp
AGND
Vrefp
Vrefn
+Vref
Cc
Cc
Cf
Cf+Vtap,7
-Vtap,7
-Vref
R
R
R
R
R
R
R
R
R
R
Vcm
+Vtap,0
+Vref,0
-Vref,0
-Vtap,0
-Vtap,1
+Vref,6
-Vref,6
Fig. 12 Schematic of the
reference voltage buffer used
Analog Integr Circ Sig Process (2010) 62:193–204 201
123
required for implementing the proposed technique is
extremely limited: only two extra capacitors and a few
switches are needed. Moreover, the power consumption of
the RD modulator is not affected by the proposed calibra-
tion technique. The most important features of the pro-
posed modulator are summarized in Table 2.
6 Conclusions
A method for on-line calibrating the DAC used in multi-bit
RD modulators has been proposed. The method exploits an
additional transmission zero, located at fS/2, in the modu-
lator noise transfer function. This creates a ‘‘clean’’ area in
the output spectrum where it is possible to allocate a tone
whose amplitude is proportional to the DAC element
mismatch. A simple digital processing allows us to mea-
sure the mismatches and to store them in a digital memory.
Measurements on a second-order 4-bit RD modulator val-
idate the proposed technique, which allows an SFDR
improvement of more than 26 dB to be achieved.
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Table 2 Performance of the RD modulator (input signal at 1 kHz)
Parameter Value
Area (including pads) 6 mm2
Sampling frequency 2.3 MHz
Signal bandwidth 18 kHz
SNDR at 1 kHz before calibration 58.8 dB
SNDR at 1 kHz after calibration 66.1 dB
SFDR at 1 kHz before calibration 61 dB
SFDR at 1 kHz after calibration 87 dB
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Andrea Fornasari was born in
Piacenza, Italy in 1976. He
received the Laurea and Ph.D.
degrees from the University of
Pavia, Pavia, Italy in 2000 and
2004, respectively. In this per-
iod, his main field of interest
was the design of analog–digital
converters (ADCs) and the
study of digital calibration of
circuital non idealities, receiv-
ing a patent in this area. In
2004, he joined Austriamicro-
systems, Pavia, Italy, while in
2006 he moved to National Semiconductor, Milano, Italy, where he is
involved in the design of analog and mixed-signal circuits.
Fausto Borghetti was born in
Verona, Italy, in 1974. He
received the Laurea and Ph.D.
degrees in Electronics and Com-
puter Science from the University
of Pavia, Pavia, Italy, in 2000 and
2005, respectively. In 2005, he
joined the Integrated Optical
Sensor Group, Fondazione Bruno
Kessler, Istituto Ricerca Scien-
tifica e Tecnologica (FBK-irst),
Povo, Italy. His research interests
are in high-performance analog–
digital converters, DC/DC con-
verters and CMOS image sensors.
Piero Malcovati was born in
Milano, Italy, in 1968. He
received the Laurea degree
(summa cum laude) in Elec-
tronic Engineering from the
University of Pavia, Italy, in
1991. He received the Ph.D.
degree in Electrical Engineering
from the Physical Electronics
Laboratory (PEL) at the Federal
Institute of Technology in Zur-
ich (ETH Zurich), Switzerland,
in 1996. From 1996 to 2001, he
was an Assistant Professor in the Department of Electrical Engi-
neering, University of Pavia. Since 2002, he has been an Associate
Professor of electrical measurements in the same institution. His
research activities are focused on microsensor interface circuits and
high-performance data converters. He has authored or co-authored
more than 40 papers in international journals, more than 150 pre-
sentations at international conferences (with published proceedings),
and seven book chapters, and holds five industrial patents. Dr. Mal-
covati was a co-recipient of the ESSCIRC 2007 Best Paper Award.
He was a guest editor for the Journal of Analog Integrated Circuits
and Signal Processing for the special issue on IEEE ICECS 1999. He
served as Special Session Chairman for the IEEE ICECS 2001
Conference, as Secretary of the Technical Program Committee for the
Analog Integr Circ Sig Process (2010) 62:193–204 203
123
ESSCIRC 2002 Conference, and as Technical Program Chairman of
the IEEE PRIME 2006 Conference. He was and still is a member of
the Scientific Committees for several international conferences,
including ESSCIRC, DATE, and PRIME. He is regional editor for
Europe of the Journal of Circuits, Systems, and Computers, as well as
an Associate Editor for the IEEE Transactions on Circuits and
Systems II.
Franco Maloberti received the
Laurea degree in Physics
(summa cum laude) from the
University of Parma, Parma,
Italy, in 1968, and the Doctorate
Honoris Causa in electronics
from the lnstituto Nacional de
Astrofisica, Optica y Electronica
(lnaoe), Puebla, Mexico, in
1996. He was a Visiting Pro-
fessor at the Swiss Federal
Institute of Technology (ETH-
PEL), Zurich, Switzerland, and
at the EPFL, Lausanne, Swit-
zerland. He was the TI/J. Kilby
Chair Professor at the A&M University in Texas, and the Distin-
guished Microelectronic Chair Professor at the University of Texas at
Dallas. Presently, he is Professor of microelectronics and Head of the
Micro Integrated Systems Group, University of Pavia, Italy. His
professional expertise is in the design, analysis, and characterization
of integrated circuits and analog–digital applications, mainly in the
areas of switched-capacitor circuits, data converters, interfaces for
telecommunication and sensor systems, and CAD for analog and
mixed AID design. He has written more than 370 published papers in
journals or conference proceedings and four books, and holds 27
patents. In 1992, Dr. Maloberti was the recipient of the XII Pedriali
Prize for his technical and scientific contributions to national indus-
trial production. He was corecipient of the 1996 Institute of Electrical
Engineers Fleming Premium, the Best Paper Award in ESSCIRC
2007, and the Best Paper Award in IEEJ Analog Workshop 2007. He
was the President of the IEEE Sensor Council from 2002 to 2003,
Vice-President, Region 8, of the IEEE CAS Society from 1995 to
1997, and an Associate Editor of IEEE TRANSACTIONS ON CIR-
CUITS AND SYSTEMS II. Presently, he is serving as VPPublica-
tions of the IEEE CAS Society. He received the 1999 IEEE CAS
Society Meritorious Service Award, the 2000 CAS Society Golden
Jubilee Medal, and the 2000 IEEE Millennium Medal.
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