a robust prml read channel with digital timing recovery...

A Robust PRML Read Channel with Digital Timing

Recovery for Multi-Format Optical Disc

Gunjae Koo

SoC Core Technology Group

LG Electronics Institute of Technology

LG Electronics Read Channel 2

Introduction

1. Channel characteristics of optical disc

2. Digital timing recovery

3. PRML- Adaptive equalizer- Viterbi decoder with adaptive PR-level

4. Simulation results

5. Conclusion


Optical Disc Characteristics

❖ Disc Characteristics

» Increase the data density

» Narrower track pitch

DVD BD

Wavelength of laser diode 630 nm 405 nm

Channel bit length 133.3 nm 74.5 nm

Channel bit frequency (x1) 26.15625 MHz 66 MHz

Maximum signal frequency (x1) 26 / 6 = 4.4 MHz (3T) 66 / 4 = 16.5 MHz (2T)

Optical cut-off frequency (x1) 6.44 MHz 20.64 MHz

Signal asymmetry -0.05 ~ 0.15 -0.10 ~ 0.15

Modulation (Run-length limit) EFM+, RLL(2,10) 17PP, RLL(1,7)

Ideal maximum defect length About 6 mm About 9 mm


Optical Disc Characteristics

❖ Channel modeling

<Frequency response>

<FIR-form modeling>

NAFffffH cut

2,1)(cos

2)( 21


Overall Architecture

❖ Read channel for optical disc

» Digital timing recovery + PRML

» Use static 115MHz system clock – all digital processing

» 2x parallel processing for supporting high speed

PD /Loop filter

Pick-upunit

Analogfilters & EQs

ADCDn/up sample

& filter

Envelopedetector

Asymmetrycompensator

PD /Loop filter

RLL-basebit correction

NCO

Coefficientupdate

Viterbidecoder

+

+

Optical disc

RF signal

Digital front-end(Read channel)

Static sampling(115MHz)

Digital timing recovery

Interpolator

PRML

Interpolator

FD

Limit EQLimit EQ

AdaptiveEQ

AdaptiveEQ

2x parallel processing


Digital Timing Recovery

❖ NCO (Numerically controlled oscillator)

» Accumulates feed-backed timing error & control the timing matched position

❖ Interpolator

» Calculates timing matched data with interpolation scheme using 4-sampling data

• Y[0] = μ[0]2 x 0.5 x (X[3] - X[2] - X[1] + X[0]) + μ[0] x 0.5 x (-X[3] + 3X[2] - X[1] - X[0]) + X[1]

• Y[1] = μ[1]2 x 0.5 x (X[4] - X[3] - X[2] + X[1]) + μ[1] x 0.5 x (-X[4] + 3X[3] - X[2] - X[1]) + X[2]

• μ[0] = Udto[0] / Idto[0], μ[1] = Udto[1] / Idto[1]

• At overflow point, Udto[0] = Udti[1] + Idto[0] – Mdto, Idto = output of loop filter

X[0]

Idto[1]

X[3]

X[2]X[1]

x(t)

x(t-T)

x(t-2T)

Udto[2]

Udto[1]

Mdto

=NCO bit^2

Y[1]◎

●●

●

●

●

X[4]

x(t-4T)

Udto[0]

Idto[0]

◎

Y[0]Overflowed position



❖ Frequency detector

» Reduce the locking time of the timing recovery

» Detect the sync duration and adjust the accumulation value of NCO

❖ Timing error generation

» Limit EQ output between zero crossing points

» RLL-based corrected bit is used to determine zero crossing

❖ Loop filter

» 1st IIR filter structure

» Process maximum 2 timing error in one cycle

+ Idto[1]

G1

G2

+ Idto[0]

G1

G2

+

G3

G3

Z-1

+

Timing error[0]

Timing error[1]

o

o

+

+

+

Zero crossing(bit corrected)

Timing error

baseline

+o

: Limit EQ output

: The middle value of limit EQ outputs

<Timing Error> <Loop filter>



❖ RLL-based bit correction

» Many bit errors of high frequency signals by ISI

» Correct the miss-detected bits violating the minimum run-length

» Corrected bit is used for generated reference level of adaptive-EQ

(b)(a)

+o

: Limit EQ output

: The middle value of limit EQ outputs

o

+

baseline

+

+

o1→0 1→0

Bit detection: …, 1, 1, …

Corrected: …, 0, 0, …

baseline

1→0

++

+

+

o

o

o1

compare ABS value

0

Bit detection: …, 1, 0, 1, …

Corrected: …, 0, 0, 1 …

<RLL-based bit correction>


Adaptive Equalizer

❖ Adaptive equalizer

» Generates defined partial response (PR) signal

» LMS algorithm applying power-of-2 method

» RLL-based corrected bit data are used for generating reference level

Limit EQ

RLL-based

Bit correction

Z-1

Z-1

Delay

Control

Z-1

a b b a

a b b a

+

+

--

Reference[0]

Reference[1]

+

ADEQ out[0]

ADEQ out[1]

Power-of-2

generation

Coefficients

update

FIR filter

(5-tap, 2x parallel)

Error[0] Error[1]

Bit[0]

Bit[1]

0 a

0 a

<Structure of adaptive equalizer>


Viterbi Decoder

❖ Viterbi decoder with adaptive PR-level adjusting

» Process two bits in one flag cycle – modified transition diagram

» Adjust the PR-level adaptively for compensating signal asymmetry

000

001

011

100

110

111

000

001

011

100

110

111

000

001

011

100

110

111

000

001

011

100

110

111

000

001

011

100

110

111

1

0

‘0’ transition

‘1’ transition

BMU PMU ACSU SMU

PR-level update

ADEQ out[1]

ADEQ out[0]

Bit[1]

Bit[0]

<Transition diagram>

<Structure of Viterbi decoder>


Simulation Results

❖ Simulation for Gaussian noise (2x BD)

SNR vs BER

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

16 16.5 17 17.5 18 18.5 19 19.5

SNR

BE

R

Raw bit

RLL-based correction

PRML (PR121)

Adaptive PRML (PR121)


Simulation Results

❖ Simulation for asymmetry defect*

Assymetry vs SNR

1.00E-06

1.00E-05

1.00E-04

1.00E-03

0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18

Assymetry

BE

R

PRML (PR121)

Adaptive PRML (PR121)

* Asymmetry model is from “Modeling and Compensation of Asymmetry in Optical Recording” by H. Pozidis


Conclusion

Supporting media & speedBD (~3x), DVD (~8x) & CD

(~ 210 Mbit/s)

ADC bit resolution 8-bit (ENOB > 7)

Operating clock 115 MHz

Process technology 0.18-um TSMC digital library

Area (except ADC) 70k gates (about 0.70mm2)

❖ Summary

a robust prml read channel with digital timing recovery...

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