a reconfigurable design-for-debug infrastructure for socs
DESCRIPTION
A Reconfigurable Design-for-Debug Infrastructure for SoCs. Peter Levin Gerard Memmi Dave Miller. Miron Abramovici Paul Bradley Kumar Dwarakanath. Silicon Debug: Growing Barrier to Market Entry. Debug & Qualification. 1 st Si. Netlist. Spec. RTL. 180nm $4.2M ~12 mo. ~ 17% of TTM. - PowerPoint PPT PresentationTRANSCRIPT
A Reconfigurable Design-for-Debug Infrastructure for SoCs
A Reconfigurable Design-for-Debug Infrastructure for SoCs
Miron Abramovici
Paul Bradley
Kumar Dwarakanath
Peter Levin
Gerard Memmi
Dave Miller
Silicon Debug: Growing Barrier to Market EntrySilicon Debug: Growing Barrier to Market Entry
Spec RTL Netlist 1st Si Debug & Qualification180nm
$4.2M~12 mo
130nm$10.8M~15 mo
Source: Collett ASIC/IC Verification Study 2004 (180nm / 130nm)
> 28% of TTM !
Traditional Debug Strategies Failing
90nm$25.8M~18 mo
> 35% of TTM ?
~ 17% of TTM
Post-Silicon Debug Problem StatementPost-Silicon Debug Problem Statement
1st Silicon often doesn’t work More than 50% of new chips have functional issues After substantial and expensive pre-silicon verification
Post-silicon debug is expensive Average debug and validation period (at 90nm): 6 months Economic impact of delayed ramp to production: $ tens
of millions
Post-silicon debug is challenging Very limited observability of chip-internal signals On-chip clock frequency often too high for external
access
In-System At-Speed Silicon DebugIn-System At-Speed Silicon Debug
Required to validate silicon
Exercises functionality and timing not verified pre-silicon
More constrained than tester-based debug
Expected values not known
The problem may be caused by a defect
Problem difficult to reproduce on tester
State-of-the-art Ad-hoc debug structures Time-consuming manual effort Few commercially available tools
Application program
SoC Under Debug
A New ApproachA New Approach
Distributed reconfigurable infrastructure fabric User-guided insertion compatible with existing design
flows Soft IP inserted at RTL Configured post-silicon for maximum debug flexibility
Effective debug and verification platform Signal capture and analysis Assertion-based debug Stimulate and capture What-if analysis Event- and transaction-driven debug support
Design Flow IntegrationDesign Flow Integration
Accelerated Debug & Validation
Prototype SiliconCustomer
Design
InsertInstrumentation
DebugEnvironment
SynthesisPhysical Design
Debug StructuresDebug Structures
Configured dynamically (when needed): triggers to start/stop recording of signals assertion checkers event detectors event counters pattern generators value injectors … …
Configuration and instrument control via JTAG TAP
Instrumented Chip ExampleInstrumented Chip Example
Signal Probe Network(transport/selection)
DEbug MONitor(analysis)
Tracer(capture)
Wrapper(analysis & control)
CapStim(capture/stimulate)
JTAG
Primary CONtroller(instrumentation access & control)
Tapping / Wrapping of SignalsTapping / Wrapping of Signals
BEFORENet_a
TAP
Net_aAFTER
MUX
Net_a <X>_Net_aMUX
WRAP
WrapElement
Delay: none Load: 1 Gate TAP: þ WRAP: ¨ OBS: þ SCTL: ¨ ASCTL: ¨ MOD: ¨
Delay: 1 MUX Load: 1 Gate TAP: þ WRAP: þ OBS: þ SCTL: þ ASCTL: þ MOD: þ
Supported Debug ParadigmsSupported Debug Paradigms
Signal capture and logic analysis
Assertion-based debug
Stimulate and capture (in-situ, at-speed IP verification)
Event- and transaction-driven debug
Scan-based debug
What-if analysis Fault/error injection Soft fixes or ECOs
May be intermixed
Signal Probe Network (SPN)Signal Probe Network (SPN)
Daisy chainfor ease-of
routing
Pipeline registerfor enhanced
speed
FIFOfor clock domain
crossing
Alignerfor data path
balancing
Logic Analysis and Signal CaptureLogic Analysis and Signal Capture
DEMON block implements triggers
Signals captured by Tracer
Software reads trace buffer and prepares VCD or FSDB files
MonitorsMonitors
Reconfigurable Monitor more flexible Programmable Trigger Engine
less area
higher speed
CAPSTIM InstrumentCAPSTIM Instrument
Used for in-situ IP verification
Assertion-Based Silicon DebugAssertion-Based Silicon Debug
Assertions Properties that must be true in a correct circuit Extensively used in pre-silicon verification
Benefits Automatic continuous checks Significant reduction in search space for root-cause
Implement assertions in silicon Configure instrumentation with assertions
User-defined assertions Library of pre-set assertions
Benefits Automatic continuous checks Significant reduction in search space for root-cause
Implementing AssertionsImplementing Assertions
Use DEMONs and wrappers
Assertions run at speed
Concurrent assertions
Large number of assertions can be run by reusing the fabric for different groups
No need for expected values
Help identifying transient or deep-state functional issues
Configuring AssertionsConfiguring Assertions
Personality Editor
Pre-set library 50+ assert functions
Verilog compiler
What Signals To InstrumentWhat Signals To Instrument
Tap signals identifying important transactions
Identify high-risk areas new IP cores new user-defined logic logic with poor verification coverage logic for new or evolving standards
Tap signals likely to expose errors (signals of interconnected high-risk FSMs)
Tap input signals for assertions in high-risk areas
Wrap signals likely to be modified for what-if experiments for soft-fixes or ECOs for fault/error injection
Infrastructure InvestmentInfrastructure Investment
Observability: 8192 signals tapped
2.1% additional gates
Observability & Control 819 signals wrapped
7.7% additional gates
Example: 5M user gates 10% ratio tapped/wrapped 32bit debug bus PTE with 16 states / 4
branches
TappedSignals
WrappedSignals
PTE Tracer SPN Wrap
1,024 102 1.16% 0.16% 0.11% 0.96%4,096 409 1.16% 0.16% 0.37% 3.84%8,192 819 1.16% 0.16% 0.74% 7.68%
ConclusionsConclusions
A new approach to silicon debug Reconfigurable debug infrastructure On-chip observability and control Support for many different debug paradigms
Advantages Enables in-system at-speed debug and validation Repeatedly configured for different debug structures Accelerates debug in the lab and in the field Eliminates the need for multiple respins
Other applications Performance measurements On-line testing … …