A Posynomial-Based LagrangianA Posynomial-Based LagrangianRelaxation Tuning Tool forRelaxation Tuning Tool forCombinational Gates and Flip-Flops SiziCombinational Gates and Flip-Flops Sizingng

Presenter: Tsung-Tse LinAdvisor: Prof. Chung-Ping Chen

 

Outline• Background and Motivation• The Optimal Algorithm for Sizing Cyclic

Sequential Circuits• Experiment Result• Conclusion

Previous Work• Several convex optimization methods have been prop

osed for sizing combinational circuits.• C.C.P. Chen et al. ”Fast and Exact Simultaneous Gate and

Wire Sizing by Lagrangian Relaxation,”, in TCAD 1999• H. Sathyamurthy et al. formulated the sequential circui

t sizing problem as a nonlinear convex program using the Elmore delay model.• ”Speeding up Pipelined Circuits through a Combination of G

ate Sizing and Clock Skew Optimization”, in TCAD 1998

Thesis Motivation• Circuit tuning for sequential circuits

• Most of the existing circuit tuning algorithms are only for combinational circuit

• However, most of the VLSI circuits contain flip-flops and/or latches

• Therefore, circuit tuning for sequential circuits is crucial

Overall FlowOverall FlowCell Library

Posynomial Model

Posynomial Fitting

Gate-level Netlist

Tuning Tool

Interconnect Data

Optimized Netlist

Flatten the hierarchical netlistTop

A B

C RAMA1 A2

C1 C2

Hierarchical Netlist Flatten Netlist

BRAM C

C1

C2

Top

AA2 A1

Our tool in design flowOur tool in design flowConcept

Architectural Specs

RTL coding & simulation

Logic Synthesis

Pre-Layout STA

Timing Ok?

No

Floorplanning, Placement

Yes

Routing

DRC&LVS

Post-Layout STA

Timing Ok?

No

Tape Out

Yes

Our Tuning Tool

Posynomial Functions

monomials. of sum theisfunction posynomialA function. monomial a

called is and 0 where,xxcx f(x)

as defined,with , :ffunction A n21 a

na2

a1 Rac

RfRR

i

nn

functions. affine oflsexponentia of sum thein tofunction posynomial the

can turn we,log variablesof changingBy ii xy

Modelling in Posynomial Form

kjc

bxc

j

z

m

k

jm

n

i

aij

ij

1 ,0 Subject to

))(( Minimize :Posyfit1 1

2

1

kjc j

aaa

aaa

jjj

jjj

1 ,0 Subject to

)15)127.0c((

)12)355.0c(( Minimize

2k

1jj

2k

1jj

321

321

Sequential Circuits Tuning Problem Formulation

Q

QSET

CLR

DQ

QSET

CLR

D

a5clk

a1clk

a1out

a3

a2

a4a5outa6 1

2

3

4

5 CaTa

CaTa

aDaaDaaDaaDa

aDaaDaaDa

capC

clksetup

clksetup

outclk

outclk

out

out

Njj

11

2

55

6

111

555

331

445

223

224

336

21

subject to

minimize

C:clock, a: arrival time, C:clock, a: arrival time, D:delay, Tsetup:setup timeD:delay, Tsetup:setup time

Lagrangian Relaxation

)(,

,

)( subject to

minimize

,

21

iinputjFFiCaTa

FFiaDa

iinputjFFiaDa

capC

iclkisetupj

ioutiiclk

ijij

Njj

FFi )(

FFici

FFi )(

21

) (

) (

) (

)s,L,cap,(a,

CaTa

aDa

aDa

capCL

iclkisetupj

iinputjji

ioutiiclk

ijijiinputjji

Njj

Primal Primal ProblemProblem

Lagrangian Relaxation

KKT Condition for the Lagrangian Function Solution

m,1,i ,0m,1,i ,0)(

0)()()(11

i

ii

i

l

iii

m

ii

uxgu

xhvxguxf

x1

x2

)ˆ(3 xg

)(2 xg

)(1 xg

)(xf

)0,5(

)2,0(

)ˆ(xf

Unconstrainedminimum

Contours of f)(x

)ˆ(4 xg

)ˆ(x

output(i)kik

input(i)jji

a

:smultiplier timearrival the

on condition optimality required

obtain the we,0 By takingi

L

Iterative Multiplier Adjustment

node.sink the toinputs theofnumber theis N where,/ be to

each assigningby start We

1

j0

N

clkjiinputj

FFiCa

Ta

clkj

iinputjFFia

Da

iinputjFFiaDa

i

setupijsetup

jisetupji

i

jij

i

jij

out

)(

,)(

)(,)(

)(,)(

:follows asgiven methodgradient -sub modified

a using updatey iterativel We

cici

jiji

*

Algorithm Summary

STA Perform B-BFGS-L using

L minimizingby / Solve 2.condition KKT

satisfying smultiplier lagrange of vector initialarbitray :

1:k 1.periodclock

and sizes gate optimal :Output:SEQ_SIZE ALGOTITHM

LRS

strengths drive available tosizes gate Discretize 6.

2 step togo criteria, stoppingan greater th is and in difference If .5

1k :k 4.KKT satisfyingpoint

nearest the toProject adjustment multiplier

tsubgradienafter multiplier : 3.

LRS/λPP

new

new

Experiment Results on RDC Circuits(Run PrimeTime)Netlist Name

Runtime

Gate Count

Original Timing(ns)

After Timing(ns)

Percentage(%)

Ice.v 45.813s

3575 3.30 3.18 3.7

Ieu.v 9m31.84s

17686 6.95 6.65 4.5

Alu.v 6.31s 377 1.81 1.68 7.7

Iqctl.v 9.90s 393 3.06 2.95 3.7

Conclusion• In this thesis, we propose an optimal Lagrangia

n relaxation based gate sizing algorithm for globally sizing industrial library based designs.

• We use nonlinear convex models for accurately representing the gate delays and can size both cyclic and acyclic sequential circuits.

• We can also handle the hierarchy of the synthesized netlist, and integrate our tuning tool to the standard design flow seamlessly.

Q & A• Thank You