234 IEEE ELECTRON DEVICE LETTERS, VOL. 19, NO. 7, JULY 1998

A Possible Mechanism for Reconciling Large Gate-Drain Overlap Capacitance with a Small Difference

Between Polysilicon Gate Length and EffectiveChannel Length in an Advanced Technology PFET

R. Young, L. Su, M. Ieong, and S. Kapur

Abstract—A mechanism is proposed for reconciling an observedlarge gate-drain overlap capacitance with a small differencebetween polysilicon gate length and effective channel lengthin an advanced technology PFET. Dopant in the source-drainextension is assumed to segregate to the Si/SiO2 interface by areversible reaction. It then diffuses along the interface into thechannel region where the dopant is able to return to the bulkSi. By this means a shallow sliver of p-type dopant is formedwhich protrudes laterally from the source-drain extension intothe channel. Simulations with this model are found to matchmeasured PFET device parameters where other assumptions fail.

Index Terms— Capacitance, CMOSFET logic devices,semiconductor-insulator interfaces, semiconductor processmodeling, simulation.

I. INTRODUCTION

I T is commonly assumed that gate-drain overlap capaci-tance ( ) in a FET correlates with , defined here

as the polysilicon gate length minus the effective channellength. For example see [1]–[8]. However, we have recentlyobserved contrary results in an advanced logic technology[9]. Experimental data of 1.12 for the ratio of PFETto NFET (RATIO ), and 0.25 for the ratio of PFET

to NFET (RATIO ) were obtained with identicalpolysilicon gate lengths for the NFET and PFET. Even thoughthe PFET is larger than the NFET , the PFET hasa significantly smaller than the NFET. In this letter wepropose a possible mechanism which is able to explain thisapparent contradiction.

II. PROPOSEDMECHANISM

Loss of dopant dose from bulk Si to the Si/SiOinterfacehas been reported in [10]–[12] with boron from BFimplantsbeing shown to be particularly susceptible to interface doseloss in [12]. The source-drain extension for the PFET’s beingstudied here was indeed created by implantation of BF.Hence, the proposed mechanism includes a model of dopantdose loss to the interface similar to that in [11]. An additionalassumption of the proposed mechanism is that the dopant isallowed to diffuse laterally along the interface much like grain-

Manuscript received July 25, 1997; revised February 25, 1998..The authors are with the IBM Microelectronics Division, Hopewell Junc-

tion, NY 12533 USA.Publisher Item Identifier S 0741-3106(98)04771-5.

Fig. 1. Junction contours near the edge of the gate: (a) no interfacial doseloss, no interfacial diffusion, (b) interfacial dose loss, no interfacial diffusion,and (c) both interfacial dose loss and interfacial diffusion.

boundary diffusion. Because of the concentration gradientalong the interface, the interfacial boron diffuses laterally fromthe extension region into the channel region where boron isreleased from the interface back into the bulk Si by assuminga reversible reaction. Fig. 1 shows the junction contour underthe edge of the gate using three different assumptions. Contour(a) has neither dose loss, nor interfacial diffusion. Contour (b)has dose loss with no interfacial diffusion, and contour (c) hasboth dose loss and interfacial diffusion. The figure shows thatthe proposed model can be used to adjust the shape of thejunction contour from a reentrant situation like (b) to a lateralsurface sliver like (c).

III. SIMULATION RESULTS

In order to test the validity of the simulated lateral pro-files PFET device simulations of 20 device parameters werecompared to measured values. The set of device parameterswith specified tolerances is shown in Table I. The effectivechannel length, , was determined by the shift-and-ratiomethod [13]. However, the conclusions do not depend on thischoice, since other extraction methods were shown toproduce similar values of . Process and device simulationswere done using a modified version of TSuprem-4 [14] andFIELDAY [15], respectively.

0741–3106/98$10.00 1998 IEEE

YOUNG et al.: POSSIBLE MECHANISM FOR RECONCILING LARGE GATE-DRAIN OVERLAP CAPACITANCE 235

TABLE IPFET DEVICE PARAMETERS CHOSEN FORVALIDATION OF TWO-DIMENSIONAL DOPANT PROFILES WITH TOLERANCE FOREACH. A COMPARISON OFMATCHING

BETWEEN SIMULATIONS AND MEASURED PFET PARAMETERS, GIVEN FOUR PROCESSMODEL ASSUMPTIONS, IS SHOWN. IN (A) THE PROCESSMODEL PARAMETERS

FOR THE PFETARE THOSE WHICH GIVE GOOD MATCHING OF NFET DEVICE PARAMETERS. NEITHER DOSE LOSS NORINTERFACIAL DIFFUSION ARE ASSUMED. (B) IS

THE SAME AS (A) WITH THE BORON BULK DIFFUSION INCREASED TOMATCH Cov. CASE (C) IS THE SAME AS (B) WITH THE BORON DOSE LOSS MODEL INCLUDED.(D) IS THE SAME AS (A) WITH OPTIMIZED BORON DOSE LOSS AND INTERFACIAL DIFFUSION MODELS ADDED. SIMULATION ACCURACY IN ALL FOUR CASES IS GIVEN

AS (SIMULATION -MEASUREMENT) DIVIDED BY THE TOLERANCE. RMS IS THE ROOT MEAN SQUARE OF THE SIMULATION ACCURACY VALUES IN EACH COLUMN

Table I also compares the matching of simulation resultsand measured device parameter values for four process modelassumptions. Simulation accuracy is defined as (simulation-measurement)/tolerance. Ideally each of the simulation accu-racy values should be less than 1, for each parameter to fallwithin its tolerance. The RMS value (root mean square ofsimulation accuracy values in each column) is a figure ofmerit for the overall level of matching and should also beless than 1. Table I, column (A), includes no dose loss andno interfacial diffusion. This starting point assumes processparameters which give simulated NFET parameters that are in

good agreement with measured values, includingand .In Table I, column (A), it is seen that the PFET long-channelparameters are well matched and the at isreasonable. However, the and most of the short-channelparameters are not well matched. In Table I, column (B), thereis also no dose loss and no interfacial diffusion. In this casethe boron bulk diffusion constant was increased enough tomatch . Many of the short-channel parameters improvetheir matching, but the and matching both degradeseriously. Table I, column (C) is the same as column (B)with the addition of the dose loss model. Overall matching

236 IEEE ELECTRON DEVICE LETTERS, VOL. 19, NO. 7, JULY 1998

TABLE IIPFET TO NFET RATIOS OF Cov AND �L.

CASES (A)–(D) ARE THE SAME AS IN TABLE I

Fig. 2. Overlap capacitance and effective channel length versus sliver con-centration. Simulation accuracy is (simulation-measurement) divided by thetolerance.

is better. Matching of in particular is improved. However,and several other short-channel parameters are still not

satisfactorily matched. In Table I, column (D), the boronbulk diffusion is assumed to be the same as in column (A).However, both the boron dose loss and interfacial diffusionmodels are included. It is seen that this column gives asignificantly better match to the set of device parameters thanany of the other columns. It is to be noted that this is theonly case in which and are both matched. It is alsosatisfying that the other short-channel parameters as well asthe long-channel parameters are well matched. Table II showsthat RATIO and RATIO are also best matched to theirmeasured values in column (D).

and effective channel length ( ) as a function of thesliver concentration is shown in Fig. 2. For this plot the boronconcentration inside a rectangular region encompassing thesliver was artificially multiplied by a variable factor withoutotherwise changing the shape of the sliver. It is seen that thesimulated values of and both match measurementswell at the same sliver concentration.

IV. CONCLUSIONS

By introducing a new interfacial diffusion mechanism as anaddition to a previously proposed interfacial dose loss model[11], anomalous PFET short-channel measurements were ex-plained. The simulated RATIO was 1.12 in agreement withthe measured value of 1.12. The simulated RATIOwas0.28 in good agreement with the measured value of 0.25. Thismechanism produces a lateral surface sliver in the shape of thejunction contour under the edge of the gate as illustrated inFig. 1, contour (c). The sliver is high enough in concentration

to increase . By its shallow geometry and lateral grading,however, the sliver does not lead to a commensurate increasein . Including the interfacial diffusion mechanism was keyin matching simulated and measured PFET device parameters.From a technological point of view control or elimination ofsuch a feature is of obvious importance for very short-channelPFET’s.

ACKNOWLEDGMENT

R. Gafiteanu did some initial simulations of the sliver con-cept as a summer intern at IBM. The authors would also like toacknowledge useful discussions with M. Hargrove, J. Snare, S.Crowder, Y. Taur, R. Logan, D. Chidambarrao, O. Dokumaci,M. Pelella, and C. Murthy. The samples were processed inthe Advanced Semiconductor Technology Center at the EastFishkill location of the IBM Microelectronics Division. Devicemeasurements were by the Device Engineering Department.

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