a novel single-phase buck pfc acdc converter with power decoupling capability using an active buffer

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 50, NO. 3, MAY/JUNE 2014 1905

A Novel Single-Phase Buck PFC AC–DC ConverterWith Power Decoupling Capability Using

an Active BufferYoshiya Ohnuma, Member, IEEE, and Jun-Ichi Itoh, Member, IEEE

Abstract—This paper discusses a new circuit configuration anda new control method for a single-phase ac–dc converter withpower factor (P.F.) correction and a power pulsation decouplingfunction. The proposed converter can achieve low total harmonicdistortion (THD) on the input current and the power pulsationdecoupling function between the input and output sides, whichallows low output voltage ripple even on a small output energybuffer at the same time using an active buffer. Therefore, theproposed converter does not require large smoothing capacitorsor large smoothing inductors. The buffering energy is stored bya small capacitor, which controls the variation of the capacitorvoltage through the active buffer. In this paper, the fundamentaloperations of the proposed converter are investigated experimen-tally. The experimental results reveal that the input current THDis 1.44%, the rate of the output voltage ripple is 6.33%, and theinput P.F. is over 99%. In addition, a maximum efficiency of over96% is obtained for a 750-W prototype converter.

Index Terms—AC–DC power converters, capacitors, powerconversion.

I. INTRODUCTION

R ECENTLY, single-phase ac–dc converters are widely ap-plied in power supplies of home appliances, such as unin-

terrupted power supplies and battery chargers. In particular, thepower consumption of information technology equipment hasrapidly increased [1]. Therefore, ac–dc converters are prefer-able in terms of high efficiency, low cost, and reduced weight.

In general, the ac–dc power supply for this equipment,which requires a low input voltage, such as a 48-V dc bus, isconstructed of an ac-to-dc front-end converter with a powerfactor (P.F.) correction (PFC) function and an isolated dc–dcconverter. The ac-to-dc front-end converter in the first stage is

Manuscript received November 15, 2012; revised March 4, 2013 andJune 19, 2013; accepted August 3, 2013. Date of publication August 28, 2013;date of current version May 15, 2014. Paper 2012-IPCC-656.R2, presentedat the 2012 IEEE Energy Conversion Congress and Exposition, Raleigh, NC,USA, September 15–20, and approved for publication in the IEEE TRANSAC-TIONS ON INDUSTRY APPLICATIONS by the Industrial Power Converter Com-mittee of the IEEE Industry Applications Society. This work was supported bythe Industrial Technology Grant Program in 2009 from the New Energy andIndustrial Technology Development Organization of Japan.

Y. Ohnuma was with the Department of Electrical Engineering, NagaokaUniversity of Technology, Nagaoka 940-2188, Japan. He is now with Na-gaoka Power Electronics Company, Ltd., Nagaoka 940-2188, Japan. (e-mail:[email protected]).

J.-I. Itoh is with the Department of Electrical Engineering, NagaokaUniversity of Technology, Nagaoka 940-2188, Japan (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIA.2013.2279902

required in order to provide low-input-current harmonics so asto meet various standards, such as IEEE 519 or IEC 61000-3-2 (JIS 61000-3-2). Therefore, a number of PFC converters andcontrol methods have been investigated [2]–[17]. The simplestconfiguration of the ac–dc converter with a PFC function con-sists of a diode rectifier and a chopper circuit.

In dc voltage applications, the PFC circuits are basically cat-egorized as, for example, boost chopper circuits [2]–[7], buckchopper circuits [8]–[12], and buck–boost circuits [13]–[17].The boost chopper circuit is often used in practical applications,because the input current can be easily shaped into a sinusoidalwaveform that achieves a unity P.F. However, the boost choppercircuit has a limited capability in that the output voltage must behigher than the peak ac input voltage. In the case of low-voltageapplications (battery chargers), the high dc bus voltage requiresan additional power conversion, which is typically implementedby a resonant converter. Due to the high dc bus voltage, highvoltage rating of switching devices is applied.

On the other hand, a buck PFC ac–dc converter provides analternative option for low-voltage applications. Unlike in theboost chopper, the output voltage of the buck chopper is lowerthan the peak of the input ac voltage, and this significant featureallows the low voltage rating of switching devices to be usedin the converter, which can significantly reduce the componentcost. On the one hand, depending on the application, a resonantconverter can be excluded from the buck converter topology.

However, the volume of the single-phase buck ac–dc con-verters becomes larger because the use of a large inductor isrequired in order to decouple the power pulsation, which is sub-jected to the power supply frequency. Typically, boost-chopper-type single-phase ac–dc converters require a large smoothingcapacitor, such as electrolytic capacitors. Large electrolyticcapacitors typically have a limited lifetime and increase thevolume of the converter. In contrast, for the same reason, buck-chopper-type single-phase ac–dc converters require a largesmoothing inductor at the dc link part. Since the energy storagedensity of an inductor is smaller than that of a capacitor, single-phase buck ac–dc converters are larger than single-phase boostac–dc converters.

In order to reduce the value of the energy storage com-ponents, a number of strategies, such as dc active filters andpower pulsation decoupling methods, have been proposed [18]–[31]. Moreover, conventional buck PFC ac–dc converters witha power pulsation decoupling function have been investigated[29], [30]. The basic concept is to use an active circuit to

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1906 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 50, NO. 3, MAY/JUNE 2014

Fig. 1. Circuit configuration of the conventional converter.

absorb the power pulsation from the dc link to other energystorage components, which permits a larger fluctuation of thevoltage or current. Therefore, the value of the energy storagecomponents can be reduced. Inverters similar to dc-to-single-phase-ac inverters, such as microinverters and single-phasefuel cell inverters, have been proposed [24]–[28]. However,the additional circuit to absorb the power pulsation requiresmore switches, diodes, and other inductors. Consequently, theadditional circuit increases the size of the converter and the totalpower consumption.

In order to overcome this drawback, this paper introduces anew single-phase buck ac–dc converter with a power pulsationdecoupling function as an ac-to-dc front-end converter. Theproposed converter is constructed based on a buck-type PFCac–dc converter topology using an active buffer [20], whichis composed of two switches and a small capacitor. In otherwords, the proposed converter can control a sinusoidal inputcurrent and can also control the low output dc voltage ripplewithout a large inductor or a large capacitor. The values ofthe active buffer capacitor can be reduced by controlling thecapacitor voltage variation, allowing for the use of small capac-itors such as film capacitors or laminated ceramic capacitors.Therefore, the proposed converter is smaller than conventionalconverters.

The remainder of this paper is organized as follows. First, thecircuit topology and the configuration of the proposed converterare described. Second, the control strategy of the proposedconverter is explained. The passive component used to decouplethe power pulsation is then discussed. The fundamental op-eration and validity of the proposed converter are confirmedexperimentally, demonstrating that the input and output currentwaveforms have few harmonic distortions.

II. CIRCUIT TOPOLOGY

Fig. 1 shows the circuit configuration of the conventionalbuck-chopper-type single-phase ac–dc converter. The conven-tional converter has a low-cost structure because this converterrequires only one switching device and five diodes. However,the buck PFC converter fails to provide a sinusoidal waveformfor the input current at the zero crossings of the input voltage,i.e., during the period when the input voltage is lower than theoutput voltage, the total harmonic distortion (THD) of the inputcurrent and the output voltage ripple become higher because ofthe discontinuous current of the smoothing inductor. Therefore,a large smoothing inductor is required in order to obtain a low-THD input current and a low-ripple output dc voltage.

Fig. 2. Circuit configuration of the proposed converter.

Fig. 2 shows the circuit configuration of the proposed con-verter. The buffer circuit consists of two switching devices (Swa

and Swb), a diode, and a small capacitor. The power pulsationgenerated with twice the power supply frequency is absorbed bythe active buffer capacitor Cdc. If film capacitors or laminatedceramic capacitors can be used, the converter lifetime can beincreased, because the lifetimes of these capacitors are longerthan that of the electrolytic capacitor. The passive componentsof the converter without Cdc are only required at the input andoutput filters in order to eliminate the switching frequency. Inthis paper, a high-speed switching device MOSFET is selectedin order to reduce the filter size.

Fig. 3 illustrates the switching pattern of the proposed circuit.The current path does not occur from the rectifier to theactive buffer capacitor through the switch Swa because theactive buffer capacitor voltage must be higher than the inputvoltage. Therefore, assuming that the output inductor currentis maintained to be constant, the current paths of the proposedconverter have four modes based on the switching pattern. Inmode 1, the output power is directly supplied by an input single-phase source. The buffer power is controlled by modes 2 and 3.In mode 2, the buffer capacitor is discharged. In contrast, inmode 3, the buffer capacitor is charged. Mode 4 is a pass modeof the output inductor current. Thus, the proposed converterperforms the function of a buck chopper (modes 1 and 4) andthe buffering function of the power pulsation (modes 2 and 3).

III. CONTROL STRATEGY

A. Principle of Power Pulsation Compensation

Fig. 4 depicts the principle of power pulsation compensation.When both the input voltage vin and the input current iin havesinusoidal waveforms, the instantaneous input power pin isexpressed as follows:

pin =VINpIINp sin2(ωt)

=1

2VINpIINp − 1

2VINpIINp cos(2ωt) (1)

where VINp is the peak amplitude of the input voltage, IINp

is the peak amplitude of the input current, and ω is the inputangular frequency.

Based on (1), a power pulsation with twice the input fre-quency appears in the input power. In order to decouple this

OHNUMA AND ITOH: NOVEL SINGLE-PHASE BUCK PFC AC–DC CONVERTER WITH POWER DECOUPLING CAPABILITY 1907

Fig. 3. Switching pattern of each mode.

Fig. 4. Compensation principle of the power pulsation.

power pulsation, the buffer circuit instantaneous power pbuf isrequired, as given by

pbuf =1

2VINpIINp cos(2ωt) (2)

where the polarity of pbuf is defined as positive when the buffercapacitor discharges. The mean power of the buffer circuitis zero because the buffer capacitor absorbs only the powerpulsation.

Consequently, the instantaneous output power pout will beconstant

pout =1

2VINpIINp = VOUTil. (3)

B. Control Approach

The proposed converter is controlled by four modes, asshown in Fig. 3. Therefore, assuming that the output inductorcurrent il is continuous, the rectifier current irec and the capac-itor current ic can be expressed as follows:

irec =(dmode1 + dmode3)il

ic =(dmode2 − dmode3)il (4)

where dmode1 through dmode4 are the duty ratios of the respec-tive modes. The duty ratios are constrained by the continuous


current (il), as follows:

dmode1 + dmode2 + dmode3 + dmode4 = 1. (5)

In order to obtain a sinusoidal input current, irec is con-strained as follows:

irec = IINp |sin(ωt)| . (6)

Therefore, dmode1 is controlled by the following equation,based on (4) and (6):

dmode1 =IINp

il|sin(ωt)| − dmode3 (7)

where dmode3 is determined in order to decouple the powerpulsation of the input power supply. The capacitor currentic should be controlled as follows, based on (2), in order tocompensate for the power pulsation:

ic =VINpIINp

2vccos(2ωt) (8)

where vc is the capacitor instantaneous voltage. Substituting (8)into (4) yields

dmode2 − dmode3 = dtempo =VINpIINp

2vcilcos(2ωt) (9)

where the temporary duty dtempo is defined as dmode2 −dmode3. Here, dtempo has two degrees of freedom, which aredecided as follows from the viewpoint of the minimum ic.When the capacitor current ic is positive, i.e., when dtempo ispositive, mode 2 is selected in order to discharge the capacitor.In contrast, when the capacitor current ic is negative, i.e., whendtempo is negative, mode 3 is selected. Therefore, dmode2 anddmode3 are calculated as follows:

⎧⎪⎪⎨⎪⎪⎩

dmode2 =

{dtempo, dtempo ≥ 00, dtempo ≤ 0

dmode3 =

{−dtempo, dtempo ≤ 00, dtempo ≥ 0.

(10)

The ratio of IINp to il can be obtained as follows basedon (3):

IINp

il= 2

VOUT

VINp. (11)

By substituting (11) into (7) and (9), we obtain

dmode1 =2V ∗OUT

VINp|sin(ωt)| − dmode3 (12)

dmode2 − dmode3 = dtempo =V ∗OUT

vccos(2ωt). (13)

Note that VOUT is usually used as a command to control theconverter. Thus, VOUT is replaced by the voltage commandV ∗OUT. Finally, these duty ratios are given by (5), (10), (12) and

(13) in terms of VINp, ω, vc, and V ∗OUT.

Fig. 5. Commands, a carrier pattern, switching patterns, switch voltages, andcurrents (discharge mode).

C. Maximum Output Voltage of the Proposed Converter

In the control algorithm, all duty ratios should be positive,and the sum of the duty ratios should be one, as shown in (5).By substituting (12) into (5), dmode4 can be obtained as follows:

dmode4 = 1−(2V ∗OUT

VINp|sin(ωt)|+ dmode2

). (14)

Based on (14), in order to obtain a positive value of dmode4,the value in brackets should approach one. When ωt is π/2,the value in brackets becomes a maximum. Therefore, we canobtain the following inequalities:

0 ≤ 1− 2V ∗OUT

VINp

V ∗OUT ≤ VINp

2. (15)

Thus, the maximum output voltage of the proposed converter islimited to half the peak amplitude of the input voltage.

D. Pulse Generation Method

Fig. 5 shows three commands, which are obtained by theduties, a carrier pattern, and switching patterns. Since the transi-tion from mode 1 to mode 4 immediately increases the numberof switching times, there is a transition through mode 2 ormode 3. Therefore, three commands dmode1, dmode1 + dmode2,and dmode1 + dmode3 are calculated. Commands are comparedto a triangular carrier, so as to obtain comparison signals s1,s2, and s3, as shown in Fig. 5. The comparison signals areconverted into gate switching signals using Table I.

This method enables switching patterns to be achieved basedon the required ratios of each duty and the required transitionpattern. Note that the proposed converter has an advantage inthat it is not necessary to consider the dead time or the overlap


TABLE IPULSE TRANSFORM TABLE

time for gate signals because all of the switching patterns areused.

Fig. 6 shows a control block diagram of the proposed circuit.Based on (5), (10), (12), and (13), the duty ratio commands arecalculated using the detected single-phase voltage vin, the ca-pacitor voltage vc, the output inductor current il, the commandof the output voltage V ∗

OUT, the minimum voltage of the activebuffer capacitor V ∗

Cmin, and the capacitance of the active buffercapacitor Cdc. The gate pulses are given as shown in Fig. 5and Table I. Note that the capacitor voltage is controlled by aproportional–integral (PI) controller. The method for capacitorvoltage control is described in the next section.

The proposed control, which is shown in Fig. 6, is imple-mented using a digital control system with a digital signalprocessor [(DSP); TMS320C6713 DSP Starter Kit] and a field-programmable gate array (Actel ProASIC Plus APA300). Notethat the controller is not optimized for the proposed circuit. Atypical controller is used to check the fundamental operationof the proposed circuit in our laboratory. The typical controllercan be used in the proposed control method because only simpleequations are used.

E. Control Method of the Capacitor Voltage

Practically speaking, the capacitor voltage does not matchthe theoretical value due to the voltage error resulting from theON-state drop of the power device. Thus, the capacitor voltageis controlled by the PI regulator to the theoretical value.

The capacitor power (capacitor voltage times capacitor cur-rent) corresponds to (2). Therefore, the theoretical value of thecapacitor voltage can be obtained as follows:

t∫t0

vcicdt =

t∫t0

1

2VINpIINp cos(2ωt)dt

vc =

√v2c0 −

poutωCdc

{sin(2ωt)− sin(2ωt0)} (16)

where vc0 and t0 are the initial capacitor voltage and theinitial time of integration, respectively. The output power isobtained by the output voltage command V ∗

OUT and the outputinductor current il. By substituting the minimum capacitorvoltage VCmin into the initial capacitor voltage vc0, we obtainthe following:

vc =

√V 2Cmin − pout

ωCdc{sin(2ωt)− 1}. (17)

The value obtained by subtracting the detected value fromthe theoretical value of the capacitor is fed into the PI regulator,and the output of the PI regulator is then added to the duties,

as shown in Fig. 6. In the proposed control method, the outputof the PI regulator is subtracted from dtempo in order to controlthe capacitor voltage. As a result, dtempo is reduced, and theoutput voltage is distorted without the term (2vc/VINp) ∗ dPI.Therefore, in order to increase dtempo, the period of mode 1is needed in order to control the output voltage to be constant.However, each output voltage in dtempo and dmode1 is different.Therefore, the coefficient 2vc/VINp should be multiplied by theoutput of the PI controller. The purpose of the PI control is tocontrol the average voltage of Cdc. Therefore, the proportionalgain of the PI regulator is not set to be large. If the toleranceof Cdc is large, the average voltage of Cdc cannot be controlledto the command of the capacitor voltage. As a result, the inputcurrent and the output voltage will be distorted.

IV. PASSIVE COMPONENTS

In this section, we discuss the passive components, whichdecouple the power pulsation. If the output power is constant,then the electric storage energy of the passive componentneeded in order to compensate for the power pulsation Wr

is obtained from (2). Thus, the maximum storage energy in apassive component is given by

Wr =1

2VINpIINp

π/(4ω)∫−π/(4ω)

cos(2ωt)dt

=VINpIINp

2ω=

poutω

. (18)

Equation (18) indicates that the storage energy in the passivecomponent is determined by the output power and the inputangular frequency. When this energy is stored by the capacitor,the following equation holds:

Wr =1

2CV 2

Cmax −1

2CV 2

Cmin (19)

where VCmax and VCmin are the maximum and minimumvoltages, respectively, of the capacitor. Therefore, the requiredcapacitance is calculated as follows:

C =2Wr

V 2Cmax − V 2

Cmin

=2Pout

ω (V 2Cmax − V 2

Cmin). (20)

The fluctuation range of the voltage ΔVC is defined as follows:

ΔVC = VCmax − VCmin. (21)

Equation (20) can be described as

C =Pout

ωΔVCVCave(22)

where VCave is the average voltage of the capacitor. Then, theripple ratio KRip is defined as

KRip =ΔVC

2VCave(23)


Fig. 6. Control block diagram of the proposed converter.

Fig. 7. Required value of the passive component of conventional converters.

and the required capacitance is finally calculated as follows:

C =Pout

2ωV 2CaveKRip

. (24)

On the other hand, the energy is stored by the inductor, and therequired inductance is calculated as follows:

L =Pout

2ωI2LaveKRip. (25)

From (24) and (25), the required capacitance (inductance) isproportional to the output power and inversely proportional tothe input frequency, the square of average voltage (current), andthe ripple ratio.

The proposed converter is then compared with conventionalconverters at the required values of the passive components.Fig. 7 shows the required value of the passive component ofthe conventional converters calculated by (24) and (25) underthe condition in which the output power is 750 W and theripple ratio of the output voltage is 10%. Note that these valuesassume that all power pulsation energy can be stored in thepassive components and that the switching ripple is ignored.In the conventional converter, the output voltage (current) andthe ripple rate of the output voltage are equivalent to the averagevoltage of the capacitor VCave (ILave) and the ripple ratio KRip,respectively.

In regard to the inductance of the buck chopper, the requiredinductance increases according to (25) because the outputpower and ripple ratio are constant in (25). On the other hand,for the same reason, the required capacitance of the boostchopper decreases according to the increment of the outputvoltage. Based on Fig. 7, the required values of the conventionalconverter are large because the ripple of the passive components

Fig. 8. Required value of the active buffer capacitor of the proposed converter.

is directly influenced by the ripple rate of the output voltage.In addition, the required values depend on the output voltage.In particular, when the output voltage is 130 V, the requiredcapacitance for the boost-type converter is approximately700 μF, where an electrolytic capacitor is required. Further-more, the required inductance for a buck-type converter underthis condition is 350 mH, which is a very large value for thisoutput power condition. As a result, it is difficult to downsizethe converter.

On the other hand, the proposed converter decouples thepower pulsation by means of an active buffer. The voltage rippleof the capacitor does not affect the output voltage ripple becausethe proposed control method calculates the switching duty inconsideration of the voltage ripple. Therefore, the voltage of theactive buffer capacitor can fluctuate, and the average capacitorvoltage does not depend on the output voltage.

Fig. 8 shows the required value of the passive componentof the proposed converters under the condition that the outputpower is 750 W. As permitted by the maximum capacitor volt-age, the capacitance can be easily reduced. The minimumvoltage of the capacitor is determined by the amplitude inputvoltage; the maximum voltage of the capacitor is constrainedby the allowable voltage of the devices and the capacitor.However, a capacitor that allows high voltage and large currentis required, and a film capacitor or a laminated ceramic capac-itor can be used under this condition. The laminated ceramiccapacitor can be used in order to realize a small converter.

V. EXPERIMENTAL RESULTS

In order to demonstrate the validity of the proposed con-verter, a 750-W class prototype circuit has been tested.Table II shows the experimental parameters. In the prototype,superjunction MOSFETs are selected in order to achieve highefficiency. The input and output filters of a 1-mH inductor anda 3.3-μF capacitor were used. In the experiment, the output


TABLE IISPECIFICATIONS OF THE PROTOTYPE CONVERTER

Fig. 9. Photograph of the main circuit of the prototype converter.

Fig. 10. Experimental results of the proposed circuit. (a) Input and outputwaveforms. (b) Input and capacitor voltage waveforms.

voltage command is set to 130 V, and the output power iscontrolled by the output load.

Fig. 9 shows a photograph of the main circuit. All switchesand diodes are mounted on top of a heat sink. In order toeliminate the effect of line inductance, these switches anddiodes are closely connected. Note that one large heat sink isused for all of the switches and diodes. In this experiment, a

Fig. 11. Experimental waveforms of the diode and buffer output voltages.(a) Voltage waveforms of the diode D1 and the buffer output. (b) Enlargedwaveforms of (a) (Viewpoint A). (c) Enlarged waveforms of (a) (Viewpoint B).

100-μF film capacitor was used. Note that it is not an optimalmaterial for the proposed circuit in order to demonstrate thefundamental performance of the proposed circuit. At the ratedoutput power, the maximum capacitor voltage becomes 357 V,which can be calculated using (20). If the maximum capacitorvoltage can be 500 V, then a 28-μF laminated ceramic capacitorcan be selected. In terms of size reduction, chip-type ceramiccapacitors should be selected. In this case, significant downsiz-ing of the buffer capacitor can be achieved.


Fig. 12. Switching waveforms of Swa and Swb. (a) Voltage waveformsof switches Swa and Swb. (b) Enlarged waveforms of (a) (Viewpoint A).(c) Enlarged waveforms of (a) (Viewpoint B). (d) Enlarged waveforms of(a) (Viewpoint C).

Fig. 10(a) shows the operation input and output waveformsof the proposed converter. Based on the results, sinusoidalwaveforms without distortion are obtained at the input current.In addition, dc waveforms of the output voltage and the outputinductor current without ripple were obtained. Moreover, an in-put P.F. of 99.9% and a high efficiency of 96.4% were obtained.

Fig. 10(b) shows the input and capacitor voltage waveformsof the proposed converter. This figure shows that the pro-posed strategy controlled the capacitor voltage between approx-imately 280 and 360 V at twice the input voltage frequency.

Fig. 11 shows the diode voltage vd1 and the buffer outputvoltage vdc. In the discharge period, when the input voltagebecomes low [Fig. 11(b)], the low input voltage and the ac-tive buffer capacitor voltage are applied to the buffer output.During the charge period, when the input voltage becomes high

Fig. 13. Experimental results for the transient response. (a) Load is changedfrom 40% to 100%. (b) Load is changed from 100% to 40%.

[Fig. 11(c)], the high input voltage and the negative voltage areapplied to the buffer output voltage vdc. The negative voltagecan be calculated in order to subtract the active buffer capacitorvoltage from the input voltage. The differential voltage betweenthe input voltage and the active buffer capacitor voltage isapplied to the diode D1. As a result, the recovery loss can bereduced because the differential voltage is low.

Fig. 12 shows the switching waveforms of Swa and Swb.The active buffer capacitor voltage is always applied to switchSwb. On the other hand, the differential voltage between theinput voltage and the active buffer capacitor voltage is appliedto switch Swa. As a result, the switching loss can be reducedbecause the differential voltage is low.

Fig. 13 shows the transient response of the proposed circuit.The output load was changed from 40% to 100% or from 100%to 40%. The experimental results reveal that the input currenthad a sinusoidal waveform. In addition, the capacitor voltagewas controlled. Moreover, an undistorted direct output voltagewaveform was obtained.

Fig. 14 shows the efficiency and input P.F. of the proposedconverter as functions of the output power. These results revealthat an input P.F. of over 99% and a high efficiency of over 96%were obtained. The P.F. is low in the light-load region becausethe lead current initially flows to the capacitor of the input filter.

Fig. 15 shows the THD of the input current. The minimumvalue for the input current THD is 1.91%. The input currentharmonics in the proposed circuit meet the requirement of thestandard of IEC 61000-3-2.

Fig. 16 shows the ripple rates of the output voltage withrespect to the output power of the proposed circuit and theconventional buck converter, which is connected to the 100-μFcapacitor by an output filter capacitor. As the output power in-creases, the ripple rate of the conventional converter increases.


Fig. 14. Characteristics of efficiency and input P.F. for the proposed circuit.

Fig. 15. THD of the input current.

Fig. 16. Ripple rates of the output voltage.

On the other hand, the ripple rate of the proposed converter isless than 10% for a wide range of output power.

VI. CONCLUSION

We have herein proposed a circuit configuration and a controlmethod for a single-phase ac–dc converter with an active buffer,which is used to decouple the power pulsation between theinput and output sides. The proposed circuit can achieve lowTHD at the input current and can also control the low outputdc voltage ripple. The validity of the proposed control strategywas confirmed experimentally. The power pulsation at twice thefrequency of the power supply can be adequately suppressedusing a buffer capacitor of only 100 μF at 750 W. Finally, theinput current THD was less than 2%, and a unity input P.F. wasachieved.

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Yoshiya Ohnuma (M’13) was born in Yamagata,Japan, in 1985. He received the M.S. and Ph.D.degrees in electrical, electronics, and information en-gineering from Nagaoka University of Technology,Nagaoka, Japan, in 2010 and 2013, respectively.

Since 2013, he has been with Nagaoka PowerElectronics Company, Ltd., Nagaoka, Japan. His re-search interests include power conversion systems,particularly matrix converters, and power factor cor-rection techniques.

Dr. Ohnuma is a member of the Institute of Elec-trical Engineers of Japan.

Jun-Ichi Itoh (M’01) was born in Tokyo, Japan, in1972. He received the M.S. and Ph.D. degrees inelectrical and electronic systems engineering fromNagaoka University of Technology, Nagaoka, Japan,in 1996 and 2000, respectively.

From 1996 to 2004, he was with Fuji ElectricCorporate Research and Development Ltd., Tokyo.Since 2004, he has been an Associate Professor withthe Department of Electrical Engineering, NagaokaUniversity of Technology. His research interests arematrix converters, dc/dc converters, power factor

correction techniques, energy storage systems, and adjustable-speed drivesystems.

Dr. Itoh is a member of the Institute of Electrical Engineers of Japan (IEEJ)and the Society of Automotive Engineers of Japan. He was the recipient ofthe IEEJ Academic Promotion Award (IEEJ Technical Development Award)in 2007. In addition, he was also the recipient of the Isao Takahashi PowerElectronics Award at the 2010 International Power Electronics Conference fromIEEJ, the 58th OHM Technology Award from The Foundation for ElectricalScience and Engineering in November 2010, the Intelligent Cosmos Awardfrom the Intelligent Cosmos Foundation for the Promotion of Science in May2012, and the Third Prize Award from the Energy Conversion Congress andExposition—Asia in June 2013.

a novel single-phase buck pfc acdc converter with power decoupling capability using an active buffer

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