38 Iranian Journal of Electrical & Electronic Engineering, Vol. 10, No. 1, March 2014

A New Low-Voltage, Low-Power and High-Slew Rate CMOS Unity-Gain Buffer M. Piry*, M. Khanjanimoaf* and P. Amiri* (C.A.)

Abstract: Class-AB circuits, which are capable of dealing with currents several orders of magnitude larger than their quiescent current, are good candidates for low-power and high slew-rate analog design. This paper presents a novel topology of a class AB Flipped Voltage Follower (FVF) that has better slew rate and the same power consumption as the conventional class-AB FVF buffer previously presented in literature. It is thus suitable for low-voltage and low-power stages requiring low bias currents. These buffers have been simulated using 0.5 µm CMOS Technology models provided by IBM. The buffer consumes 16 µA from a 0.9 V supply and has a bandwidth of 52 MHz with an 18 pF load. It has a slew rate of 10.3 V/µs and power consumption of 36 µw. Keywords:Class-AB Circuits, CMOS Integrated Circuits, Flipped Voltage Follower, High Slew Rate Buffers,Level Shifting Techniques.

1 Introduction1 Voltage follower which is here denoted as VF, are widely used as output stages of opamps or in standalone configuration for signal conditioning, to accurately force an input voltage to an output load with both high input and low output impedance [1]. The conventional configuration of a VF is the voltage follower shown in Fig. 1-a. It has an output impedance of Rout = 1/gm (~ 2 kΩ) [2] and positive slew rate SR = ID2/CL. Notation CL is the load capacitance, ID2, the drain current of transistor M2 and gm, the small signal transconductance.

This VF is biased on the source side with a constant current source (M2) which ideally keeps a constant gate-to-source voltage in M1. This causes output voltage variations to follow the input voltage with a gate to source DC level shift. In practice this VF suffers from some problems like, not enough low output impedance, dependence of drain current of M1 on Iout and nonsymmetrical slew rate.

The FVF [3] shown in Fig. 1-b is an improvement to a conventional VF. The FVF has a constant current through transistor M1, independent on the output current. Because of the shunt feedback [4], the output impedance is decreased to:

Iranian Journal of Electrical & Electronic Engineering, 2014. Paper first received 7 Aug. 2013 and in revised form 1 Oct. 2013. * The Authors are with the Department of Electrical Engineering, Shahid Rajaee Teacher Training University, Tehran, Iran. E-mails: Piry.milad@yahoo.com, m_khanjani69@yahoo.com and pamiri@srttu.edu.

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This is bigger than the voltage gain of conventional VF. The circuit in Fig. 1-b is able to source a large current but its sinking capability is limited by the drain current of M3.

To overcome this problem, circuit in Fig. 1-c [5-7] is used. Under quiescent conditions, every transistor is in saturation region and no current is delivered to the load. Neglecting second order effects, transistor M4 copies the drain current of transistor M1. Therefore the total current taken from the supply voltage is 2Ib ( = 2ID3) which increases the power consumption of the circuit.

In this paper a very simple, low-voltage class-AB structure is proposed which is able to take current from supply sources only when the load requires it, so the power consumption decreases, and the slew rate increases, thus it can be used in low-voltage and low-power amplifiers as a level shifter [8].

The proposed structure has been simulated using the models of the IBM CMOS 0.5 µm technology, in order to compare its performance with the other buffers in terms of settling time, bandwidth, output impedance, power consumption and total harmonic distortion.

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Piry et al: A New Low-Voltage, Low-Power and High-Slew Rate CMOS Unity-Gain Buffer 43

increases to 72 µW, which is 30 µW larger than power consumption of circuit Fig. 5. Note that since in these circuits, transistors are operation in strong inversion they are not capable to operate under ultra-low-power application [13]. The bandwidth of second proposed circuit is larger than other buffer configurations presented in literature except the buffer Fig. 1-c. Thus it can be used in high frequencies. Also it can be seen that the second proposed circuit has the largest FOM among Fig. 3-d and Fig. 1-c.

5 Conclusion A new class-AB unity-gain buffer based on the

Flipped Voltage Follower (FVF) has been proposed. This circuit can be operated at a low voltage and low power. With respect to other class-AB stages based on the FVF topology, it has superior slew rate with low power consumption. This novel buffer has also low output impedance. The characteristics of the proposed circuit were validated by simulations.

Table 2 Comparison of buffers.

Circuit Technology Voltage Supply

ID (µA)

P (µw)

BW SR+

(V/µs)SR-

( V/µs) FOM Rout (Ω)

Gain (dB) THD HD2

(dB)HD3 (dB)

Fig. 5 Second

proposed circuit

0.5 µm 0.9 V 16 36 76 MHz CL=10 pF 10.3 10.3 0.28 210 -0.35

-50 dB 200 mVPP

1 MHz -53 -54

Fig. 3-d First

proposed circuit

0.5 µm 0.9 V 16 18 68 MHz CL=10 pF 2.7 5.4 0.23 489 -0.2

-45 dB 200 mVPP

1 MHz -45 -60

Fig. 1-c Class-AB [7] 0.5 µm 1.5 V 20 36 87 MHz

CL=10 pF 6.1 6.1 0.17 220 -0.2 -55 dB

200 mVPP 1 MHz

-56 -62

Buffer [1] 65 nm 1.2 V 10 - 100 MHzCL=2 pF - - - 760 -0.4 - - -

FVF [3] 65 nm 1.2 V 7.8 - 30 MHz CL=2 pF - - - 540 -0.6

- - -

SDP [5] 0.5 µm 3 V 30 - 11 MHz CL=10 pF - - - 2K -

-59 dB 300 mVPP

2 MHz - -

DFVF [5] 0.5 µm 3 V 30 - 70 MHz CL=10 pF - - - 40 -

-52 dB 300 mVPP

2 MHz - -

CASDPFVF [5] 0.5 µm 3 V 30 - 70 MHz

CL=10 pF - - - 0.5 - -52 dB

300 mVPP 2 MHz

- -

References [1] F. Centrurelli, P. Monsurro and A. Trifiletti, “A

Class-AB Flipped Voltage Follower Output Stage”, IEEE (2011) 20th European Conference on Circuit Theory and Dedsing (ECCTD), pp. 757-760, Aug. 2011.

[2] B. Razavi, Design of Analog CMOS Integrated Circuits, New York: McGraw-Hill, 2001.

[3] R.G. Carvajal, J. Ramirez-Angulo, A. Lopez-Martin, A. Torralba, J. Galhn, A. Carlosena and F. Mufioz, “The Flipped Voltage Follower: A useful cell for low-voltage low-power circuit design”, IEEE Transactions on Circuits and Systems I, Vol. 52, No. 7, pp. 1276-1291, July 2005.

[4] H. Faraj Baghtash, S. J. Azhari and Kh. Monfaredi, "A Novel Very High Performance CMOS Current Mirror With Extremely Low Input and Ultra High Output Resistance", Iranian

Journal of Electrical & Electronic Engineering, Vol. 7, No. 4, pp. 235-240, Dec. 2011.

[5] J. Ramirez-Angulo, S. Gupta and R. G. Carvajal, “New Improved CMOS Class-AB Buffers Based on Differential Flipped Voltage Followers”, IEEE International Symposium on Circuits and Systems, May 2006.

[6] J. Ramirez-Angulo, S. Gupta and R. G. Carvajal, A. Torralba, M. Jimenez and F. Munoz, “Comparison of Conventional and New Flipped Voltage Structures with Increased Input/output Signal Swing and Current Sourcing/Sinking Capabilities”, IEEE International Symposium on Circuits and Systems, Vol. 2, pp. 1151-1154,Aug. 2006.

[7] M. Jimenez, A. Torralba, R. G. Carvajal and J. Ramirez-Angulo, “A new low-voltage CMOS unity-gain buffer”, IEEE Int. Symposium on Circuits and Systems, May 2006.

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44 Iranian Journal of Electrical & Electronic Engineering, Vol. 10, No. 1, March 2014

[8] S. H. Mirhosseini and A. Ayatollahi, "A Low-Voltage, Low-Power, Tow-Stage Amplifier for Switched-Capacitor Application in 90 nm CMOS Process", Iranian Journal of Electrical & Electronic Engineering, Vol. 6, No. 4, pp. 199-204, Dec. 2010.

[9] J. Ramirez-Angulo, M. S. Sawant, R. G. Carvajal and A. J. Lopez-Martin, “Cascode Mirrors and Telescopic Op-Amps”, IEEE Int. Symposium on Circuits and systems, May 2006.

[10] M. Bikumandla, J. Ramirez-Angulo, C. Urquidi, R. G. Carvajal and A. J. Lopez-Martin, “Biasing CMOS amplifiers using MOS transistors in sub-threshold region”, IEICE Electronics Express, Vol. 1, No. 12, pp. 339-345, Sep. 25, 2004.

[11] G. Khodabandehloo, S. Mirzakuchaki and G. Karimi, “Modeling and Simulation of Substrate Noise in Mixed-Signal”, Iranian Journal of Electrical & Electronic Engineering, Vol. 2, No. 1, pp. 8-15, Jan. 2006.

[12] R. Mirzalou, A. Nabavi and Gh. Darvish, “A Highly Linear LNA with Noise Cancellation for 5.8-10.6 GHz UWB Receivers”, Iranian Journal of Electrical & Electronic Engineering, Vol. 8, No. 3, pp. 234-242,Sept. 2012.

[13] E. Farshidi, "A Micropower Current-Mode Euclidean Distance Calculator for Pattern Recognition”, Iranian Journal of Electrical & Electronic Engineering, Vol. 5, No. 1, pp. 42-50, March 2009.

Milad Piry was born in 1990 in Tehran. He received the electrical engineering in 2013 from Shahid Rajaee Teacher Training University (SRTTU Tehran, Iran). He is currently pursuing his education to get MS. degree in Sharif University of Technology in Microelectronics. His research interest is to design low- voltage and low-power

analog integrated circuits, especially the design of operational amplifiers.

Mona Khanjanimoaf was born in 1991 in Bandar-e Anzali. She received the electrical engineering in 2013 from Shahid Rajaee Teacher Training University (SRTTU Tehran, Iran). Her research interest is to design Analog integrated circuit, especially the design of low-voltage and low-power circuits.

Parviz Amiri was born in 1970, received B.S degree from University of Mazandaran in 1994, M.S from Khajeh Nasir Toosi University (KNTU Tehran, Iran) in 1997, and his Ph.D. from University of Tarbiat Modares (TMU Tehran, Iran) (2010), all degrees in electrial engineering (electronic). His main research internest include

electronic circuit design in industries. His primaryresearch interest is RF and power circuit design. He is currently with the department of electrical engineering Shahid Rajaee Teacher Trainning University in Tehran, Iran.

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