IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 2, FEBRUARY 2007 219

A New Analog Buffer Using Low-TemperaturePolysilicon Thin-Film Transistors for

Active-Matrix DisplaysIlias Pappas, Stilianos Siskos, Member, IEEE, and Charalambos A. Dimitriadis, Member, IEEE

Abstract—In this paper, a new source-follower-type ana-log buffer for active-matrix displays, designed by using low-temperature polysilicon thin-film transistors (TFTs), is proposed.The buffer, consisting of five n-type polysilicon TFTs, one biasvoltage, and an additional control signal, exhibits high immunityto threshold voltage and mobility variations. The functionality ofthe proposed buffer was verified by HSPICE simulations. In orderto obtain realistic simulations, the TFT model parameters usedfor the simulations were extracted from fabricated TFTs usingthe Silvaco tools (ATLAS). The proposed buffer has 7-bit outputvoltage with the dynamic output voltage range of 7.5 V rangingfrom 2.5 to 10 V and with resolution up to 0.03 V.

Index Terms—Active-matrix displays (AMDs), analog buffer,polysilicon thin-film transistors (TFTs).

I. INTRODUCTION

LOW-TEMPERATURE polysilicon thin-film transistors(TFTs) have been widely investigated due to their poten-

tial applications in large-area electronics [1], such as displays,memories, and scanners [2], [3]. Despite the similarities be-tween polysilicon TFTs and the commonly used MOSFETs,a number of key differences exist. The main reason causingthese differences is that, instead of single-crystal silicon wafer,a typical heat-sensitive material, glass, or quartz is usually used.Due to such a substrate, TFTs are three terminal devices withthe substrate contact being absent. The presence of an insulatingsubstrate provides an ideal isolation of each device and negli-gible parasitic capacitance [4]. Furthermore, the higher carriermobility of polysilicon TFTs, compared to the mobility ofamorphous silicon TFTs [5], leads to integration of the drivingand the peripheral circuits of a display device by using onlythe polysilicon TFT technology, resulting in reduction of thefabrication cost.

The major disadvantages of polysilicon TFTs are the largevariations of the threshold voltage and carrier mobility fromtransistor to transistor [6]. These variations are caused becauseof the random distribution of the grain boundaries within thechannel of the transistor [7]. Across a 2.7-in diagonal display[8], the threshold-voltage variation is about 300 mV and it can

Manuscript received July 19, 2006; revised October 17, 2006. This work wassupported in part by the Greek Ministry of Education within the frame of theresearch program PYTHAGORAS. The review of this paper was arranged byEditor H.-S. Tae.

The authors are with the Department of Physics, Aristotle University ofThessaloniki, 54124 Thessaloniki, Greece.

Digital Object Identifier 10.1109/TED.2006.888720

be up to ±1 V in some displays with large substrate area [5].These disadvantages make the design of analog drivers difficultand leads to nonuniformity of the brightness and poor grayscaleaccuracy.

During the last decades, liquid-crystal displays (LCDs) haveemerged on almost all types of display devices; from watchesto computers and projection TVs. Display addressing (driving)techniques have a major influence on the LCD image quality.The addressing techniques can be classified in three essentialtypes namely: direct (static) addressing; passive matrix address-ing; and active-matrix (AM) addressing. The AM addressingtechnique is used in high-information content displays [9] andis the most commonly used addressing technique in LCDs.

Since active-matrix LCD (AMLCD) pixels use voltage asdriving quantity, the nonuniformity of the polysilicon TFTthreshold voltage is critical. Many compensation methods forthe variation of the polysilicon-TFT characteristics have beenproposed [10]–[13]. These methods either require a number ofTFTs used as switches for sampling the threshold voltage anda capacitance for storing the threshold voltage [12] or they usedifferent ways of charging, such as bootstrapping [11], [13].

In this paper, an improved source-follower-type analog bufferis proposed, which can be used as data voltage driver forAM-display (AMD) applications. The main advantages of theproposed buffer are that the new buffer presents high immunityto threshold voltage and to mobility variations. Also, it iscapable to drive large-load capacitance in large-area panels. Itconsists of five n-type TFTs, one bias voltage (Vbias) dependingon the input voltage Vin, and one additional control signal.The proposed buffer does not require storage capacitor for thethreshold-voltage variation cancellation, leading to high-speedoperation.

II. PROPOSED ANALOG-BUFFER CIRCUIT

Fig. 1 shows the proposed analog buffer and its timingdiagram. As shown in Fig. 1, the proposed analog buffer isa source-follower-type buffer. The operation of the buffer isbased on applying the value of the input-voltage level Vin tothe load capacitance Cs. Therefore, the gate voltage of thedriver transistor M4 needs to be: VG4 = Vin + VTH, whereVTH is the threshold voltage of M4. For the right operation ofthe buffer, we assume that M1, M2, and M4 share the sameelectrical characteristics, such as threshold voltage. In practicalapplications, this can be achieved when the transistors areplaced close enough on the same wafer and fabricated under the

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220 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 2, FEBRUARY 2007

Fig. 1. Proposed source-follower-type analog buffer and its timing diagram.

same polysilicon growth and process conditions. The detailedoperation of the buffer is divided in three phases.Phase 1—(Capacitance Discharge): During the first phase,

the control signal (S), the bias voltage (Vbias), and the input-voltage-level signal (Vin) are low, so that the transistor M5is only turned-on, since the complement value of the controlsignal S is supplied to the gate of M5 and the load capacitanceis discharged through M5.Phase 2—(Node-A Charge): During the second phase, Vbias

and Vin signals are applied on the gates of the transistorsM1 and M2, respectively, which have a gate-width ratio of4 : 1. The value of the supply voltage Vdd has to be selectedcarefully. When the value of Vdd is small, the buffer will notbe able to load the large capacitance Cs, whereas when thevalue of Vdd is high, the operation point of the transistors M1and M2 will enter the kink-effect region. In this case, in theexpression of the drain–current, the impact-ionization effecthas to be taken into account. Transistors M1 and M2 have tooperate in the saturation region and before the onset of the kinkregion. Therefore, the drain–current can be described by therelationship [13]

ID =12k(VGS − VTH)2, k = µCox

W

L(1)

where µ is the electron mobility, W is the gate width, L isthe gate length, and Cox is the gate-oxide capacitance per-unitarea.

Transistors M1 and M2 share the same drain–current becauseof their cascade connection and, by applying (1), it is obtained:

I = ID1 = ID2 (2)

or12k1(VGS1 − VTH,1)2 =

12k2(VGS2 − VTH,2)2 (3)

where the subscripts 1 and 2 refer to the corresponding parame-ters of the transistors M1 and M2, respectively.

The voltage at node A is calculated by taking into accountthat M2 has a four times larger gate width than M1 andassuming that the electron mobility and the threshold voltageof the transistors are identical. Thus, k1 = 4k2, which leads tothe relationship:

(VGS1 − VTH)2 = 4(VGS2 − VTH)2 (4)

or

(VGS1 − VTH) = 2(VGS2 − VTH). (5)

The voltage Vbias is selected to be equal to 3Vin. Therefore,VGS1 = Vbias − VA = 3Vin − VA and VGS2 = Vin. Applyingthese relationships to (5), we obtain

3Vin − VA − VTH = 2(Vin − VTH) (6)

or

VA = Vin + VTH. (7)

The above equation shows that when the selected bias voltageis equal to 3Vin, node A will be charged to the proper voltage.Phase 3—(Load-Capacitance Charge): At the beginning of

the third phase, the control signal (S) is high, making transistorM3 to turn-on. Since the voltage at node A has the valueestimated in phase 2, the input voltage will be transferred tothe load capacitance, i.e., the output voltage will be the same asthe input voltage. The voltages Vin and Vbias are low, causingtransistors M1 and M2 to turn off during this phase in order toreduce the power consumption of the buffer. This will not affectthe operation of the buffer, because the voltage at node A cannotbe discharged, since M2 is turned off and node A is connectedto the gate of M4.

III. SIMULATION SETUP

A. Simulation Parameters

The verification of the theoretical analysis of the bufferwas made through simulations using Synopsys HSPICE. Thepolysilicon-TFT model used for the simulations was theRensselaer Polytechnic Institute (RPI) polysilicon-TFT model,level 62 [14]. The supply voltage Vdd was 21 V, and theload capacitance was 2 pF. Vdd has to be 21 V in order toensure that the transistors will be working in saturation voltageand the value of the load capacitance is typical for AMLCDapplications. The input-voltage level was varied from 2.5 to10 V. The upper input-voltage-level limit was set, because thehighest voltage available in AMDs is 30 V [15]. Therefore,there is a limitation of the bias voltage Vbias, which is equal to3Vin. If higher voltages in AMDs are available, then the upperlimit of Vin can be increased. In AMD applications, the requiredbias-voltage levels are exactly as many as are the input-voltagelevels, which can be generated by a voltage generator designedfor TFT–LCD flat panels [16]. The bias-voltage generator will

PAPPAS et al.: NEW ANALOG BUFFER USING LOW-TEMPERATURE POLYSILICON TFTs 221

TABLE ICHANNEL WIDTH (W ) AND CHANNEL LENGTH (L) OF THE USED POLYSILICON TFTS

TABLE IIVALUES OF THE EXTRACTED TFT PARAMETERS

share the same control signals as the input-voltage generator,since the two voltages will be supplied simultaneously at theproposed driver. The channel dimensions of the used transistorsare presented in Table I.

B. TFTs Parameter Extraction

In order to ensure that the simulation results are realistic,the values of the RPI-model parameters were extracted fromfabricated TFT devices using the Silvaco tools (ATLAS). Theoutput and transfer characteristics of the fabricated TFTs weremeasured experimentally.

The used polysilicon TFTs were fabricated on fused quartz-glass substrates, covered by 200-nm-thick SiO2, which wasdeposited by electron cyclotron resonance–plasma-enhancedchemical vapor deposition (ECR-PECVD). First, amorphousSi films (about 50 nm thick) were deposited by low-pressureCVD at the temperature of 425 ◦C and a pressure of 1.1 torrusing Si2H6 as reactant gas. Then, the amorphous Si films weretransformed into polycrystalline phase by furnace annealingat 600 ◦C for 24 h in nitrogen ambient [solid-phase crystal-lization (SPC)]. Such polysilicon films have a high densityof intragrain defects that cause decrease in the field-effectmobility and increase in the threshold voltage of the TFTs[17]. However, application of excimer-laser annealing to theSPC polysilicon films was found to effectively reduce theintragrain-defect density, while the mean grain size remainsunchanged [17]. For this reason, the SPC films were irradiatedby XeCl excimer laser (λ = 308 nm, 23 shots) with energydensity 435 mJ/cm2. A standard self-aligned NMOS processwas used to fabricate devices with a gate width W varyingfrom 10 to 100 µm and gate length varying from 4 to 20 µm.A SiO2 layer of thickness 60 nm deposited by ECR-PECVDat 100 ◦C was used as a gate insulator. From a large num-ber of fabricated TFTs, we have selected transistors closelylocated on the same wafer with channel dimensions W/L =10 µm/10 µm, 40 µm/10 µm, 100 µm/10 µm, which wereused for the design of the proposed buffer. The output and

transfer characteristics of these transistors were measured atroom temperature using a computer-controlled system includ-ing a Keithley 617 electrometer and two Keithley 230-voltagesources.

In the next step, using the ATLAS program of the Silvacotools [18], the cross sections of the transistors were describedwith exactly the same type of materials for each region ofthe transistors. Then, the measured characteristics of the tran-sistors were imported into the ATLAS program. The transfercharacteristics were measured at drain voltage Vd = 0.1 V andVd = 10 V. Optimization of the parameters was performed inorder to achieve good correlation between measured character-istics and characteristics reproduced with ATLAS. The basicparameters, among others, which were extracted for each oneof the three transistors, are presented in Table II. From Table II,it can be seen that the selected TFTs have almost similar theparameters of the threshold voltage and the field-effect mobilityas expected, since the transistors are closely located on thesame wafer and they were fabricated under the same polysilicongrowth and process conditions.

The extracted values of the RPI-model parameters wereinserted into HSPICE, and the characteristics of each transistorwere reproduced again. Fig. 2 shows the measured and simu-lated transfer characteristics of the three transistors for drainvoltage Vd = 0.1 V and Fig. 3(a)–(c) shows the correspondingoutput characteristics. Both ATLAS- and HSPICE-simulatedinput and output characteristics are represented in Figs. 2 and 3,respectively. The measured and simulated characteristics are ingood agreement, with a deviation between them by about 2%.The good correlation between measured and simulated char-acteristics confirms that HSPICE simulations are realistic and,thus, the functionality of the proposed analog buffer can beensured.

IV. SIMULATION RESULTS

Fig. 4(a) shows the simulation results of the proposedbuffer, with the input-voltage levels varying from 2.5 to 10 V.From Fig. 4(a), it is clear that the output voltage follows the

222 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 2, FEBRUARY 2007

Fig. 2. Measured and simulated transfer characteristics of polysilicon TFTs atVd = 0.1 V.

Fig. 3. Measured and simulated output characteristics of polysiliconTFTs with channel dimensions: (a) W/L = 10 µm/10 µm. (b) W/L =40 µm/10 µm. (c) W/L = 100 µm/10 µm.

input-voltage levels, indicating that the dynamic output voltagerange of the buffer is 7.5 V. Fig. 4(b) shows the offset voltage(Vout − Vin) versus the input voltage of the buffer. In the worstcase, the error between input voltage and load-capacitance volt-age is 2%, when the input-voltage level is equal to 10 V. Thiserror is caused because of the slight difference in the thresholdvoltages of the transistors M1, M2, and M3 (about 2%). Furtherimprovement in the performance of the buffer can be achieved,

Fig. 4. (a) Simulation results of the proposed analog buffer when the input-voltage levels vary from 2.5 to 10 V. (b) Offset voltage (Vout − Vin) versusinput voltage Vin.

Fig. 5. Simulation results when the input voltage varies from 5 to 5.3 V withinput-voltage-level step of 0.03 V, in order to determine the resolution of theproposed buffer.

if the variation in the threshold voltage of the transistors will bereduced. The response time of the buffer, i.e., the time neededfor the output voltage to reach the 90% of its nominal value,is 7 µs.

Fig. 5 shows the performance of the buffer with the input-voltage levels varying from 5 to 5.3 V with step of 0.03 V,which is an enlargement of the figure obtained for wider input-voltage range (not shown), in order to resolve more clearly thebuffer performance. Even with this small-input-voltage step,the performance of the buffer is very good. The input-voltagelevel step of 0.03 V corresponds to the resolution of the buffer,measured within the entire input-voltage range varying from2.5 to 10 V. For input voltages ≥ 9.5 V, the resolution isincreased slightly to the value of about 0.04 V, caused by the

PAPPAS et al.: NEW ANALOG BUFFER USING LOW-TEMPERATURE POLYSILICON TFTs 223

Fig. 6. Monte Carlo analysis of the proposed buffer with input-voltage levels4.5, 5.5, and 6.5 V and standard deviation of the threshold voltage ±20% fromits nominal value of 1.91 and 1.89 V for the transistors M2 and M4, respectively.For each Vin, the simulated output voltages are represented for 30 pairs of VTH

values, randomly selected from the threshold-voltage Gaussian distributions ofthe transistors M2 and M4.

increase of the offset voltage. In the AMD applications, thefunctionality of the pixels requires different voltage levels forthe liquid-crystals gray-scale [15]. For high data voltages, thewidth of the voltage level corresponding to 1 bit of the gray-scale, is larger than the level width at lower data voltages [15].When the proposed buffer is used as data voltage driver forAMLCD applications, its resolution will be determined fromthe offset voltage, because this is the smaller voltage-levelwidth that can be produced. As shown in Fig. 4(b), the offseterror is lying within the region of 0.1 to 0.2 V for high inputvoltages and is below 0.1 V at small input voltages. This meansthat the output voltage of the buffer can have about 80 volt-age levels of different voltage widths, suitable for AMLCDs,namely the ability of the buffer is 6-bit output-voltage levels insuch applications.

Fig. 6 shows the Monte Carlo analysis of the proposed buffer,for the three different input-voltage levels of 4.5, 5.5, and 6.5 V.The Monte Carlo analysis was implemented in order to deter-mine the effect of the threshold-voltage variation on the perfor-mance of the buffer. For Monte Carlo analysis of the transistorsM2 and M4, we assumed a Gaussian distribution of the thresh-old voltage with standard deviation ±20% from their nominalvalues of 1.91 and 1.89 V, respectively. Such a distributionfor the threshold voltage was found from statistical analysis ofthe device parameters, obtained from measurements in a largenumber of similar technology TFTs [19]. As shown in Fig. 6,the performance of the buffer is deteriorated as the threshold-voltage variations are increased. Furthermore, the offset erroris increased as the input-voltage level is reduced. In this case,when the deviations of the threshold voltages were larger than15%, the offset error was up to 7%. For larger input-voltagelevels, the buffer exhibits higher immunity to threshold-voltagevariations, since the offset error was up to 4%. Finally, a MonteCarlo analysis was implemented with both threshold voltageand mobility distributions. The distribution of the thresholdvoltage was the same as the previous, and the distribution ofthe mobility of M1 was a Gaussian one with standard deviation±15% from their nominal value of 110 cm2/V · s. This is theworst case analysis, and the offset was up to 11%.

V. CONCLUSION

In this paper, a new source-follower-type analog buffer forAMD applications is presented, using low-temperature poly-silicon TFTs. The proposed buffer consists of five n-channelpolysilicon TFTs, one bias voltage, and an additional controlsignal, exhibiting high immunity to the threshold-voltage vari-ation of the TFTs. The proposed circuit is a 7-bit analog buffer,with dynamic output-voltage range of 7.5 V, ranging from 2.5to 10 V and with resolution 0.03 V. The benefit of this bufferis the absence of a capacitor for the threshold-voltage-variationcancellation, which improves the speed of the buffer. The ver-ification of the functionality of the proposed buffer was madethrough simulations. For realistic simulations, the device para-meters were extracted with the Silvaco tools in fabricated TFTs,with channel dimensions as those used in the proposed buffer.

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Ilias Pappas was born in Ioannina, Greece, in1980. He received the B.Sc. degree in physicsand the M.Sc. degree in electronics engineer-ing from the Aristotle University of Thessaloniki,Thessaloniki, Greece, in 2002 and 2005, respec-tively, where he is currently pursuing the Ph.D.degree in polycrystalline-silicon TFTs.

He is currently with the Department of Physics,Aristotle University of Thessaloniki, Thessaloniki.His current research interest includes design of ana-log blocks using polysilicon TFTs and electricalcharacterization of TFT devices.

Stilianos Siskos (M’96) was born in 1956. He re-ceived the B.Sc. degree in physics from the AristotleUniversity of Thessaloniki, Thessaloniki, Greece, in1980, and the M.Sc. and Ph.D. degrees in electronicsfrom the University of Paul Sabatier de Toulouse,Toulouse, France, in 1983.

He was a Lecturer at the Polytechnic School,Thessaloniki, from 1985 to 1989. In 1989, he joinedthe Electronics Laboratory, Physics Department,Aristotle University of Thessaloniki, Thessaloniki,as a Lecturer and, currently, as an Associate Pro-

fessor. His current research interests include analog integrated-circuit design,mixed built-in signal structures, current-mode integrated-circuit design, sensor-interfacing integrated circuits, low-energy FPGA design for embedded systems,design of signal-processing circuits, and low-voltage analog integrated circuits.

Charalambos A. Dimitriadis (M’90) was born inNaousa, Greece, in 1950. He received the degree inphysics (with Honors) from the Aristotle Universityof Thessaloniki, Thessaloniki, Greece, in 1974, andthe M.Sc. and Ph.D. degrees in solid-state electron-ics from the University of Manchester Institute ofScience and Technology, Manchester, U.K., in 1976and 1979, respectively.

In 1985, he was elected Lecturer, in 1988, anAssistant Professor, in 1992, an Associate Professor,and in 2001, a Professor in the Physics Department,

Aristotle University of Thessaloniki. Between June 1988 and February 1989, hespent his sabbatical at the Max-Planck Institute, Stuttgart, Germany, workingon the growth and characterization of iron disilicide. Between May 1996 andOctober 1996, he spent his sabbatical at the Laboratiore de Physique desComposants a Semiconducteurs, Grenoble, France, working on low-frequencynoise characterization of semiconductor devices and hot-carrier effects in sub-micrometer MOSFETs. Between May 1998 and July 1998, he was an InvitedProfessor at the Laboratiore de Physique des Composants a Semiconducteurs,working on low-frequency noise characterization and hot-carrier effects inpolysilicon TFTs. Since September 2001, he has been a Director of the SolidState Physics Group, Physics Department, Aristotle University of Thessaloniki.He is author or coauthor of more than 200 publications in referred internationaljournals and conferences. His current areas of research are in nanodevices,polysilicon TFTs, and low-frequency noise in semiconductor devices.