A Multiple-Crystal Interface PLL withVCO Realignment to Reduce Phase

Noise

Sheng Ye1,2, Lars Jansson2, Ian Galton1

UC San Diego 1

Silicon Wave Inc. 2

Outline

• Motivation

• Proposed PLL architecture

• Theoretical analysis

• Measured results

• Summary

Clock Generation for Bluetooth

• Clock generator phase noise requirements:1 MHz: low (e.g., -140dBc/Hz @ 20kHz)32 MHz: moderate (e.g., -97dBc/Hz @ 20kHz)

Bluetooth Transceiver

ReferenceClock

Generator

UHFPLL

1 MHz

32 MHzData

Converters

Clock Generation For Bluetooth

Objective: Requirement:• Low cost ⇒ multiple crystal compatibility• High integration ⇒ use ring VCO• Low complexity ⇒ use integer-N PLL

Bluetooth Transceiver

ReferenceClock

Generator

UHFPLL

1 MHz

32 MHzData

Converters

. . .

12 MHz

19.68 MHz

19.8 MHz

Host Devices

The Problem with a Conventional PLL

⇒ bandwidth > 100 kHz

⇒ bandwidth < 25 kHz• Stability requirement• Noisy ring VCO• Low noise spec

19.68MHz 96MHz

PFDCHP VCOLPF

÷ 200

÷ 41

480kHz

÷ 3

1MHz

32MHz

÷ 32

Our Approach: Phase Realigned PLL

Conventional integer-N PLL except the VCOphase is realigned periodically to a bufferedreference edge

Divideby M

CtrlLogic

Ref OutPFDCHP

LoopFilter

Oscillators Accumulate Phase Errors

• Circuit noise ⇒ phase error in oscillators• Phase error is accumulated in oscillators†

⇒ Oscillator “remembers” previous phase errors ⇒ Oscillator acts as a phase error integrator ⇒ high phase noise in PLL passband† [G.Chien et al., ISSCC 2000]

OutputConventionalring oscillator

Output

Oscillators Accumulate Phase Errors

OutputConventionalring oscillator

Output

f f

cycle-cyclefluctuation

phasenoise

PSD PSD

Realignment Blocks Noise Memory

Periodically realigning the oscillator to a“clean” edge suppresses noise accumulation

Tref Tref

"clean" edgeen_rlgn

"clean" edgeen_rlgn

Reference

Ring oscillatorwith realignment Output

Output

Realignment Blocks Noise Memory

Tref Tref

"clean" edgeen_rlgn

"clean" edgeen_rlgn

Reference

Ring oscillatorwith realignment Output

Output

f f

cycle-cyclefluctuation

phasenoise

PSD PSDFref

Realigned VCO Prototype

• 7-stage ring VCO:4 stages, variable delay → frequency control3 stages, fixed delay → phase realignment

→ reduce disturbance

Vctrl

Ref +Ref -

Phase Realigning Details (1)

• VCO and buffered reference are in phasenominally; phase error is due to noise

• Phase realignment pulls the VCO edgetoward its “correct” value

Bufferedreference

VCO w/orealignmentRealigned

VCO

Buffered referenceReference

VCO output

Phase Realigning Details (2)

• VCO phase shifts almost instantly when realigned• VCO phase shifts almost linearly to phase error by

a factor of β. ( 0≤ β ≤ 1 )

Bufferedreference

VCO w/orealignmentRealigned

VCO

qe[n]

qshift[n] = - b qe[n]

Known Model for Conventional PLL

Kchp= Charge pump gainKvco=VCO gainHlp (s) = Loop filter transfer functionM = Divider ratio

qref(s) Kvco/s qout(s)

qvco(s)

Kchp Hlp (s)

÷ M

Kvco/s

Modified Model for Realigned PLL

Realignment ⇒ two new blocks: Hup (s) : up-conversion of reference noise

Hrl (s) : transfer function of realignment

qref(s) qout(s)

qvco(s)

Kchp

Hup (s)

Hlp (s)

÷ M

Hrl (s) Kvco/s Kvco/s

VCO Phase Noise Transfer Function

⇒ Realignment widens the noise stopband

103 104 105-60

-50

-40

-30

-20

-10

0

10

frequency (Hz)

dB

conventional PLLrealigned PLL

Loop Transfer Function

⇒ Realignment increases the phase margin

103 104 105

-150

-100

-50

pm = 55.3

pm = 119.0

degr

ee

Loop transfer function phase

103 104 105-50

0

50

100

frequency (Hz)

dB

Loop transfer function magnitude squared

conventional PLLrealigned PLL

Measurement Versus Theory

fref = 480 kHz, PLL bandwidth = 25 kHz

103 104 105 106-125

-120

-115

-110

-105

-100

-95

-90

-85

offset frequency from carrier (Hz)

pha

se n

oise

(dBc

/Hz)

Realignment disabled (measured) Realignment disabled (calculated)Realignment enabled (measured) Realignment enabled (calculated)

10dB

Reference Spur Issue

• 2 reference signal paths; 2 phase comparisons• Delay mismatch ⇒ more reference spur power• Realignment disabled: -78 dBc spur• Realignment enabled: -34 dBc spur

Divideby M

CtrlLogic

Ref OutPFDCHP

LoopFilter

Phase comparison

Reference Spur Reduction

• Variable delay ⇒ compensate for mismatch• Manual calibration ⇒ -71 dBc spur• Auto-calibration loop feasible

Divideby M

CtrlLogic

Ref OutPFDCHP

LoopFilter

Voltage Controlled Delay Cell

Performance Summary

8.3 dB w/ 25 kHz PLL bandwidth5.3 dB w/ 50 kHz PLL bandwidth

Reduction of noise powerfrom 1 kHz - 50 kHz

-92.5 dBc/Hz (realignment disabled)-102.5 dBc/Hz (realignment enabled)

Spot noise @ 20 kHzOffset

0.22 mm2. Conventional PLL: 73%Realignment circuitry: 27%Realigned PLL core area

1.8 mm2Die size

6.8mW (no observable differencewhen realignment enabled)Total power consumption

2.7-3.3V (measurements at 3V)Supply voltage

0.35 µm BiCMOS SOI(with only CMOS components used)Technology

Die PhotoBias CHP

VCO

Realigning Buffer

Xtal Osc

Divider

Summary

• A new VCO phase realignment technique hasbeen presented and shown to significantlyreduce phase noise in an integer-N PLL

• A theoretical model has been developed thatclosely supports the measured results