a multi-level optimizer for burst mode …nowick/asynctools/mlo-v0.9-tutorial.pdfmlo: a multi-level...
TRANSCRIPT
MLO
:A
Mul
ti-Le
vel O
ptim
izer
For
Bur
st M
ode
Asy
nchr
onou
s C
ontr
olle
rs
Wal
ter D
earin
g
Ste
ven
Now
ick
Com
pute
r Sci
ence
Dep
artm
ent
Col
umbi
a U
nive
rsity
This
wor
k w
as s
uppo
rted
by N
SF
ITR
Aw
ard
No.
NS
F-C
CR
-008
6036
and
by a
n In
itiat
ives
in S
cien
ce a
nd E
ngin
eerin
g (IS
E) g
rant
from
Col
umbi
a U
nive
rsity
(fro
m th
e O
ffice
of t
he E
xecu
tive
Vic
e P
resi
dent
for R
esea
rch)
2
MLO
: Acc
ess
Info
rmat
ion
!A
cces
sibl
e on
the
web
from
:
!In
itial
Rel
ease
!O
ne v
ersi
on �
for L
inux
Dis
tribu
tions
!In
clud
es
!C
ompl
ete
Tuto
rial
!D
ocum
enta
tion
!Ex
ampl
es
!To
ol re
quire
s P
ytho
n in
terp
rete
r to
run:
!C
onsu
lt R
EA
DM
E fo
r MLO
inst
alla
tion
info
rmat
ion
http
://w
ww
1.cs
.col
umbi
a.ed
u/~n
owic
k/as
ynct
ools
http
://w
ww
.pyt
hon.
org/
dow
nloa
d/
3
Out
line
!In
trodu
ctio
n to
MLO
(Mul
ti-Le
vel O
ptim
izer
)
!O
verv
iew
of f
eatu
res
!E
xam
ple
of fe
atur
es
!E
xam
ple
of g
ate
netw
orks
pro
duce
d
!B
uilt-
in v
erifi
er
!B
rief t
utor
ial
4
Intro
duct
ion
to M
LO
!In
trod
uctio
n to
MLO
(Mul
ti-Le
vel O
ptim
izer
)
!O
verv
iew
of f
eatu
res
!E
xam
ple
of fe
atur
es
!E
xam
ple
of g
ate
netw
orks
pro
duce
d
!B
uilt-
in v
erifi
er
!B
rief t
utor
ial
5
Intro
duct
ion
to M
LO!
MLO
is a
n in
tegr
ated
pos
t-pro
cess
ing
(i.e.
bac
kend
) too
l for
Min
imal
ist.
!Ta
rget
ed to
mul
ti-le
vel l
ogic
.
!In
con
trast
, Min
imal
ist c
urre
ntly
is ta
rget
ed to
two-
leve
l log
ic.
!D
esig
ned
to w
ork
on c
ombi
natio
nalh
azar
d-fr
ee lo
gic
for B
urst
Mod
e
cont
rolle
rs.
!U
ses
�haz
ard-
non-
incr
easi
ng�t
rans
form
s.
!O
utpu
t of M
LO is
Ver
ilog.
!M
LO is
a s
tand
alon
e to
ol ru
nnin
g fro
m th
e Li
nux
shel
l out
side
of
Min
imal
ist.
6
Intro
duct
ion
to M
LO
Mul
ti-le
vel t
ool f
low
BM
SPE
C (*
.bm
s)
MIN
IMAL
IST
PLA
file
(*.s
ol)
Tran
sitio
n fil
e(*
.pla
)
Mul
ti-Le
vel O
ptim
izer
Veril
ogfil
e(*
-ML.
v)
Two-
Leve
l
Mul
ti-Le
vel
New
7
Ove
rvie
ws
of fe
atur
es
!In
trodu
ctio
n to
MLO
(Mul
ti-Le
vel O
ptim
izer
)
!O
verv
iew
of f
eatu
res
!E
xam
ple
of fe
atur
es
!E
xam
ple
of g
ate
netw
orks
pro
duce
d
!B
uilt-
in v
erifi
er
!B
rief t
utor
ial
8
Feat
ure
Set
�O
verv
iew
MLO
has
man
y fe
atur
es w
hich
are
orth
ogon
al a
nd c
an
be u
sed
toge
ther
.
1.G
ate
fan-
in li
mita
tion
2.N
egat
ive-
logi
c
3.C
ritic
al E
vent
Opt
imiz
er (C
EO)
!Tw
o m
odes
a)A
utom
ated
b)U
ser-
spec
ified
9
Feat
ure
Set
�G
oal o
f CE
O
Goa
l of C
EO
is to
redu
ce th
e cr
itica
l pat
hof
crit
ical
eve
nts.
!C
ritic
al e
vent
sar
e de
fined
as
a tra
nsiti
on o
f a p
rimar
y
outp
ut in
resp
onse
to a
n in
put t
rans
ition
!D
one
by m
ovin
g cr
itica
l inp
uts
clos
er to
the
prim
ary
outp
ut.
!In
tent
ion
is fo
r crit
ical
inpu
ts to
trav
el th
roug
h th
e ci
rcui
t
as fa
st a
pos
sibl
e.
10
Feat
ure
Set
�C
EO M
ode
1 -
Aut
omat
ed M
ode
CE
O d
efau
lts to
aut
omat
ed m
ode
if no
use
r inp
ut s
peci
fied.
!To
ol a
utom
atic
ally
opt
imiz
es li
kely
crit
ical
pat
hs.
!Fo
cuse
s op
timiz
atio
ns o
n pr
imar
y in
put-t
o-ou
tput
path
sin
volv
ed in
dyn
amic
tran
sitio
ns.
!(i.
e. 0"
1 / 1
"0)
11
Feat
ure
Set
�C
EO M
ode
2 -
Use
r-Sp
ecifi
ed C
ritic
al E
vent
s
!U
ser m
ay k
now
whi
ch p
rimar
y in
put(s
) are
impo
rtant
to c
ritic
al p
rimar
y ou
tput
.
!D
one
by d
efin
ing
a cr
itica
l tra
nsiti
on&
inpu
t/out
put
pair
at th
e B
urst
-Mod
e sp
ec le
vel.
!Fo
r par
ticul
ar o
utpu
ts s
peci
fied
durin
g tra
nsiti
on, u
ser
over
rides
auto
mat
ed m
ode.
!C
onsi
der t
he s
ituat
ion
on th
e ne
xt s
lide
whe
re u
ser s
peci
fies
inpu
t & o
utpu
ts o
ff sp
ecifi
c ar
cs.
Use
r can
spe
cify
det
ails
for C
EO
to u
se.
12
Feat
ure
Set
�C
EO M
ode
2 -
Use
r-Sp
ecifi
ed C
ritic
al E
vent
s
Cas
e 1:
Non
col
oriz
ed
arc.
Use
r-Sp
ecifi
ed
noth
ing
is c
ritic
al. D
efau
lts
to a
utom
ated
mod
e fo
r ev
ery
outp
ut.
Cas
e 2:
Som
e ou
tput
s co
loriz
ed, s
ome
outp
uts
not.
Both
use
r-spe
cifie
d da
ta a
nd a
utom
ated
ap
proa
ches
are
use
d to
de
term
ine
criti
calit
y.
ITEv
entR
eqw
ill u
se u
ser-
spec
ified
dat
a to
de
term
ine
criti
calit
y.
Ctr
incR
eqw
ill d
efau
lt to
au
tom
ated
mod
e to
de
term
ine
criti
calit
y.
Cas
e 3:
Ever
y ou
tput
is
colo
rized
. Aut
omat
ed
appr
oach
is n
ever
used
. In
tITR
eq-i
s cr
itica
l with
re
spec
t to
Ctr
IncR
eq-,
whi
le IT
Even
t2Ti
cks-
is
NO
T cr
itica
l to
Ctr
IncR
eq-
.
Use
r-Sp
ecifi
ed C
ritic
al A
rcs
Hig
hlig
hted
inR
ed
IntIT
Req
-
ITEv
ent2
Tick
s-/
Ctr
IncR
eq-
50 1
23
4
IntIT
Req
+ /
ITEv
entR
eq+
IntIT
Req
+ /
ITEv
entR
eq+
ITEv
ent2
Tick
s-
Ctr
IncA
ck+
/ Ctr
IncR
eq-
IntIT
Req
-/
ITEv
entR
eq-
IntIT
Req
+ /
ITEv
entR
eq+
CtIn
cAck
-/
ITEv
entR
eq+
ITEv
ent2
Tick
s-/
Ctr
IncR
eq+
ITEv
entR
eq-
13
Exa
mpl
e of
feat
ures
!In
trodu
ctio
n to
MLO
(Mul
ti-Le
vel O
ptim
izer
)
!O
verv
iew
of f
eatu
res
!Ex
ampl
e of
feat
ures
!E
xam
ple
of g
ate
netw
orks
pro
duce
d
!B
uilt-
in v
erifi
er
!B
rief t
utor
ial
14
Feat
ure
Set
-In
itial
Tw
o-Le
vel
Impl
emen
tatio
n (b
efor
e ap
plyi
ng M
LO)
The
next
four
slid
es
pres
ent d
iffer
ent M
LO
outp
ut e
xam
ples
. Fo
r eac
h
exam
ple,
the
star
ting
circ
uit (
inpu
t to
MLO
) is
this
circ
uit
Two-
leve
l Str
uctu
re fr
om M
inim
alis
t Out
put
15
Feat
ure
Set
Exa
mpl
e 1
-G
ate
Fan-
in L
imita
tion
Res
ult o
f MLO
: M
ulti-
Leve
l circ
uit w
ith A
ND
gat
e fa
n-in
lim
it of
2
16
Feat
ure
Set
Exa
mpl
e 2
-N
egat
ive
Logi
c
Res
ult o
f MLO
: M
ulti-
Leve
l Circ
uit u
sing
MLO
Neg
ativ
e Lo
gic
This
mod
e ca
refu
lly o
ptim
izes
on
ly h
azar
d no
n-in
crea
sing
sa
fe tr
ansf
orm
atio
ns
(DeM
orga
n�s
Law
).
Opt
imiz
atio
ns a
re a
lso
incl
uded
to c
aref
ully
elim
inat
e ex
tra
inve
rter
s.
17
Feat
ure
Set
Exa
mpl
e 3
-C
EO Res
ult o
f MLO
: M
ulti-
Leve
l Circ
uit a
fter M
LOC
EOis
use
d
Gat
e D
ecom
pose
d.In
put
intit
req
is m
ore
criti
cal t
o
outp
ut it
even
treq
than
ctrin
cack
�and
y0�
criti
cal p
rimar
y in
put-
to-o
utpu
t pat
h
18
Feat
ure
Set
Exa
mpl
e 4
-C
ombi
ned
Res
ult o
f MLO
: Mul
ti-Le
vel C
ircui
t with
neg
ativ
e lo
gic,
AN
D g
ate
fan-
in li
mit
of 2
, an
d C
EO.
Gat
e fa
n-in
lim
it of
2
Neg
ativ
e Lo
gic
CEO
Opt
imiz
es C
ritic
al P
ath
19
Exa
mpl
e of
gat
e ne
twor
ks
prod
uced
!In
trodu
ctio
n to
MLO
(Mul
ti-Le
vel O
ptim
izer
)
!O
verv
iew
of f
eatu
res
!E
xam
ple
of fe
atur
es
!Ex
ampl
e of
gat
e ne
twor
ks p
rodu
ced
!B
uilt-
in v
erifi
er
!B
rief t
utor
ial
20
Gat
e D
ecom
posi
tion
!G
ates
can
be
deco
mpo
sed
in tw
o w
ays
!C
EO
�re
sulti
ng n
etw
ork
will
be
casc
aded
!Fa
n-in
lim
itatio
ns �
resu
lting
net
wor
k w
ill b
e ba
lanc
ed
!N
etw
ork
can
be a
mix
ture
of t
wo
met
hods
.
!C
onsi
der a
6 in
put A
ND
gat
e�.
21
Gat
e D
ecom
posi
tion
-C
asca
ded
Gat
e is
dec
ompo
sed
base
d on
prio
rity
diffe
renc
e of
inpu
ts
Onl
y us
ed fo
r CEO
Low
est I
nput
Prio
rity
H
ighe
st In
put P
riorit
y
(s
tate
var
iabl
es o
nly)
22
Gat
e D
ecom
posi
tion
�B
alan
ced
Gat
e is
dec
ompo
sed
stric
tly b
ased
on
fan-
in li
mita
tion
Onl
y us
ed fo
rgat
efa
n-in
lim
itatio
n
All
Inpu
ts h
ave
the
sam
e pr
iorit
y
23
Gat
e D
ecom
posi
tion
�M
ixG
ate
is d
ecom
pose
d ba
sed
on b
oth
diffe
renc
e in
prio
rity
of in
puts
and
fan-
in li
mits
Com
bina
tion
ofga
tefa
n-in
lim
itatio
n an
dC
EO
Low
Prio
rity
M
ediu
m P
riorit
y
Hig
h Pr
iorit
y
24
Brie
f tut
oria
l
!In
trodu
ctio
n to
MLO
(Mul
ti-Le
vel O
ptim
izer
)
!O
verv
iew
of f
eatu
res
!E
xam
ple
of fe
atur
es
!E
xam
ple
of g
ate
netw
orks
pro
duce
d
!B
uilt-
in v
erifi
er
!B
rief t
utor
ial
25
Bui
lt-in
Ver
ifier
!A
verif
ier i
s bu
ilt in
to M
LO.
!Ve
rifie
s M
LO o
utpu
t is
func
tiona
lly c
orre
ctan
d ha
zard
free
!C
ompa
res
two-
leve
l stru
ctur
e (M
inim
alis
t out
put)
to m
ulti-
leve
l
stru
ctur
e (M
LO o
utpu
t).
!Ve
rifie
s sp
ecifi
c pr
oper
ties
hold
for e
ach
gate
net
wor
k in
mul
ti-le
vel
stru
ctur
e.
!M
ust b
e ex
plic
itly
set u
sing
com
man
d lin
e fla
g (n
ot ru
n by
def
ault)
26
Brie
f tut
oria
l
!In
trodu
ctio
n to
MLO
(Mul
ti-Le
vel O
ptim
izer
)
!O
verv
iew
of f
eatu
res
!E
xam
ple
of fe
atur
es
!E
xam
ple
of g
ate
netw
orks
pro
duce
d
!B
uilt-
in v
erifi
er
!B
rief t
utor
ial
27
Tuto
rial
!Th
e sp
ec fi
le h
p-ir.
bms
will
be u
sed
durin
g th
is tu
toria
l.
This
can
be
foun
d in
the
exam
ples
fold
er.
!E
very
com
man
d us
ed in
the
tuto
rial i
s al
so d
escr
ibed
in
the
tool
hel
p m
enu.
!To
dis
play
gen
eral
hel
p m
enu
>MLO.py--help
!To
dis
play
use
r-sp
ecifi
ed c
ritic
al e
vent
hel
p m
enu
>MLO.py--more_help
28
Tuto
rial -
Setu
pC
reat
e th
e fil
es n
eede
d fo
r MLO
to p
roce
ss
Step
1 �
Cre
ate
wor
king
dire
ctor
y> mkdir
MLO_tutorial
Step
2 �
Cop
y sp
ec fi
le> cp examples/hp-ir.bms
MLO_tutorial/
Step
3 �
Ente
r Dire
ctor
y> cd
MLO_tutorial
Step
4 �
Cre
ate
.pla
& .s
ol fi
les
>minimalist-speed hp-ir.bms
single-output fedback
Step
5 �
Verif
y fil
es c
reat
ed> Verify hp_IR-Fs.sol
and hp_IR-
Fs.pla
has been created
Two-
Leve
lcirc
uit f
rom
Min
imal
ist
Ass
umes
Min
imal
ist i
s lo
aded
and
path
s ar
e se
t cor
rect
ly!
29
Tuto
rial �
Gat
e Fa
n-In
Lim
itatio
nIm
plem
ent c
ircui
t with
gat
e fa
n-in
lim
it of
2 fo
r AN
D g
ates
. Th
is c
an b
edo
ne u
sing
two
diffe
rent
met
hods
(res
ults
will
be th
e sa
me)
Step
1 �
Run
MLO
> MLO.py
–A 2 –d hp_IR-Fs.sol
Step
2 �
View
Res
ults
> less hp_IR-Fs-ML.v
Step
3 �
Verif
y R
esul
ts> Compare output with circuit on
next page
Step
1 �
Run
MLO
> MLO.py
–M 2 –d hp_IR-Fs.sol
Step
2 �
View
Res
ults
> less hp_IR-Fs-ML.v
Step
3 �
Verif
y R
esul
ts> Compare output with circuit on
next page
Met
hod
1: I
ndep
ende
ntly
M
etho
d 2:
Glo
bally
S
peci
fy fa
n-in
lim
it fo
r AN
D g
ates
onl
y
S
peci
fy fa
n-in
lim
it fo
r eve
ry g
ate
type
30
Tuto
rial �
Gat
e Fa
n-In
Lim
itatio
nmodule hp_IR_Fs(intitreq, itevent2ticks, ctrincack, iteventreq, ctrincreq);
input intitreq, itevent2ticks, ctrincack;
output iteventreq, ctrincreq;
wire neg_ctrincack, neg_ctrincreq_i, neg_itevent2ticks, ctrincreq_i, ctrincreq, _i1;
wire _i2, _i3;
// Wires needed for multi-level
wire _i4, _i5, _i6;
// Feedback variables
assign ctrincreq_i= ctrincreq;
// Negative input literals
not (neg_ctrincack, ctrincack);
not (neg_ctrincreq_i, ctrincreq_i);
not (neg_itevent2ticks, itevent2ticks);
// First plane of logic
// --Network implementing gate _i3 --
and (_i3, _i4, neg_ctrincack);
and (_i4, intitreq, ctrincreq_i);
// --Network implementing gate _i2 --
assign _i2 = itevent2ticks;
// --Network implementing gate _i1 --
and (_i1, _i5, _i6);
and (_i5, neg_ctrincack, neg_ctrinreq_i);
and (_i6, intitreq, neg_itevent2ticks);
// Second plane of logic
// --Network implementing gate CtrIncReq--
or (ctrincreq, _i3, _i2);
// --Network implementing gate ITEventReq --
assign iteventreq= _i1;
endmodule
MLO
Out
put:
2 A
ND
gat
es h
ave
been
dec
ompo
sed
base
d on
fan-
in li
mit
of 2
.
31
Tuto
rial �
Neg
ativ
e Lo
gic
Impl
emen
t circ
uit u
sing
neg
ativ
e lo
gic.
Step
1 �
Run
MLO
> MLO.py
–n –d hp_IR-Fs.sol
Step
2 �
View
Res
ults
> less hp_IR-Fs-ML.v
Step
3 �
Verif
y R
esul
ts> Compare output with
circuit on next page
MLO
Res
ult:
Mul
ti-Le
vel C
ircui
t usi
ng n
egat
ive
logi
c on
ly
32
Tuto
rial �
Neg
ativ
e Lo
gic
module hp_IR_Fs(intitreq, itevent2ticks, ctrincack, iteventreq, ctrincreq);
input intitreq, itevent2ticks, ctrincack;
output iteventreq, ctrincreq;
wire neg__i2, neg_ctrincack, neg_intitreq, ctrincreq_i, ctrincreq, _i1;
wire _i2, _i3;
// Wires needed for multi-level
wire neg__i3;
// Feedback variables
assign ctrincreq_i= ctrincreq;
// Negative input literals
not (neg__i2, _i2);
not (neg_ctrincack, ctrincack);
not (neg_intitreq, intitreq);
// First plane of logic
// --Network implementing gate neg__i3 --
nand(neg__i3, neg_ctrincack, intitreq, ctrincreq_i);
// --Network implementing gate _i2 --
assign _i2 = itevent2ticks;
// --Network implementing gate _i1 --
nor (_i1, ctrincack, ctrincreq_i, neg_intitreq, itevent2ticks);
// Second plane of logic
// --Network implementing gate CtrIncReq--
nand(ctrincreq, neg__i3, neg__i2);
// --Network implementing gate ITEventReq --
assign iteventreq= _i1;
endmodule
MLO
Out
put:
Onl
y N
OT/
NO
R/N
AN
D g
ates
use
d.
33
Tuto
rial �
CE
O C
ritic
al E
vent
O
ptim
izer
(Aut
omat
ed M
ode)
Run
MLO
usi
ng d
efau
lts (C
EO o
n, n
o ga
te fa
n-in
lim
its, a
nd n
one
gativ
e lo
gic)
.
Step
1 �
Run
MLO
> MLO.py
hp_IR-Fs.sol
Step
2 �
View
Res
ults
> less hp_IR-Fs-ML.v
Step
3 �
Verif
y R
esul
ts> Compare output with
circuit on next page
Mul
ti-Le
vel c
ircui
t afte
r CEO
is u
sed
No
switc
h se
lect
ed: d
efau
lt is
CE
O in
aut
o m
ode
criti
cal p
rimar
y
inpu
t-to-
outp
ut p
ath
34
Tuto
rial �
CE
Omodule hp_IR_Fs(intitreq, itevent2ticks, ctrincack, iteventreq, ctrincreq);
input intitreq, itevent2ticks, ctrincack;
output iteventreq, ctrincreq;
wire neg_ctrincack, neg_itevent2ticks, neg_ctrincreq_i, ctrincreq_i, ctrincreq, _i1;
wire _i2, _i3;
// Wires needed for multi-level
wire _i4;
// Feedback variables
assign ctrincreq_i= ctrincreq;
// Negative input literals
not (neg_ctrincack, ctrincack);
not (neg_itevent2ticks, itevent2ticks);
not (neg_ctrincreq_i, ctrincreq_i);
// First plane of logic
// --Network implementing gate _i3 --
and (_i3, neg_ctrincack, intitreq, ctrincreq_i);
// --Network implementing gate _i2 --
assign _i2 = itevent2ticks;
// --Network implementing gate _i1 --
and (_i1, intitreq, _i4);
and (_i4, neg_itevent2ticks, neg_ctrincack, neg_ctrincreq_i);
// Second plane of logic
// --Network implementing gate CtrIncReq--
or (ctrincreq, _i2, _i3);
// --Network implementing gate ITEventReq --
assign iteventreq= _i1;
endmodule
MLO
Out
put:
Gat
e D
ecom
pose
d. I
nput
intit
req
is
mor
e cr
itica
l to
outp
ut it
even
treq
than
ne
g_ct
rinca
ckan
d ne
g_ct
rincr
eq_i
35
Tuto
rial �
Feat
ures
Mix
Feat
ures
can
be
mix
ed a
nd m
atch
ed.
This
exa
mpl
e do
es n
ot u
tiliz
e C
EO, b
ut it
doe
s ta
rget
neg
ativ
e lo
gic
circ
uit a
nd li
mits
fan-
in to
2.
Step
1 �
Run
MLO
> MLO.py
–d –n –R 2 –N 2 hp_IR-Fs.sol
Step
2 �
View
Res
ults
> less hp_IR-Fs-ML.v
Step
3 �
Verif
y R
esul
ts> Compare output with circuit on next
page
36
Tuto
rial �
Feat
ures
Mix
module hp_IR_Fs(intitreq, itevent2ticks, ctrincack, iteventreq, ctrincreq);
input intitreq, itevent2ticks, ctrincack;
output iteventreq, ctrincreq;
wire neg__i2, neg_ctrincack, neg_intitreq, neg_ctrincreq_i, neg_itevent2ticks, ctrincreq_i;
wire ctrincreq, _i1, _i2, _i3;
// Wires needed for multi-level
wire _i4, _i5, _i6, neg__i3;
// Feedback variables
assign ctrincreq_i= ctrincreq;
// Negative input literals
not (neg__i2, _i2);
not (neg_ctrincack, ctrincack);
not (neg_intitreq, intitreq);
not (neg_ctrincreq_i, ctrincreq_i);
not (neg_itevent2ticks, itevent2ticks);
// First plane of logic
// --Network implementing gate neg__i3 --
nand(neg__i3, _i4, neg_ctrincack);
nor (_i4, neg_intitreq, neg_ctrincreq_i);
// --Network implementing gate _i2 --
assign _i2 = itevent2ticks;
// --Network implementing gate _i1 --
nor (_i1, _i5, _i6);
nand(_i5, neg_ctrincack, neg_ctrincreq_i);
nand(_i6, intitreq, neg_itevent2ticks);
// Second plane of logic
// --Network implementing gate CtrIncReq--
nand(ctrincreq, neg__i3, neg__i2);
// --Network implementing gate ITEventReq --
assign iteventreq= _i1;
endmodule
MLO
Out
put:
Onl
y N
OT/
NO
R/N
AN
D g
ates
us
ed a
nd fa
n-in
lim
ited
to 2
37
Tuto
rial �
Use
r-S
peci
fied
Crit
ical
E
vent
s -O
verv
iew
!M
LO o
rigin
ally
nee
ded
only
two
files
to ru
n (*
.pla
and
*.so
l)
!To
util
ize
Use
r-S
peci
fied
Crit
ical
Eve
nts,
MLO
now
nee
ds tw
o
addi
tiona
l file
s:
1.st
ate_
info
.txt
2.*.
bms
spec
-file
38
Tuto
rial �
Use
r-S
peci
fied
Crit
ical
E
vent
s �
stat
e_in
fo.tx
tS
tate
min
imiz
atio
n da
ta is
nee
ded
to u
tiliz
e U
ser-
Spe
cifie
d C
ritic
al E
vent
s
!Th
is in
form
atio
n is
onl
y fo
und
on s
tand
ard
outp
ut d
urin
g ru
n of
Min
imal
ist.
!Th
eref
ore
new
pro
gram
cap
utur
e_m
in_d
ata
is n
eede
d to
redi
rect
Min
imal
ist
outp
ut to
sta
te_i
nfo.
txt
!R
uns
from
linu
xsh
ell
!W
rapp
er a
roun
d M
inim
alis
t cal
l
!Im
porta
nt to
not
e th
at c
aptu
re_m
in_d
ata
only
wor
ks w
ith s
ingl
e-ru
n
Min
imal
ist s
crip
ts.
In o
ther
wor
ds, i
t doe
sn�t
wor
k fo
r scr
ipt s
uite
s
39
Tuto
rial �
Use
r-S
peci
fied
Crit
ical
E
vent
s �
stat
e_in
fo.tx
tS
ynta
x R
ules
:
1.ca
putu
re_m
in_d
ata
sim
ply
prec
edes
Min
imal
ist c
all.
�Fo
r exa
mpl
e, if
use
r wan
ts to
cap
ture
dat
a of
min
imal
ist-a
rea
scrip
t usi
ng m
ulti-
outp
ut ru
n ty
pe, t
he s
ynta
x w
ould
be
> capture_min_dataminimalist-area hp-ir.bmsmulti-output
2.Sy
ntax
for M
inim
alis
t com
man
d lin
e op
tions
are
sam
e as
if
capt
ure_
min
_dat
aw
as n
otbe
ing
used
.
40
Tuto
rial �
Use
r-S
peci
fied
Crit
ical
E
vent
s �
*.bm
ssp
ec-fi
le
!C
ritic
al e
vent
s w
ill b
e sp
ecifi
ed b
y pr
ovid
ing
criti
cal i
nput
/out
put p
airs
for
spec
ified
tran
sitio
ns in
the
burs
t-mod
e sp
ecifi
catio
n.
!If
all i
nput
s ar
e cr
itica
l for
out
put d
urin
g tra
nsiti
on, w
ildca
rd(�
*�) c
an b
e
used
.
!N
o bl
ank
lines
can
sur
roun
d an
y in
serte
d us
er-s
peci
fied
criti
cal
com
men
ts(�
; CR
ITIC
AL�
stat
emen
ts) i
n th
e *.
bms
file.
!C
omm
ent m
ust i
mm
edia
tely
pre
cede
the
trans
ition
that
it is
des
crib
ing.
Burs
t Mod
e S
pec
file
has
to b
e ed
ited
to s
peci
fy c
ritic
al e
vent
s.
41
Tuto
rial �
Use
r-Spe
cifie
d C
ritic
al
Eve
nts
-*.b
ms
spec
-file
Syn
tax
Rul
es (r
edco
mm
ent):
1.To
spe
cify
that
the
inpu
t CtrI
ncA
ck+
is c
ritic
al to
CtrI
ncR
eq-d
urin
g tra
nsiti
on fr
om
curre
nt s
tate
3 to
nex
t sta
te 4
(not
e th
at th
is is
als
o sa
ying
that
ITev
ent2
Tick
s is
NO
Tcr
itica
l): ;CRITICAL: CtrIncAck+/CtrIncReq-
3 4 ITevent2Ticks-CtrIncAck+ | CtrIncReq-
2.To
spe
cify
all
inpu
ts a
re c
ritic
al to
CtrI
ncR
eq-f
rom
cur
rent
sta
te 3
to n
ext s
tate
5:
;CRITICAL: */CtrIncReq-
3 5 ITevent2Ticks-CtrIncAck+ | CtrIncReq-
3.A
noth
er w
ay to
spe
cify
all
inpu
ts a
re c
ritic
al (s
ame
as R
ule
#2)t
o C
trInc
Req
-dur
ing
a tra
nsiti
on fr
om c
urre
nt s
tate
3 to
nex
t sta
te 5
:;CRITICAL: ITevent2Ticks-/CtrIncReq-, CtrIncAck+/CtrIncReq-
3 5 ITevent2Ticks-CtrIncAck+ | CtrIncReq-
4.If
no in
put/o
utpu
ts a
re m
arke
d cr
itica
l, au
tom
ated
CE
O is
use
d. A
utom
ated
CE
O is
us
ed to
rate
crit
ical
ity o
f ITe
vent
2Tic
ks a
nd C
trInc
Act
with
resp
ect t
o C
trInc
Req
:3 5 ITevent2Ticks-CtrIncAck+ | CtrIncReq-
42
Tuto
rial �
Use
r-Spe
cifie
d C
ritic
al
Eve
nts
Ther
efor
e, th
ere
are
thre
e st
eps
to u
se U
ser-
Spec
ified
Crit
ical
Eve
nts
1.C
aptu
re o
utpu
t of M
inim
alis
t.
!R
un M
inim
alis
t with
cap
ture
_min
_dat
ato
cre
ate
stat
e_in
fo.tx
t
2.Sp
ecify
crit
ical
eve
nts
in s
pec
file
(*.b
ms)
.
!Ad
d ;CRITICAL...
stat
emen
ts
3.R
un M
LOw
ith p
rope
r com
man
d lin
e op
tions
.
!M
ust u
se �
U [*
.bm
ssp
ec-fi
le] o
ptio
n.
!O
nly
have
to s
peci
fy *
.bm
san
d *.s
ol fi
le, M
LO a
ssum
es
stat
e_in
fo.tx
t and
*.pl
aar
e in
sam
e di
rect
ory
as *.
sol.
43
Tuto
rial �
Use
r-Spe
cifie
d C
ritic
al
Even
ts: C
ompl
ete
Run
Spe
cify
Use
r-Spe
cifie
d C
ritic
al E
vent
sSt
ep 1
�C
aptu
re M
inim
alis
t Out
put
> capture_min_data
minimalist-speed hp-ir.bms
single-output
Step
2 �
Edit
spec
file
>emacs
(or vi) hp-ir.bms
Step
3 �
Add
crit
ical
eve
nts
to s
pec
file
(def
ault
auto
mod
e w
ill b
e us
ed fo
r oth
er e
vent
s)
> add line in red to file:
;CRITICAL: CtrIncAck+/CtrIncReq-
34
ITEvent2Ticks-
CtrIncAck+
| CtrIncReq-
Step
4 �
Run
MLO
> MLO.py
–U hp-ir.bms
hp_IR-s.sol
Step
5 �
View
Res
ults
> less hp_IR-s-ML.v
Step
6 �
Verif
y R
esul
ts> Compare output with circuit on next page
44
Tuto
rial �
Use
r Def
ined
Crit
ical
E
vent
smodule hp_IR_s(intitreq, itevent2ticks, ctrincack, iteventreq, ctrincreq);
input intitreq, itevent2ticks, ctrincack;
output iteventreq, ctrincreq;
wire neg_ctrincack, neg_itevent2ticks, neg_y0_i, y0_i, y0, _i1;
wire _i2, _i3, _i4, _i5;
// Wires needed for multi-level
wire _i6, _i7;
// Feedback variables
assign y0_i = y0;
// Negative input literals
not (neg_ctrincack, ctrincack);
not (neg_itevent2ticks, itevent2ticks);
not (neg_y0_i, y0_i);
// First plane of logic
// --Network implementing gate _i5 --
and (_i5, neg_ctrincack, _i6);
and (_i6, intitreq, y0_i);
// --Network implementing gate _i4 --
assign _i4 = itevent2ticks;
// --Network implementing gate _i3 --
and (_i3, intitreq, _i7);
and (_i7, neg_itevent2ticks, neg_ctrincack, neg_y0_i);
// --Network implementing gate _i2 --
and (_i2, neg_ctrincack, intitreq, y0_i);
// --Network implementing gate _i1 --
assign _i1 = itevent2ticks;
// Second plane of logic
// --Network implementing gate CtrIncReq--
or (ctrincreq, _i5, _i4);
// --Network implementing gate y0 --
or (y0, _i2, _i1);
// --Network implementing gate ITEventReq--
assign iteventreq= _i3;
endmodule
Gat
e de
com
pose
d us
ing
fact
that
us
er-s
peci
fied
neg_
ctrin
cack
is
criti
cal t
o ct
rincr
eq
Not
ice
that
Aut
omat
ed C
EO
is
still
used
on
outp
uts
not
spec
ified
by
user
45
Tuto
rial �
Ver
ifier
Run
MLO
usi
ng w
ith C
EO a
nd u
se th
e ve
rifie
r to
ensu
re o
utpu
t is
func
tiona
lly c
orre
ct a
nd h
azar
d fre
e
Step
1 �
Run
MLO
> MLO.py
-V hp_IR-s.sol
Step
2 �
Verif
y M
LO o
utpu
t pas
ses
verif
ier (
verif
y su
cces
s m
essa
ge is
prin
ted)
> check standard output
-----------------------------------
Verification Results
Output has been verified -
Everything OK.
----------------------------------
If ou
tput
pas
ses
built
-in
verif
ier,
a su
cces
s m
essa
ge w
ill be
prin
ted
to s
tand
ard
outp
ut.
46
Rec
ap
!M
LO u
ses
Min
imal
ist t
wo-
leve
l log
ic o
utpu
t and
prod
uces
an
optim
ized
mul
ti-le
vel c
ircui
t
spec
ified
in V
erilo
g.
!To
ol h
as m
ultip
le fe
atur
es in
clud
ing
nega
tive
logi
c im
plem
enta
tions
, crit
ical
-eve
nt o
ptim
izer
,
and
gate
fan-
in li
mita
tions
.