A LOAD-BALANCED PIPELINE ARCHITECTURE FOR IP ROUTE LOOKUP

Author : Shengqing Hu, Yi Wu and Ge Nong

Publisher : 2013 IEEE

Presenter : Pei-Hua Huang

Date : 2014/01/08

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INTRODUCTION• In a pipeline routing architecture, nodes of a routing table

transformed into a prefix trie are distributed to multiple memory blocks of a pipeline level by level

• The majority of entries in an IPv4 routing table are occupied by 24-bit prefixes typically contained by the prefix nodes of a same level, leading to unbalanced storage demands among memory blocks

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INTRODUCTION• Random duplicate allocation (RDA) : each subtrie has two

copies randomly rooted in two different memory blocks• A packet can execute its route lookup if any copy of the

subtrie is available• Access conflicts may occur when multiple packets try to

access a same memory block simultaneously

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Routing Architecture• A demultiplexer (DEMUX):

dispatches arriving packets to each input buffer

• N input buffers (IBs): each input buffer maintains N virtual output queues (VOQs) for queuing packets according to their root blocks

• A rotator• N output buffers (OBs):

Each output buffer maintains a FIFO queue

• N memory blocks (MBs):Each memory block i is connected with OBi and its circular upstream block i -1

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Queuing Model• Time is split into discrete fixed-size time slots, each time

slot is divided into N cycles• At the beginning of each cycle, at most one packet can

arrive at the router• At the middle of each time slot, for each IBi connected to

OBj , the rotator forwards the head-of-line (HOL) packet of IQi, j from IBi to Obj

• The rotator rotates once at the end of each time slot• Each memory block can be accessed once per time slot

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Queuing Model

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Prefix Distribution

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Access Control• A packet will experience a two-phase search procedure

• a quick lookup in the index table• a deep search in its active trie

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SIMULATION• Each result is the average of samples from 10 runs and

each run consists of 100,000 packet arrivals randomly chosen from 219581 entries of the AS4637 BGP routing table

• Three different trie-based routing algorithms, i.e. BT(binary trie), PT(prefix tree) and FST(fixed-stride trie), are pipelined in this experiment

• Parameters• S: the average number of searching steps• W: the normalized workload on a memory block in each time slot,

which is defined as W = Sλ, where λ ∈ [0, 1/S).• D: the average number of time slots for a packet to finish its route

lookup• LO: the longest output queue length in each OB

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Results

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CONCLUSION• Can be generally applied to pipeline memory accesses of

any trie-based routing algorithm• Achieve a saturated throughput of nearly 100% for traffic

with uniform distributed destinations