A Knowledge-Based LogicDesign System

Takao Uehara, Fujitsu Laboratories Ltd.

I n developing Fujitsu's computer-aided logic design sys-tem, we began by using the digital system design lan-

guage (DDL)-a register-transfer-level computer hardwaredescription language-to create a variety of support soft-ware, including a simulator, verifier, and translator. ' TheDDL simulator was used to design such large-scale com-puters as theFACOM M380 and M382. The results were sosuccessful that the DDL simulator became an indispensablecomponent of Fujitsu's design automation system forcommercial computers. The verifier and translator wereused experimentally to design the adapter connecting theFACOM Alpha, a Lisp machine, and the FACOM M18011,a general-purpose machine.2 Verification of the register-transfer-level design and translation were successful, exceptthat the translator generated a redundant gate-level design.The experiment revealed that manually optimizing the

gate-level design introduces many errors. This findingmotivated us to develop better tools for the gate-leveldesign, including a symbolic simulator, debugger, and syn-thesizer. Symbolic manipulation and logical inference playimportant roles in these tools. The synthesizer is a typicalknowledge-based system.

System overview

Figure I is an outline of our computer-aided logic designsystem. The register-transfer-level design is described inDDL, and most design errors are found by the DDL simula-tor. The DDL verifier is used to prove assertions difficult tocheck exhaustively by the simulator. The DDL translatorgenerates a technology-independent functional design fromthe DDL description.

0740-7475/85/1000-0027$01.00O 1985 IEEE 27October 1985

The symbolic simulator checksfunctional or gate-level design. Thedebugger assists users in debuggingtheir designs. The synthesizer trans-forms the functional design into a

technology-dependent, gate-level de-sign. The gate-level logic simulator isthe most widely used tool for findingdesign errors.

DDL verifier. The basic configura-tion of the DDL verifier3 is shown inFigure 2. A hardware design descrip-tion in DDL and an assertion are inputto the verifier. The DDL description istransformed into cause-effect tablesby the DDL translator, and the asser-

tion is described in temporal logic. Theverifier assumes the assertion to befalse, and traces the cause-effect rela-tions to find feasible causes for thisassumption by backward reasoning. Ifno feasible causes exist, the assump-

tion is denied and the assertion isverified. Otherwise, it is shown whythe assertion is false.

Symbolic simulator. The symbolicsimulator4 handles both symbolic andlogical values. Logical values shouldbe used for the control part of a digitalsystem and symbolic values for thedata paths of the system. Figure 3shows an example of symbolic simula-tion. The value of the primary outputis CARI at time 26. Values of signals

Hlgure 2. Basic configuration of the DDL verifier.

Flgure 1. Outline of the computer-aided logic design system. Flgure 3. An example of symbolic simulation.

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are symbols or hexadecimal numbers.The symbolic simulator was imple-

mented in UtiLisp.5 Artificial in-telligence concepts such as frames anddemons are used to implement a hier-archical representation of a digitalsystem and event-driven simulation.The user can input a Lisp assertion intothe simulator as a demon to find an il-legal value. For example, exclusivenessof the set and reset signals into a flip-flop are monitored by a demon.

Debugger. Figure 4 shows the basicconfiguration of the debugger. If auser finds an unexpected result whileusing the symbolic simulator, he canask the debugger, "Why isn't this theexpected value?" The debugger ana-lyzes the simulation history and in-dicates probable design error loca-tions; analysis is based on backwardreasoning and is implemented in Pro-log/KR.6 An example is shown inFigure 5, where the user asks thedebugger why the value ofthe primaryoutput is not ADRI. The debugger in-dicates probable error locations in red.

Synthesizer

Figure 6 shows the number of errorsdetected during design of the FACOMAlpha adapter. Six errors were de-tected by the DDL simulator. Anothererror was revealed by the DDL veri-fier. After the errors were corrected,theDDL description was translated in-to tables representing the conditionalactions of each facility (terminals, reg-isters, and states). Figure 7 shows anexample of the translated results and acorresponding functional diagram.The gate-level design using standard

TTL ICs was done manually accord-ing to the tables generated by the DDLtranslator. The gate-level logic simu-lator detected 38 errors. (We did nothave the symbolic simulator or debug-ger at that time.) These errors wererelated to the gate-level design, not tothe register-transfer-level design.

Another 38 errors were found in thehardware. Two of them were register-transfer-level design errors and allothers were gate-level. Thus, automat-ic synthesis of a gate-level design from

Figure 4. Basic configuration of the debugger.

Figure 5. An example of debugging.

Figure 6. Errors made and errors detected.

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the register-transfer-level would elimi-nate 36 out of 38 errors. VLSI design-ers must be able to achieve this level ofreliability, because debugging hard-ware is very difficult. We developed asynthesizer for this reason.

Knowledge-based system. The pro-cess of synthesizing a logic circuit is notclear enough to enable establishing analgorithm. Design constraints andoptimization techniques depend heavi-ly on the target technology. We imple-mented the synthesizer as a knowl-edge-based system because it workswithout an established algorithm andis easy to modify according to the tar-get technology.

There are many tools and method-ologies for building knowledge-basedsystems. The synthesizer was imple-mented in a production system basedon the blackboard model.7 The pro-duction system's interpreter is writtenin UtiLisp. The frame developed forthe symbolic simulator is used forembedding functional diagrams andlogic diagrams. The basic configura-tion of the synthesizer is shown inFigure 8.

Expert knowledge. The first targettechnology was standard TTL ICs. Atechnology-independent functionaldiagram was input to the synthesizer.About 20 types ofmacro-components,

Figure 7. Translated result and functional diagram.

such as and-macro, or-macro, de-coder, multiplexer, and register areused for the functional design. For ex-ample, an and-macro with five inputsis used without checking whether thereis an and-gate with five inputs in the IClibrary. A variety of expert knowledgeis necessary to transform a functionaldiagram to a logic diagram using morethan 200 types of TTL ICs. Some ofthe necessary expert knowledge isshown in Figure 9. About 100 produc-tion rules derived through interviewswith expert designers have been builtinto the knowledge base.

Synthesis process. A part of the syn-thesizer implemented experimentallyin Prolog8 is presented here.And-macros (logical components

independent of the technology) can bemanipulated as follows:

Rule 1: If an inverter-macro is con-nected to the output of an and-macro,then replace the inverter-macro andthe and-macro with a nand-macro.Rule 2: If N, the number of inputs

to the and-macro, is equal to or lessthan M, the maximum number of in-puts to an and-gate in the IC menu,then use an and-gate with the mini-mum number of inputs equal to orgreater than N.Rule 3: IfNexceeds M, then replace

the and-macro with the following twoand-macros. The first and-macro hasM- 1 original inputs and an inputfrom the output of the second and-

Figure 8. Basic configuration of the synthesizer.

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Figure 9. An example of logic circuit synthesis knowledge.

Figure 10. Knowledge for manipulating and-macros.

macro. The second and-macro hasN-M+ I original inputs.To simplify the explanation, it is

assumed that there are only six ICs inthe menu, as shown in Table 1.The knowledge, represented in Pro-

log, for manipulating and-macros isshown in Figure 10 with illustrations.Knowledge for manipulating or-

macros, nand-macros, and inverter-

October 1985

Table 1.Six types of ICs.

Macro type Number ofinputs IC name

OR 2 SN7432NAND 2 SN7409N

3 SN74S11NAND 2 MB400

3 MB401Inverter 1 MB418

Figure 11. Examples of logic circuit synthesis (Prolog version).

macros was represented in a simnilarway. Metalevel knowledge to deter-mine the order in which these knowl-edge sources are applied is also writtenin Prolog. A diagram consisting ofand-macros and an or-macro is shownin Figure 1 Ia. The input is shown inFigure 1I b, and the output in FigureI Ic. The result is shown in Figure I Id.

The original version of this pro-gram9 was implemented in UtiLisp.The program has 30 knowledgesources for macro-expansion, optimi-zation, and control, as well as about100 rules. The invocation of knowl-edge sources is controlled by meta-rules in the knowledge sources. Thefunctional diagram is embedded in theframe. The interpreter of the produc-tion system synthesizes a logic dia-gram from a given functional diagramaccording to the rules in the knowledgebase. Only two seconds are requiredfor the M-380 to generate logic dia-grams containing 1000 gates, com-pared to one week for a human design-er. An example is shown in Figure 12,where 12b and 12c are logic diagrams

using TTL and CMOS, respectively.The synthesizer generated these logicdiagrams from the functional diagram12a.

A knowledge-based system is aA key technology for building ad-vanced CAD systems. Knowledge-based techniques make it easy to adapt

Figure 12a. Functional diagram (input) of logic circuit synthesis (Lisp version).

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Figure 12b. Synthesized logic diagram using 1TL ICs (one of four pages).

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Figure 12c. Synthesized logic diagram using CMOS cells (one of 10 pages).

a system to different technologies. Ourknowledge-based synthesizer gener-ated a logic diagram of almost as highquality as one designed by a human ex-pert. It took only one-half man-year todevelop the CMOS gate array version,compared to four man-years for theoriginal TTL IC version. In general,the synthesizer makes it easy to use thesame functional design for varioustechnologies.Numerous knowledge-based CAD

systems have been proposed. Most ofthem are still in their experimentalstages. General improvement of the Alsupport environment should makethem practical in the near future. E;

References

1. N. Kawato et al., "Design andVerification of Large Scale Computerby Using DDL," Proc. Design Auto-mation Conf., San Diego, Calif.,IEEE-CS, June 1979, pp. 360-366.

2. F. Maruyama et al., "A VerificationTechnique for Hardware Design,"Proc. Design Automation Conf., LasVegas, Nev., IEEE-CS, June 1982,pp. 832-841.

3. T. Uehara et al., "DDL Verifier andTemporal Logic," in ComputerHard-ware Description Languages andTheir Applications, Kaiserslautern,North-Holland, 1983, pp. 91-102.

4. T. Saito, T. Uehara, and N. Kawato,"A CAD System for Logic DesignBased on Frames and Demons,"Proc. Design Automation Conf.,Nashville, Tenn., IEEE-CS, June1981, pp. 451-456.

5. T. Chikayama, UtiLisp Manual, TheUniversity of Tokyo, 1981.

6. H. Nakashima, Prolog/KR User'sManual, The University of Tokyo,1981.

7. H.P. Nii and N. Aiello, "AGE: AKnowledge-based Program for Build-ing Knowledge-based Programs,"Proc. IJCAI, Tokyo, Japan, 1979,pp. 645.

8. T. Uehara and N. Kawato, "LogicCircuit Synthesis Using Prolog, " New

Generation Computing, Ohmsha Ltd.and Springer-Verlag, Vol. 1, No. 2,1983, pp. 187-193.

9. N. Kawato, T. Saito, and H.Sugimoto, "DDL/SX: A Rule-basedExpert System for Logic Circuit Syn-thesis," Proc. ISCAS, Kyoto, Japan,1985, pp. 885-888.

Takao Uehara is the manager of theComputer-based Systems Laboratory atFujitsu Laboratories Ltd., where he hasbeen engaged in research and developmentof computer-aided design and artificial in-telligence. He received his BS, MS, and DR.Eng. degree from Waseda University,Tokyo, Japan.

His address is Computer-based SystemsLaboratory, Fujitsu Laboratories Ltd.,1015 Kamikodanaka, Nakahara-ku, Kawa-saki 211, Japan.

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