IEE E TRANSACTIONS ON CIRCUI TS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PR OCE SSI NG, VOL. 47, NO. 11, NOVEMBER 2000 1325 [17] M. Sasaki, T. Inoue, Y. Shira i, and F . Ueno , “Fuzz y multip le-in put maximum and minimum circuits in current mode and their analyzes using bounded-difference equations,” IEEE Trans. Comput. , vol. 39, pp. 768–778, June 1990. [18] T. Ino ue, F. Ueno, T . Motomura, O. Setoguchi, and R. Matsuo, “New high-speed analogue max and min circuits using OTA-based bounded- difference operations,” Electron. Lett., vol. 27, pp. 1034–1035, June 1991. [19] G. Giustolisi, G. Palmisano, an d G. Palumbo, “An alog fuzzy controller in SC technique,” in Proc. CSCC’99, Athens, Greece, July 1999, pp. 363–368. [20] G. Giustolisi , G. Palmisano , and G. Palu mbo, “Switch ed capaci tor compatible minimum-maximum function,” Electron. Lett. , vol. 36, pp. 35–36, Jan. 2000. A High-Swing MOS Cascode Bias Circuit Volney Coelho Vincence, Carlos Galup-Montoro, and Márcio Cherem Schneider Abstract—In this paper, we propose a very simple bias circuit that al- lows for maximum output voltage swing of MOSFET cascode stages. The circuit topology is valid for any current density and is technology indepen- dent. Starting from the saturation voltage as defined in [ 1], and from the current density of the cascode stage, we determine the aspect ratio of the transi stors in thebias cir cui t in order to maxi miz e theoutput volt age swin g. Experimental results validate the strategy for designing the bias network. Index Terms—Analog circuits, analog integrated circuits, biasing circuit, cascode amplifier, MOS analog integrated circuits. I. INTRODUCTION Cascode current mirrors (CCM) have a much higher output resis- tance than simple current mirrors yet at the expense of the output voltage swing. Self-biased CCM’s [2], [3] have as thei r main dra wback a very serious loss of signal swing. Cascode stages with fixed bias [4]–[7], such as those shown in Fig. 1 [ 8], [9], can be optimized for high output voltage swing. In order to maximize the output voltage swing, the values of the bias voltages , and should be such that , , and , respect ively , operate at the edge of saturation. Very simple circuits in [ 7] were proposed to bias cascode mirrors either for strong inversion or for weak inversion. The cascode biasing circuit proposed in [ 4] can operate at any current level with a minimal output saturation voltage but spends a lot of silicon area and is not suitable for high frequency applications. In this brief, we extend for moderate and strong inversion one of the biasing circuits presented in [ 7], which was proposed for operation in weak inversion. The bias circuit proposed here is useful for both am- plifier configurations shown in Fig. 1. In the first part of the brief, we re vis it theMOSFE T model fro m [1] and [10] andintroduc e a def ini tio n Manuscript received January 2000; revised April 2000. This work was sup- ported in part by CAPES and by CNPq. This paper was recommended by As- sociate Editor W. Serdijn. V. C. Vincence is with the Department of Electrical Engineering, State Uni- versity of Santa Catarina, CEP 89203-100, Joinville, SC, Brazil. C. Galup-Montoro and M. C. Schneider are with the Department of Elec- trical Engineering, Federal University of Santa Catarina, CEP 88040-900, Flo- rianópolis, SC, Brazil. Publisher Item Identifier S 1057-7130(00)09933-X. Fig. 1 . (a) Fo lded c ascod e inpu t stage [ 9]. (b) Cascoded gain stage with gain enhancement [8]. of the saturation voltage based on practical aspects of circuit design. Additionally, the small-signal output resistance is discussed and asso- ciated with the saturation voltage of the driver transistor in the CCM. The analysis of the biasing topology is discussed next. Design equa- tions, as well as experimental results, are eventually presented. II. THE SATURATION VOLTAGE According to the MOSFET models in [ 1], [7], and [10], the drain current can be decomposed into the forward ( ) a nd reverse ( ) cur- rents 0 (1) where is dependent of the gate and source (drain) voltages. In forward saturation ; consequently , . The MOSFET output characteristic [ 1], [10] is modeled, in normal- ized form, as 0 0 0 (2) where (3a) (3b) (3c) is the normalization current, is the shee t norma liza tion cur- rent, is the normalized forward (reverse) current, and is the drain-to-source voltage. , , , ,and are the mobil ity , slope factor, gate oxide capacitance/area, thermal voltage ,and the transistor aspect ratio, respectively. More details about (1)–(3) can be found in [1] and [10]. In order to introduce a definition of the saturation voltage that is useful for circuit designers, we first define , the voltage gain of the common-gate amplifier [Fig. 2(a)]. Here, is the source transconductance while is the MOSFET output conductance. In- deed, “ ” is equal to the ratio of the slope of the trans isto r output characteristic at the origin ( ) to the slope of the characte r- istic at the operating point, as shown in Fig. 2. We now define the saturation voltage as the value of , f or which the volt age gain of the common-gate amplifier equals . Clearly , the so-ca lled saturat ion 1057–7130/00$10.00 © 2000 IEEE
