A Hardware/Software Co-Design Approachfor Ethernet Controllers

to Support Time-triggered Tra�cin the Upcoming IEEE TSN Standards

Friedrich Groÿ Till SteinbachFranz Korf Thomas C. Schmidt Bernd Schwarz

Hamburg University of Applied Sciences{friedrich.gross, till.steinbach, korf, schmidt, schwarz}@informatik.haw-hamburg.de

4th IEEE International Conference on Consumer Electronics - BerlinSeptember 8th, 2014

RE NET

Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REAgenda

1 Introduction & Motivation

2 Concept & Results

3 Conclusion & Outlook

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Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REMotivationWhy is Time-Triggered Ethernet needed?

Modern cars: > 70 ECUs; about 2500 message types

Bandwidth and timing requirements increase

Now used communication systems came to theirlimits due they are not scalable

Next generation backbones will most likely base onreal-time Ethernet

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Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REIntroductionHow TDMA in Time-Triggered Ethernet works

TT

cycle

cycle

TT

ECU3

cycle

BE

TT

TT

cycle

TT

BE BE

TT BE BE BE

ECU2

ECU1

Switch ECU4

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Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REIntroductionProperties of Time-Triggered Ethernet

Real-time extension for standard Ethernet

Deterministic behavior, low latency and jitter

Clock synchronisation and special switches areneeded

TTEthernet, Pro�net IRT,upcoming IEEE 802.1Qbv, . . .

This work focuses TTEthernet AS6802

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Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REMotivationWhy Hardware/Software Co-Design?

Reduce computational power

On a high network load up to 90% of a CPU is used(ARM9 @ 200Mhz) 1

One reception bu�er for all tra�c-classesEvery received frame must be handled immediatelyfor garbage collection

Reduce timing requirements for OS

CAN-Bus and FlexRay achieved good results withHW/SW Co-Design

1K. Müller �A Real-time Ethernet Prototype Platform for Automotive

Applications,� in 2011 ICCE-Berlin

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Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REContribution

Scalable HW/SW Co-Design TTEthernet Controller

Include clock synchronisation

Results of a prototype implementation on a FPGA

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Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REAgenda

1 Introduction & Motivation

2 Concept & Results

3 Conclusion & Outlook

7 / 21

Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REConceptTypical Ethernet Design

CPU

CPU-Bus

MAC

PHY

FIFO

Memorycontroller

ExternalRAM

1-to-1

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Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REConceptMain Idea

CPU

CPU-Bus

MAC

PHY

Time- TriggeredEthernetCoprocessor

1-to-1

9 / 21

Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REConceptArchitecture

PHY

MAC

TimestampInjector

Switch

CPU

TX-Buffers

...

TTBE Guard

RX-Buffers

...BETT

Fixed point timer

CPU-Bus

GMII/MII

FPGA

PHY_DV

TX

RX

Sync

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Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REConceptArchitecture - Timestamp Injector

PHY

MAC

TimestampInjector

Switch

CPU

TX-Buffers

...

TTBE Guard

RX-Buffers

...BETT

Fixed point timer

CPU-Bus

GMII/MII

FPGA

PHY_DV

TX

RX

Sync

Timestamps needed forSynchronisation andvalidation of TT Frames

SW-Implementation haslow accuracy

Record Timestamps withPHY_DV (10 ns jitter)

Validate with rx interrupt

FIFO for TS

Works on the �y

Delay of 2 clock cycles

109 LUTs (=̂ 5%); 72 Flip Flops (=̂ 3.8%) of all (+ HW FIFO)

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Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REConceptArchitecture - Switch

PHY

MAC

TimestampInjector

Switch

CPU

TX-Buffers

...

TTBE Guard

RX-Buffers

...BETT

Fixed point timer

CPU-Bus

GMII/MII

FPGA

PHY_DV

TX

RX

Sync

Need to separate Tra�cto di�erent Bu�ers

SW-Implementation needsthe most CPU-Resources

Switches based onDest-MAC, Ether-Type,Timestamp

Independent interrupts

Application speci�c bu�ersize

Works on the �y

Delay of 6 clock cycles

307 LUTs (=̂ 14.1%); 529 Flip Flops (=̂ 11.7%) of all

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Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REConceptArchitecture - Synchronisation

PHY

MAC

TimestampInjector

Switch

CPU

TX-Buffers

...

TTBE Guard

RX-Buffers

...BETT

Fixed point timer

CPU-Bus

GMII/MII

FPGA

PHY_DV

TX

RX

Sync

Synchronize internal clockto network clock

SW-Implementation needmore energy

On fullHW-Implementation OSmodi�cation is very low

Full AS6802 clientimplementation

Rate-correction

1100 LUTs (=̂ 50.3%); 736 Flip Flops (=̂ 21%) of all

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Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REConceptArchitecture - Fixed point timer

PHY

MAC

TimestampInjector

Switch

CPU

TX-Buffers

...

TTBE Guard

RX-Buffers

...BETT

Fixed point timer

CPU-Bus

GMII/MII

FPGA

PHY_DV

TX

RX

Sync

Addon for Synchronisation

Keeps clock synchronizedduring the whole cycle

Smaller reservationwindow-> more bandwidth

SW-Implementationimpossible

Rate-correctable timerimplemented asFixed-Point timer

55 LUTs (=̂ 2.5%); 55 Flip Flops (=̂ 1.2%) of all

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Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REConceptArchitecture - TX-Bu�ers and Guard

PHY

MAC

TimestampInjector

Switch

CPU

TX-Buffers

...

TTBE Guard

RX-Buffers

...BETT

Fixed point timer

CPU-Bus

GMII/MII

FPGA

PHY_DV

TX

RX

Sync

Sends TT on schedule andBE messages between TTmessages

CPU can put asyncmessages to Bu�ers

OS don't needTime-Triggered schedulefunctions

SW-Implementation hashigh Jitter 1µs to 10µs

HW-Implementation has80ns Jitter

Application speci�c bu�ersize

614 LUTs (=̂ 28.1%); 475 Flip Flops (=̂ 5.4%) of all

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Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REConceptPossible Partitioning

PHY

MAC

TimestampInjector

Switch

CPU

TX-Buffers

...

TTBE Guard

RX-Buffers

...BETT

Fixed point timer

CPU-Bus

GMII/MII

FPGA

PHY_DV

TX

RX

Sync

Sync

CPU-Res.: few percent

HW-Res.: safe 21% FF'sand 50.3% LUT's

Accuracy: no e�ect

Energy: much higher

16 / 21

Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REConceptPossible Partitioning

PHY

MAC

TimestampInjector

Switch

CPU

TX-Buffers

...

TTBE Guard

RX-Buffers

...BETT

Fixed point timer

CPU-Bus

GMII/MII

FPGA

PHY_DV

TX

RX

Sync

TX-TTTX-BE

TX-FIFO

CPU-Res.: few percent

HW-Res.: safes 1% FIFO'sand 18.6% LUT's

Accuracy: Jitter rises upto 10µs

Energy: still is nostatement possible

17 / 21

Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REConceptHW/SW Co-Design

PHY

MAC

TimestampInjector

Switch

CPU

TX-Buffers

...

TTBE Guard

RX-Buffers

...BETT

Fixed point timer

CPU-Bus

GMII/MII

FPGA

PHY_DV

TX

RX

Sync

RX-TTRX-BESYNC

RX-FIFO

CPU-Res.: up to 90%

HW-Res.: safes 31%FIFO's and 55% LUT's

Accuracy: no e�ect

Energy: much higher

18 / 21

Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REAgenda

1 Introduction & Motivation

2 Concept & Results

3 Conclusion & Outlook

18 / 21

Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REConclusion

Full Hardware implementation of a TTEthernetController

Approach how to scale it

Result: HW/SW Co-Design is a good way to deduceCPU consumption of a Time-Triggered Ethernetprotocol stack.

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Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REOutlook

AUTOSAR is a automotive system architecturewithout time-triggered scheduling mechanisms

Develop driver for AUTOSAR

Run di�erent partitions of HW/SW Co-Desing

20 / 21

Hochschule für Angewandte Wissenschaften Hamburg Hamburg University of Applied Sciences

HW/SW Co-Design forTDMA Ethernet

controllers

F. Groÿ

Introduction &Motivation

Concept & Results

Conclusion & Outlook

REThank you!

Thank you for your attention!

Website of CoRE research group:http://www.haw-hamburg.de/core

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