a guide to designing with the gv7601 aviia™ hd...

A Guide to Designing with the GV7601 Aviia™ HD Receiver

Design Guide

1 of 16

Proprietary & Confidential

A Guide to Designing with the GV7601 Aviia™ HD ReceiverDesign Guide53599 - 0 January 2010

www.gennum.com

www.gennum.com

Contents

Overview ..............................................................................................................................................................3

1. Power.................................................................................................................................................................3

1.1 Power Supply .....................................................................................................................................3

1.2 Power Filtering and Decoupling ..................................................................................................4

1.2.1 1.2V Power Supply Considerations ................................................................................5

1.3 VCO Decoupling ...............................................................................................................................5

2. Serial Digital Input and Output.................................................................................................................6

2.1 Serial Digital Input ...........................................................................................................................6

2.2 Serial Digital Output ........................................................................................................................8

2.3 Loop Filter and Bandgap Inputs ..................................................................................................9

3. Upstream Communications Channel .................................................................................................. 10

3.1 HDcctv Communication Channel Overview ....................................................................... 10

3.2 Upstream Transmit Filter ............................................................................................................ 10

3.3 Filter Layout Recommendations .............................................................................................. 11

4. Parallel Outputs (Clock and Data)......................................................................................................... 12

5. Digital Audio Output ................................................................................................................................. 13

6. GV7601 Schematic..................................................................................................................................... 14

7. HDcctv Repeater......................................................................................................................................... 15

Version ECR Date Changes and / or Modifications

0 152778 January 2010 New document.


2 of 16


OverviewThis document serves as a reference for designing with the GV7601 Aviia™ HD Receiver for HDcctv applications. This document contains two main areas of focus:

1. Considerations in the schematic deign.

2. Recommended PCB layout practices when designing with the GV7601.

The figure below shows the features and the functions of the GV7601.

HDcctv Rx Block Diagram

1. Power

1.1 Power SupplyThe GV7601 requires stable (±10%) power with low noise. Ideally, these voltages are provided by linear voltage regulators.

The GV7601 requires two voltages; +3.3V and +1.2V with optional +1.8V for the digital I/Os which can be powered either by +1.8V or +3.3V.

The +1.2V powers the digital core as well as the analog portions of the chip, such as the PLL components. The +3.3V powers the on-chip cable driver, serial digital input buffer, other sensitive analog circuitry and digital I/O. For optimal performance, it is essential that these supplies are isolated to avoid external noise coupling.

It is recommended to use separate power planes for those supplies, as well as two separate ground planes; one for analog and one for digital.

These supplies, together with an adjacent ground plane, can be broken down into four groups: +1.2VA/AGND, +3.3VA/AGND, +1.2V/GND and IO_VDD/GND. See Figure 1-1: GV7601 Power Supply Filtering and Decoupling.

GV7601(Receiver)

AudioO/P

ParallelVideo O/P

OptionalLoop-Through

(Downstream Only)

HDcctv Input

Audio

20-bit Video

Audio Clock

GennumGV8500Power

UpstreamCommunications

FVH/PCLK

DownstreamCommunications


3 of 16


Figure 1-1: GV7601 Power Supply Filtering and Decoupling

The following guidelines are suggested when designing power for the GV7601:

• Use coupled power and ground planes i.e. use minimum spacing between power and ground planes. Power and ground planes form a natural capacitor, which will increase capacitance

• Do not overlap power planes. If it is unavoidable, different power planes should be isolated from each other with the ground plane between them

• Power and ground planes should be placed near the component side, which will reduce inductance of vias

• If possible, use multiple vias to connect components to power supply

• Use low ESL, low ESR capacitors

Isolate the power plane and ground from the main plane in a 'moat'. Gennum recommends that power and ground connections to this 'island' be made through 0Ω resistors, which are decoupled on both sides. In the case where better filtering is required, 0Ω resistors can be replaced with an inductor or ferrite beads. Place at least 1μF capacitor on the entrance of the power plane. If possible, running high-speed traces across a moat should be avoided. See Figure 1-2.

Figure 1-2: Isolated Powers in a Moat

1.2 Power Filtering and DecouplingIt is recommended to decouple each power supply pin with a 10nF capacitor. Decoupling capacitors should be connected between a power supply and the related ground, see Figure 1-2.

C9

1u

C26

1u

C25

1u

C31

1u

C17

10n

C34

10n

C16

10n

C27

10nC15

10n

R12

0R

R10

0R

R2

0R

C30

10n

C14

10n

C8

10n

C29

10n

C24

10nR91

0R

C33

10n

R11

0RC13

10nC35

10n

C12

10nC32

10n

C28

10n

C11

10n

A_GND

DNP

3.3V or 1.8V3.3V

GND

GNDGND

GND

+1.2V+1.2V

IO_VDD+3.3V_A

+1.2V_A

C10

1u

A_GND

Close to pinsB1, E1 & H1

Close to pinsA4, B2, C3 & C4

Close to pinsA7, D10, G10& K7

Close to pinsD6, E6, F6 & G6

Main Power Plane

Main Ground Plane

Isolated Power Plane

Isolated Ground Plane

0R

0R

++

Via to Ground

Via to Power

Via to Ground

Via to Power


4 of 16


All decoupling and filtering ceramic capacitors should be placed as close as possible to the related pins of the GV7601. Please see Figure 1-1.

Ideally, the bypass capacitors should be physically located between the power plane and the power pin. Current should flow from the power plane to the capacitor to the power pin. See Figure 1-3.

Figure 1-3: Power Filtering and Decoupling

For the power pins of the outside rows of a BGA, the decoupling capacitors should be placed on the top layer. For the power pins of the inner rows of a BGA, the decoupling capacitors can be placed on the bottom layer, close to the related power pin.

See Figure 1-1: GV7601 Power Supply Filtering and Decoupling for power decoupling and filtering.

1.2.1 1.2V Power Supply Considerations

The GV7601 is very sensitive to low-frequency supply noise on the 1.2V VCC and any noise will directly phase modulate the output.

Gennum recommends that separate decoupling capacitors and filtering ferrite beads are added on the 1.2V_A power supply to minimize noise coupled from the 1.2V core current.

For best performance, a separate regulator (linear) may be used for the 1.2V_A rail. While the GV7601 is not sensitive to latch-up, consideration must be given to power sequencing in this case.

Use local linear regulation whenever possible.

1.3 VCO DecouplingTo minimize jitter, it is particularly important to maintain low noise on the VCO power supply. It is recommended to connect VCO_VDD pin to the 1.2V analog power plane through the RC filter shown in Figure 1-4. The RC components should be placed as close as possible to the GV7601, and further away from noise sources.

Power Pin

Vias fromPower Plane

10nF Capacitor

CurrentFlow

Trace

Trace

Trace

Ground


5 of 16


Figure 1-4: VCO Decoupling

2. Serial Digital Input and Output

2.1 Serial Digital InputThe GV7601 has one serial digital input, which accepts data rates of 270Mb/s, 1.485Gb/s and 2.97Gb/s. To meet HDcctv performance requirements, the GV7601 includes an integrated cable equalizer.

Special consideration must be paid to component layout when designing high-speed Serial Digital Interfaces. An FR-4 dielectric can be used, however, controlled impedance transmission lines are required for PCB traces longer than approximately 1cm. Note that the following PCB artwork features are used to optimize performance:

• PCB trace width for 1.485Gb/s signals is closely matched to SMT component width to minimize reflections due to change in trace impedance

• The PCB ground plane is removed under the GV7601 input compounds to minimize parasitic capacitance

• High-speed traces are curved to minimize impedance changes

The GV7601 circuit schematic is shown in Section 6., including the upstream communications channel. However, designs which do not require the upstream communications channel will need to use the simplified input schematic shown in Figure 2-1. The PCB layout of the serial digital input is shown in Figure 2-2, also without the upstream communications channel.

A_GND

R7105R

C18

33u

+1.2VA

VCO_VDD


6 of 16


Figure 2-1: Serial Digital Input without Upstream Communications Channel

Figure 2-2: Layout without Upstream Communications Channel

SDI

SDIC1

D1

1μ

37R475R

6n2

75RBNC

1

7

GND

1μ

GND


7 of 16


2.2 Serial Digital OutputThe serial digital input is equalized and re-timed, and sent to the loop-through outputs, SDO/SDO. These are differential signals with a 100Ω impedance. The serial digital output can be used for HDcctv repeater applications, where multiple runs of coaxial cable can be connected together using repeaters for long distance transmission. In order to meet HDcctv performance requirements, a cable driver is required. Gennum’s GV8500 is the recommended cable driver for use with the GV7601.

See Section 2.1 for high-speed signal layout recommended practices.

Termination of the SDO/SDO traces should be placed close as possible to the GV8500. See Figure 2-3.

Figure 2-3: Termination of the SDO/SDO Traces

Anti-pads also apply to the pull-up resistor for the RSET pin. Any impedance transition shall be avoided on these transmission lines. Running high-speed traces through vias should be avoided.

Figure 2-4: Anti-pad for shunt component on transmission lines

Figure 2-5: Anti-pad for serial components on transmission lines

R R49.9 49.9

10nF

AGND

GV7601 GV8500SDO

SDO

SDI

SDI

2

1

0402 Sized Component

Anti-pad (Cut out in all underlying layers)expending from 50% component length

15% Reduction in transmission line width

5 mils

ComponentLength

Anti-pad (Cut out in all underlying layers):85% of component width and length for 5-mil thick dielectric, as shown50% of component width and length for 10-mil thick dielectric

Pad width altered to match the width ofthe transmission line

Component

Transmission line


8 of 16


2.3 Loop Filter and Bandgap InputsFigure 2-6 shows the recommended loop filter and bandgap components.

Figure 2-6: Loop filter and bandgap components

Since these are noise-sensitive inputs, place the components close to the GV7601, and avoid routing the other digital signals under them or close to them.

Table 2-1: LB_CONT Setting

LB_CONT Full HD HD SD Unit

GND 6 3 0.55 MHz

Floating 3 1.5 0.27 MHz

VCC 1.5 0.75 0.14 MHz

A_GND

Floating or +3.3V or GND

R21 DNP

R19DNP

VBGA1

LFA2

LB_CONTA3

Close to GV7601+3.3VA

C41 47n

LB_CONT Settings:

C42 1u

HDcctv 1.0


9 of 16


3. Upstream Communications Channel

3.1 HDcctv Communication Channel OverviewIn addition to the high-speed (1.485Gb/s) serial digital video downstream channel, the Aviia solution provides for a bidirectional communication channel that supports full duplex data rates up to 10Mb/s. In order to implement this communication channel over a single coaxial cable, two technologies are being deployed.

1. The Downstream communication channel is multiplexed with the downstream serial digital video using the ancillary data space allocated to each video frame.

2. The Upstream communication channel is implemented using a frequency multiplexing technique over the same communication media (coax cable) as the main serial digital video channel. The Upstream channel digital data is encoded using a 4b/5b technique to be compatible with an AC-coupled communication channel.

For detailed implementation of the serial digital video and communication protocol please refer to the HDcctv standard.

3.2 Upstream Transmit FilterIn order to support a high speed upstream communication channel without affecting the high performance of the downstream serial digital video, the transmit band pass of the upstream channel is precisely shaped using a high quality Active Low Pass Filter (LPF). The block diagram of this module is presented in the Figure 3-1 below:

Figure 3-1: HDcctv Upstream Transmit Filter Block Diagram

GS7601

PassiveHPF

Coax Cable

ActiveLPF

PassiveHPF

LPFCoupling

LF>HF Crosstalk Cancelation

Upstream Communication

Channel

DigitalVideo Out

HD Video &Downstream CC

Upstream CC

Downstream Communication

Channel

LogicBuffer

LPFCoupling


10 of 16


The active filter is designed as a three-pole Butterworth low-pass filter, with a cut-off frequency of 7MHz and a pass-band gain of 1. The input stage into the active filter uses a LVC buffer to ensure that proper voltage swing levels are being applied to the input op amp stage.

The peak-to-peak voltage amplitude of the communication channel signal is 1V +/- 10%.

Coupling between the active filter output and transmission line is accomplished using a LPF ferrite that insures minimal interference between the high-speed and low-speed devices.

The single-pole passive High Pass Filters (HPF) at the input of the GS7601 device prevents the low frequency channel from interfering with the operation of the high-speed video channel.

Additionally, a proprietary crosstalk cancellation technique is used at the high-speed input of the serial digital video receiver device to further improve the signal integrity of the link.

3.3 Filter Layout RecommendationsIn order to maximize efficiency of the active filter and prevent undesirable ripples, the filter circuitry is required to be grouped and located in a compact area of the board, providing good isolation from external noise sources like switchers and oscillators. The traces on the input and output of the op amps have to be routed with low parasitic capacitance and inductance, in such manner that the input and output signal paths are not being intertwined. The serial impedance matching resistors R21 and R22, illustrated in Figure 3-2 below, should be placed as close as possible to the output pin of the op amp U3.

Figure 3-2: Output Section of the Upstream Communications Channel


11 of 16


It is important that the L3 and L4 ferrites are placed as close as possible to the transmission lines that they couple into. Layout guidelines presented for the transmission line apply to L3 and L4, where it is recommended to open the ground plane underneath the ferrite devices, and place the coupling pad embedded into the transmission line to minimize impedance discontinuities.

4. Parallel Outputs (Clock and Data)

The GV7601 features an ITU-R BT.1120 parallel video output which operates at a pixel rate of 74.25MHz for a 20-bit wide bus, or 148.5MHz for a 10-bit multiplexed data bus.

The primary consideration with clock and I/O data, is to route them in a manner that reduces capacitive and inductive crosstalk, while maintaining equivalent lengths.

To get a reasonable timing margin, keep the routing lengths of the bus signals and synchronous signals to approximately the same length (<±0.5” tolerance).

If a 10-bit wide output is not required, or the length of the traces is not more than 2", trace length matching is not required.

To minimize the crosstalk, the clock traces must be at least 3x the trace width away from adjacent signals, or the clock trace can be isolated by low impedance reference (power or ground).

Try to avoid vias on the clock nets. Always use smooth-curving traces for all clock signals.

The digital outputs of the GV7601 (DOUT[19:0], PCLK and STAT[5:0]) have programmable drive strength. Serial termination resistors on these signals are not normally required when the traces are not very long and the signals are not going through a connector.


12 of 16


5. Digital Audio Output

The GV7601 audio outputs (AOUT1/2, AOUT3/4, AOUT5/6 and AOUT7/8) provide CMOS level S/PDIF or AES encoded outputs. The outputs can also be configured for I2S serial audio for device-to-device audio connectivity.

NOTE: For most applications, the GV7601 does not drive external audio interfaces. In order to connect to an external digital audio interface, a 5V differential cable driver is needed. See Figure 5-1 for the balanced AES, unbalanced AES and S/PDIF interfaces.

Figure 5-1: Balanced and Unbalanced Digital Audio Interfaces

S/PDIForAES

IO_VDD 3.3V 5V

110Ω

0.1μF

Required if IO_VDD = 1.8V

S/PDIForAES

IO_VDD 3.3V 5V

R10.1μF

R2

R10.1μF

R2

Balanced AES Interface

Unbalanced AES Interface

Common S/PDIF Interface

Required if IO_VDD = 1.8V


13 of 16


6. GV7601 Schematic

Figure 6-1: GV7601 Schematic

LB_CONT Settings:Floating or +3.3V or GND

Close to GV7601

Close to GV7601

COAX

Disable Serial Outputswhen not used

Channel - Transmit

Upstream

Communications

HD Video & UCCInput Return Loss

HostInterface

Control

GV7601 Power Decoupling & Filtering

BT. 1120Bus

Timing

Status

Audio Out

SDO_EN

SDO_EN

DOUT0

LOCKED

DATA ERROR

PCLK

DOUT1

DOUT2DOUT3DOUT4DOUT5DOUT6DOUT7DOUT8DOUT9

DOUT10DOUT11

DOUT12DOUT13DOUT14DOUT15DOUT16DOUT17DOUT18DOUT19

HVF

Y/1ANC

MCLKAOUT1/2AOUT3/4AOUT5/6AOUT7/8ACLKWCLK

861_EN656_BYPASSb

ASIAUDIO_ENPROC_EN

20BIT/10BITbSDO_EN

RECLK_ENSTANDBYJTAG_EN

RESETb

SDOUTSDINSCLK

CSb

TTL_CTRL_IN

GND

GND

3.3V

GND

GND

GND

GND

1.2V

IO_VDD

3.3V_A

1.2V_A

GND

GND

GND

GND

GND

GND

1.2V

1.2V1.2V_A

1.2V_A

3.3V_A

3.3V_A3.3V_A IO_VDD

GND

GND

GND

3.3V 3.3V

GND GND

GND

GND GND GND

GND

GND

3.3V

GND

GND

U2

SN74LVC1G17MDBVREP

U2

SN74LVC1G17MDBVREP

3

GND

4Y

5VCC

A2

C14 1uC14 1u

C510nC510n

R180RR180R

C2510nC2510n

J1BNC

J1BNC

1

7

U1

GV7601

U1

GV7601

VBGA1

LFA2

LB_CONTA3

VC

O_V

DD

A4

STAT0A5STAT1A6STAT2B5

STAT3B6

STAT4C5

STAT5C6

IO_V

DD

A7

PCLKA8

DOUT0K8DOUT1J8

DOUT2K9DOUT3K10DOUT4J9DOUT5J10DOUT6H9DOUT7H10DOUT8F9DOUT9F10

DOUT10E9DOUT11E10

DOUT12C8DOUT13C10DOUT14C9DOUT15B10DOUT16B9DOUT17A10DOUT18A9DOUT19B8

AV

DD

B1

PLL

_VD

DB

2

RSVB3

VC

O_G

ND

B4

IO_G

ND

B7

SDIC1

AG

ND

C2

PLL

_VD

DC

3

PLL

_VD

DC

4

RESETC7

SDID1

AG

ND

D2

AG

ND

D3

PLL

_GN

DD

4

CO

RE

_GN

DD

5

CO

RE

_VD

DD

6

RSVD7

JTAG_END8

IO_G

ND

D9

IO_V

DD

D10

EQ

_VD

DE

1

AG

ND

E3

PLL

_GN

DE

4

CO

RE

_GN

DE

5

CO

RE

_VD

DE

6

SDOUT_TDOE7

SDIN_TDIE8

AGCF1

RSVF2

AG

ND

F3

PLL

_GN

DF

4

CO

RE

_GN

DF

5

CO

RE

_VD

DF

6

CS_TMSF7 SCLK_TCKF8

AGCG1

AG

ND

G2

RECLK_ENG3

CO

RE

_GN

DG

4

CO

RE

_GN

DG

5

CO

RE

_VD

DG

6

656_BYPASSG7

ASIG8

IO_G

ND

G9

IO_V

DD

G10

BU

FF

_VD

DH

1B

UF

F_G

ND

H2

AUDIO_ENH3

WCLKH4

861_ENH5

XTAL_OUTH6

20BIT/10BITH7 PROC_ENH8

SDOJ1

SDO_ENJ2

AOUT1/2J3

ACLKJ4

AOUT5/6J5

XTAL2J6

IO_G

ND

J7

SDOK1

STANDBYK2

AOUT3/4K3

MCLKK4

AOUT7/8K5

XTAL1K6

IO_V

DD

K7

EQ

_GN

DE

2

C40 1uFC40 1uF

C2010nC2010n

C32 1uFC32 1uF

R16 75RR16 75R

R8 22RR8 22R

L2 6n2L2 6n2

R11 22RR11 22R

TP1TP1

TP2TP2

R2475RR2475R

-

+

U3B

OPA2830IDGK-

+

U3B

OPA2830IDGK

75

6

R2175RR2175R

C2410nC2410n

C111uC111u

C2210nC2210n

R1105RR1105R

R290RR290R

L1 6n2L1 6n2

R9 22RR9 22R

R2275R

R2275R

Y1 CS10-27.000MY1 CS10-27.000M

C341uFC341uF

R2575RR2575R

RN2 742C163220RN2 742C163220

123456789

10111213141516

C43

DNP

C43

DNP

-

+

U3A

OPA2830IDGK-

+

U3A

OPA2830IDGK

4

13

2

8

C8 47nC8 47n

C41uC41u

R60RR60R

R14 22RR14 22R

C37

100nF

C37

100nF

C122uC122u

C610nC610n

C710nC710n

R27 1.5KR27 1.5K

R20RR20R

C13 16pC13 16p

L3BLM15HD102SN

L3BLM15HD102SN

C4127pFC4127pF

R280RR280R

R2075RR2075R

C27470nC27470n

R17 75RR17 75R

R15 22RR15 22R

C4215pFC4215pF

L4BLM15HD102SNL4BLM15HD102SN

R26768RR26768R

C38

100nF

C38

100nF

C1910nC1910n

R1975RR1975R

C28

470n

C28

470n

C2310nC2310n

R32DNPR32DNP

R232.21KR232.21K

C31uC31u

R7 22RR7 22R

C17 16pC17 16p

R12 22RR12 22R

C1510nC1510n

R301.21KR301.21K

R31100RR31100R

C331uFC331uF

R3DNPR3DNP

C181uC181u

C31 220pFC31 220pF

C210nC210n

C39 330pFC39 330pF

C2610nC2610n

C101uC101u

C29 220pFC29 220pF

C1610nC1610n

C3510uFC3510uF

R5 DNPR5 DNP

C2110nC2110n

C30 1uFC30 1uF

R10 22RR10 22R

C910nC910n

R13 22RR13 22R

C36100nFC36100nF

R4 22RR4 22R

RN1 742C163220RN1 742C163220

123456789

10111213141516

C1210nC1210n


14 of 16


7. HDcctv Repeater

The HDcctv repeater design utilizes the serial digital loop-through output of the GV7601, connected to a GV8500 Cable Driver, as shown in Figure 7-1 below.

Figure 7-1: HDcctv Repeater Schematic

LB_CONT Settings:Floating or +3.3V or GND

Close to GV7601

Close to GV7601

COAX

HD Video & UCCInput Return Loss

GV7601 Power Decoupling & Filtering

INPUT

Lock Detect Flag

75-ohm traces

Output Return Loss

COAX

HD Video & UCC

OUTPUT

GND

GND

3.3V

GND

GND

GND

GND

1.2V

IO_VDD

3.3V_A

1.2V_A

GND

GND

GND

GND

GND

GND

1.2V

1.2V1.2V_A

1.2V_A

3.3V_A

3.3V_A3.3V_A IO_VDD

GND

GND

3.3V 3.3V

GND GND

GND

GND GND

GND

GND

3.3V

GND

GND

GND

GND GND

3.3V

3.3V

3.3V

GND

GND

3.3V

GND

GND

GND

GND

GND

GND

GND

GND

GND

3.3V

GND

GND

GND GND

3.3V

GND

GND

GNDGND

GND

GND

C14 1uFC14 1uF

C510nC510n

C2510nC2510n

L2 6n2L2 6n2J1BNC

J1BNC

1

7

R1649R9R1649R9

U1

GV7601

U1

GV7601

VBGA1

LFA2

LB_CONTA3

VC

O_V

DD

A4

STAT0A5STAT1A6STAT2B5

STAT3B6

STAT4C5

STAT5C6

IO_V

DD

A7

PCLKA8

DOUT0K8DOUT1J8

DOUT2K9DOUT3K10DOUT4J9DOUT5J10DOUT6H9DOUT7H10DOUT8F9DOUT9F10

DOUT10E9DOUT11E10

DOUT12C8DOUT13C10DOUT14C9DOUT15B10DOUT16B9DOUT17A10DOUT18A9DOUT19B8

AV

DD

B1

PLL

_VD

DB

2

RSVB3

VC

O_G

ND

B4

IO_G

ND

B7

SDIC1

AG

ND

C2

PLL

_VD

DC

3

PLL

_VD

DC

4

RESETC7

SDID1

AG

ND

D2

AG

ND

D3

PLL

_GN

DD

4

CO

RE

_GN

DD

5

CO

RE

_VD

DD

6

RSVD7

JTAG_END8

IO_G

ND

D9

IO_V

DD

D10

EQ

_VD

DE

1

AG

ND

E3

PLL

_GN

DE

4

CO

RE

_GN

DE

5

CO

RE

_VD

DE

6SDOUT_TDO

E7

SDIN_TDIE8

AGCF1

RSVF2

AG

ND

F3

PLL

_GN

DF

4

CO

RE

_GN

DF

5

CO

RE

_VD

DF

6

CS_TMSF7 SCLK_TCKF8

AGCG1

AG

ND

G2

RECLK_ENG3

CO

RE

_GN

DG

4

CO

RE

_GN

DG

5

CO

RE

_VD

DG

6

656_BYPASSG7

ASIG8

IO_G

ND

G9

IO_V

DD

G10

BU

FF

_VD

DH

1B

UF

F_G

ND

H2

AUDIO_ENH3

WCLKH4

861_ENH5

XTAL_OUTH6

20BIT/10BITH7 PROC_ENH8

SDOJ1

SDO_ENJ2

AOUT1/2J3

ACLKJ4

AOUT5/6J5

XTAL2J6

IO_G

ND

J7

SDOK1

STANDBYK2

AOUT3/4K3

MCLKK4

AOUT7/8K5

XTAL1K6

IO_V

DD

K7

EQ

_GN

DE

2

C54 1uFC54 1uF

C2010nC2010n

C37 1uFC37 1uF

R11 75RR11 75R

L3 6n2L3 6n2

R7 750RR7 750R

-

+

U4B

OPA2830IDGK-

+

U4B

OPA2830IDGK

75

6

D1

CMD15-21VGC/TR8LED GREEN

D1

CMD15-21VGC/TR8LED GREEN

2 1

R2875RR2875R

-

+

U4A

OPA2830IDGK-

+

U4A

OPA2830IDGK

4

13

2

8

-

+

U5B

OPA2830IDGK-

+

U5B

OPA2830IDGK

75

6

R2175RR2175R

R410RR410R

J2BNC J2BNC1

7

C2410nC2410n

C111uC111u

R26 0RR26 0R

R1549R9

R1549R9

C2210nC2210n

R1105RR1105R

R252.21KR252.21K

R370RR370R

C3010nFC3010nF

L1 6n2L1 6n2

R34 1.5KR34 1.5K

R2275R

R2275R

C60

DNP

C60

DNP

Y1 CS10-27.000MY1 CS10-27.000M

C271uFC271uF

C431uFC431uF

R2975RR2975R

R441.21KR441.21K

R232.21KR23

2.21K

C59

DNP

C59

DNP

-

+

U5A

OPA2830IDGK-

+

U5A

OPA2830IDGK

4

13

2

8

C5815pFC5815pF

C8 47nFC8 47nF

C41uC41u

R10750RR10750R

R50RR50R

C47

100nF

C47

100nF

C133uFC133uF

C2810nFC2810nF

C610nC610n

C5727pFC5727pF

C710nC710n

R27 1.5KR27 1.5K

R431.21K

R431.21K

C4110nFC4110nF

R20RR20R

C13 16pFC13 16pF

C53 1uFC53 1uF

L5BLM15HD102SN

L5BLM15HD102SN

C5527pFC5527pF

R4675RR4675R

C4810uFC4810uF

R32768RR32768R

R380RR380R

R1875RR1875R

C31470nFC31470nF

R13 75RR13 75R R14 75RR14 75R

C5615pFC5615pF

R30 75RR30 75R

R4575RR4575R


R35768RR35768R

C49100nFC49100nF

C1910nC1910n

R48DNPR48DNP

C50

100nF

C50

100nF

L4 6n2L4 6n2

R1775RR1775R

C32

470nF

C32

470nF

R62.21KR62.21K

C2910nFC29

10nF

C2310nC2310n

R47DNPR47DNP

R242.21KR242.21K

C31uC31u

C44

100nF

C44

100nF

C38 220pFC38 220pF

C17 16pFC17 16pF

C391uFC391uF

C1510nC1510n

R3375RR3375R

R391.21KR391.21K

R40100RR40100R

C421uFC421uF

C51 330pFC51 330pF

R3DNPR3DNP

C181uC181u

C35 220pFC35 220pF

C36 220pFC36 220pF

C210nC210n

C52 330pFC52 330pF

R20 10KR20 10K

L7BLM15HD102SN

L7BLM15HD102SN

R875RR875R

C2610nC2610n

C101uC101u

C33 220pFC33 220pF

C1610nC1610n

C40 220pFC40 220pF

C4510uFC4510uF

R420RR420R


R4 DNPR4 DNP

-

+

U3TLV3501DBV

-

+

U3TLV3501DBV

51

3

42

6

C2110nC2110n

R975RR975R

C34 1uFC34 1uF

R36 1.5KR36 1.5K

C910nC910n

C46100nFC46100nF

R31 75RR31 75R

C1210nC1210n

R12 75RR12 75R

R1975RR1975R

U2GV8500U2GV8500

IN+1

IN-2

NC

5

VE

E3

VCC6

NC

14

VEE10

TA

B

NC

8

OUT-11

OUT+12

NC

15

NC

13

NC7

RSET4

VC

C9

NC

16


15 of 16


OTTAWA232 Herzberg Road, Suite 101 Kanata, Ontario K2K 2A1 Canada

Phone: +1 (613) 270-0458

Fax: +1 (613) 270-0429

CALGARY3553 - 31st St. N.W., Suite 210 Calgary, Alberta T2L 2K7 Canada

Phone: +1 (403) 284-2672

UNITED KINGDOMNorth Building, Walden Court Parsonage Lane, Bishop’s Stortford Hertfordshire, CM23 5DB United Kingdom

Phone: +44 1279 714170

Fax: +44 1279 714171

INDIA#208(A), Nirmala Plaza, Airport Road, Forest Park Square Bhubaneswar 751009 India

Phone: +91 (674) 653-4815

Fax: +91 (674) 259-5733

SNOWBUSH IP - A DIVISION OF GENNUM439 University Ave. Suite 1700 Toronto, Ontario M5G 1Y8 Canada

Phone: +1 (416) 925-5643

Fax: +1 (416) 925-0581

E-mail: [email protected]

Web Site: http://www.snowbush.com

MEXICO288-A Paseo de Maravillas Jesus Ma., Aguascalientes Mexico 20900

Phone: +1 (416) 848-0328

JAPAN KKShinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo, 160-0023 Japan

Phone: +81 (03) 3349-5501

Fax: +81 (03) 3349-5505


Web Site: http://www.gennum.co.jp

TAIWAN6F-4, No.51, Sec.2, Keelung Rd. Sinyi District, Taipei City 11502 Taiwan R.O.C.

Phone: (886) 2-8732-8879

Fax: (886) 2-8732-8870


GERMANYHainbuchenstraße 2 80935 Muenchen (Munich), Germany

Phone: +49-89-35831696

Fax: +49-89-35804653


NORTH AMERICA WESTERN REGIONBayshore Plaza 2107 N 1st Street, Suite #300 San Jose, CA 95131 United States

Phone: +1 (408) 392-9454

Fax: +1 (408) 392-9427


NORTH AMERICA EASTERN REGION4281 Harvester Road Burlington, Ontario L7L 5M4 Canada

Phone: +1 (905) 632-2996

Fax: +1 (905) 632-2055


KOREA8F Jinnex Lakeview Bldg. 65-2, Bangidong, Songpagu Seoul, Korea 138-828

Phone: +82-2-414-2991

Fax: +82-2-414-2998


DOCUMENT IDENTIFICATIONDESIGN GUIDEInformation relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a guide only and Gennum assumes no liability for any errors in this document, or for the application or design described herein. Gennum reserves the right to make changes to the product or this document at any time without notice.


16 of 1616


Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement.

All other trademarks mentioned are the properties of their respective owners.

GENNUM and the Gennum logo are registered trademarks of Gennum Corporation.

© Copyright 2010 Gennum Corporation. All rights reserved.

www.gennum.com

GENNUM CORPORATE HEADQUARTERS4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada

Phone: +1 (905) 632-2996 Fax: +1 (905) 632-2055

E-mail: [email protected] www.gennum.com

CAUTIONELECTROSTATIC SENSITIVE DEVICES

DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION

HDcctv Alliance: www.highdefcctv.org

http://www.snowbush.com

http://www.gennum.co.jp

www.gennum.com

www.gennum.com

www.highdefcctv.org

a guide to designing with the gv7601 aviia™ hd...

Documents