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A Generic VHDL-AMS Behavioral Model Physically Accounting For Analog Non-Linear Output Behavior Kamal Sabet Tamer Riad

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Page 1: A Generic VHDL-AMS Behavioral Model Physically Accounting

A Generic VHDL-AMS Behavioral Model Physically Accounting For Analog Non-Linear Output Behavior

Kamal Sabet Tamer Riad

Page 2: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 2

Outlineâ–şIntroduction

â–˛Modeling AMS Systemsâ–şAnalog Output Behavior

â–˛Conventional Modeling Approachâ–˛Circuit Inspired Approach

â–şModel Implementationâ–şExperimental Resultsâ–şApplicationâ–şConclusion

Page 3: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 3

Introduction

►Mixed-signal verification has proved essential for debugging today’s integrated SOCs.

â–şTo assert the integral operation of the entire system, several top-level simulations have to be performed.

â–şExtensive computational cost and design immaturity require top-level simulation to be performed beyond the realm of SPICE kernels.

Page 4: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 4

Modeling AMS Systems►A valid AMS system’s models must capture the correct

functionality of their corresponding blocks.

â–ş In addition, accurate interfacing must correctly account for the correct impedance at the peripheral terminals.

â–şThis becomes a challenge when functionality and loading are interdependent.

Page 5: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 5

Analog Output Behavior

â–şCommon output characteristics

â–˛Output voltage saturationâ–˛Output resistanceâ–˛Output DC levelâ–˛Output capacitanceâ–˛Output current limiting

Page 6: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 6

Modeling Voltage Saturation & Output Resistance

â–şHas to be valid in both linear and non-linear operation.

â–şThe value of output resistance should change from one mode of operation to the other.

â–şAssuming it to be the same, will yield erroneous results, which would restrains the use of this model.

Page 7: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 7

Conventional Modeling Approach

The controlled source Vx is used to decide on the output voltage Vy depending on Vin.

If Vin < Vlim1Vx = Vlim1else if Vin > Vlim2Vx = Vlim2elseVx = Vin

Page 8: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 8

Conventional Modeling Approach (cont’d)

During linear operation, Vy will be evaluated by voltage division of Vinbetween Rload and Rout.

Page 9: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 9

Conventional Modeling Approach (cont’d)

During non-linear operation, voltage division will result in a signal saturated at levels below the desired output limits.

Page 10: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 10

Circuit Inspired Approach

â–şAssumed circuit comprises of 2 hypothetical MOS-like devices connected in a push-pull topology.

â–şInput common to both gates, output at their drains.

â–şPower supplies are the limiting voltages.

Page 11: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 11

Simplified Device Models

â–şCircuit inspired approach uses Abstracted transistors.

â–şExpresses Basic transistor action.

â–şPreserves relations between model parameters and device parameters.

â–şStarting point is MOS level 1 equations.

Page 12: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 12

Device I-V Characteristicsâ–ş3 Regions of operationâ–ş2 Linear Equations

Page 13: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 13

Device I-V Characteristics (cont’d)►Cutoff operation Vgs < 0

Ids = 0

Page 14: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 14

Device I-V Characteristics (cont’d)►Linear operation Vgs > 0 & Vds < Vdsat_n

Ids = K Vgs Vds (Vdsat / Vdsat_n)

Page 15: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 15

Device I-V Characteristics (cont’d)

â–şLinear operation Vgs > 0 & Vds < Vdsat_nIds = K Vgs Vds (Vdsat / Vdsat_n)

Where;â–˛K : relates Ids to Vgs = 1 S/V for simplicity

â–˛Vdsat_n : Defines onset of saturation

â–˛Vdsat = (Vdsat_n + Vdsat_p)/ 2 : Used to balance Idsat for both devices.For the same Vgs\Vsg: Idsat = Vgs\Vgs Vdsat

Page 16: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 16

Device I-V Characteristics (cont’d)►Saturation operation Vgs > 0 & Vds > Vdsat_n

Ids = Vgs λn (Vds – Vdsat_n) + K Vgs Vdsat

Page 17: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 17

Device I-V Characteristics (cont’d)

â–şSaturation operation for Vgs > 0 & Vds > Vdsat_n

Ids = Vgs λn (Vds – Vdsat_n) + K Vgs Vdsat

Where;▲λn: Controls device output resistance in saturation

Rsat_n = δVds/δIds = 1/(Vgsλn)

▲Device transconductance Gmn = λn(Vds – Vdsat_n) + KVdsat

* Gmn independent of Vgs

Page 18: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 18

Large Signal Behavior

Vin=0, Vgs=Vsg

Page 19: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 19

Large Signal Behavior (cont’d)

Vin Increases, VgsIncreases, Vsg Decreases, Vout goes nearer to the lower rail

Page 20: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 20

Large Signal Behavior (cont’d)

Vin Decreases, VgsDecreases, Vsg Increases, Vout goes nearer to the upper rail

Page 21: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 21

DC Characteristics

â–˛Divided into 5 Regions.

â–˛Gain = -(Gmn + Gmp)Rout

â–˛Required model has to have unity gain, normalization is needed.

â–˛To insure maximum swing for o/p, biasing is needed.

Page 22: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 22

DC Characteristics (cont’d)

V = Vin/Gain + Vdc_ideal

Vdc_ideal = (Vlim1 + Vlim2)/2

Page 23: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 23

Output DC Level

►An Output DC level is created by adjusting the values of each device’s resistance in saturation.

To calculate each device resistance using the user-defined output resistance and output DC level, we use the following equations :

VSD_DC = Vlim2 - Vdc_out - Vdsat_p

VDS_DC = Vdc_out - Vlim1 - Vdsat_n

Rsat_n= rout*(1.0 + (VDS_DC)/(VSD_DC));

Rsat_p= Rsat_n*(VSD_DC)/(VDS_DC);

Page 24: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 24

Model Implementationâ–ş Implemented using VHDL-AMS â–şElectrical input and output portsâ–şParameters:

â–˛Limiting voltageâ–˛Output resistanceâ–˛Output DC level

►Coding makes use of the language’s mixed-signal nature utilizing simulator’s mixed-signal kernel for better computational efficiency

entity output_stage isgeneric ( Vlim2 : voltage := 10.0 ; -- Upper limiting voltageVlim1 : voltage := -10.0 ; -- Lower limiting voltagerout : resistance := 1.0e3; -- Output resistanceVdc_out: voltage := 0.0; -- DC out voltageVmax1:real := -9.9; -- Lower saturation start VoltageVmax2:real := 9.9); -- Upper saturation start Voltageport ( terminal ain : electrical; -- input terminalterminal aout : electrical); -- output terminalend entity output_stage;architecture A1 of output_stage is…………V_in == Vin/gain + Vdc_ideal;Vps == Vlim2;Vns == Vlim1;if not Vgs’above(0.0) use Ids == 0.0;elsif not vds’above(Vdsat_n) use Ids*Vdsat_n ==Vgs*Vds*Vdsat;else Ids == Vgs*lambdaN*(Vds-Vdsat_n) + Vgs*(Vdsat);end use;if not Vsg’above(0.0) use Isd == 0.0;elsif not vsd’above(Vdsat_p) use Isd*Vdsat_p ==Vsg*Vsd*Vdsat;else Isd == Vsg*lambdaP*(Vsd-Vdsat_p) + Vsg*(Vdsat);end use;break on Vgs’above(0.0),Vsg’above(0.0);break on Vds’above(Vdsat_n),Vsd’above(Vdsat_p);end architecture A1;

Page 25: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 25

Experimental Setup

â–şSimulations performed using Mentor Graphics, ADVance MSTM mixed signal simulator.

â–şLoading effect test performed on both the conventional approach model and our proposed model.

â–şA DC analysis is performed while sweeping input Voltage both with and without load.

Page 26: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 26

Experimental Results

Conventional Approach Circuit inspired Approach

Page 27: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 27

Application

â–şTypical application for model would be as an amplifier output stage.

â–şSimplifies amplifier modeling to input characteristics and core functionality(gain, frequency response).

â–ş In case of balanced differential output, model could be instantiated twice with parameters adjusted to account for differential characteristics.

â–şModel was used as an opamp output stage and it showed ease of convergence in different feedback configurations.

Page 28: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 28

Conclusionâ–şModeling analog output behavior should preserve

interaction between voltage saturation and output resistance.

â–şDisregarding such interaction will lead to erroneous results restraining the use of the behavioral model.

â–şUsing abstracted circuit physics successfully captures these inter-related effects.

â–şOur model provides a solution for modeling output characteristics of an amplifier .

Page 29: A Generic VHDL-AMS Behavioral Model Physically Accounting

BMAS 2007Slide 29

Thank You


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