a fast pll method for power electronic

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The 33rd Annual Conference of the IEEE Industrial Electronics Society (IECON) Nov. 5-8, 2007, Taipei, Taiwan A Fast PLL Method for Power Electronic Systems Connected to Distorted Grids Mu WEI1,2 Zhe CHEN' IInstitute of Energy Technology, Aalborg University, Aalborg, Denmark 2Faculty of Electronics and Information Engineering, Southwest University, Chongqing, P.R. China mwegiet.aau.dk, zchgiet.aau.dk Abstract- A phase-locked loop (PLL) for power electronic systems is presented in this paper. The PLL system can fast detect the voltage magnitudes, phase angles and frequency under distorted power system conditions. A series of simulation studies have been conducted. The results are presented and compared with some other PLL systems. I. INTRODUCTION In ac power systems, the phase, amplitude and frequency of the grid voltage are very important information for grid- connected operation. Especially for power electronic converters which are more and more used as the interface for distributed generation (DG) units, the information of grid voltage is essential for operation and control of the power electronic converters and the interfaced DG units. With the increase of the DG units and the renewable energy generation units, such as wind and solar energy conversion system, the accurate grid voltage information becomes crucial for system security and quality power supply. Therefore the phase-locked loop (PLL) can be considered to be an important part of grid-connected power generation systems. The PLL technique has been used as a common way of obtaining the phase and frequency information in electrical systems. For power electronic applications, the PLL technique has been adopted for the speed control of electric motors. It has also been used for generating the reference signals synchronized with the utility voltages in power conversion systems. A simple method of obtaining the phase information is the zero-crossing method, which detects the zero crossing points of the utility ac voltages. However, the zero crossing points can only be detected at every half-cycle of the ac frequency, the phase tracking becomes impossible between the detecting points, consequently, the fast tracking performance cannot be achieved. In three-phase systems, the dq transform of the three-phase variables has the quadrature feature, as the "synchronous d-q frame reference" SRF PLL [1], which can be used in various applications for the detection of the phase or angular position. But the waveforms of the grid voltage may be the distorted with harmonics and unbalanced voltages, which could seriously affect the accuracy of the obtained grid voltage information. This paper firstly briefs the principle of the SRF-PLL, discusses the concept used for extracting fundamental positive sequence component [2] and the Software based PLL [3]. Then the proposed PLL is introduced. The simulation studies have been conducted. The performances of the proposed PLL have been investigated and compared with the SRF-PLL and the software based PLL systems. II. SYNCHRONOUS REFERENCE FRAME (SRF)-PLL The synchronous d-q reference frame PLL is a simple and stable three-phase PLL system which detects the phase angle in the synchronous d-q reference frame, the reference frame is synchronized to the input voltage frequency [1]. A block diagram of SRF-PLL is shown in Fig. 1. V~ Vb~ |M| + iff s S *0 -f Fig. 1 Basic structure of SRF-PLL The closed loop transfer function of this system can be represented as a generalized second order system in (1): (1) Hclose(S) = 2Gw(n s + tq9n s2 + 2 s+w 2 Where, K = 2 /o) E ,K=o2 Em, Ti= =l/K and Kp is the proportional gain and Ki is the integral gain of the PI controller, and Em is the magnitude of the input signal. Depending on the pre-conditioning applied on the signals, the signal entering the system may be normalised or non- normalised. If the normalised PLL system is adopted by using the output of M , then the Em for the parameters of PI controller may be taken as unity. Consequently, the PI controller parameters may not be affected by the variations of input utility voltage value. However, the measured waveform may be unbalanced with negative and zero sequence components, the harmonics and distortions could deteriorate the performance of the simple SRF PLL system. Thus the conventional methods are not sufficient to cope with various distortions of the measured voltage signals. 1-4244-0783-4/07/$20.00 C 2007 IEEE 1702

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Page 1: A Fast PLL Method for Power Electronic

The 33rd Annual Conference of the IEEE Industrial Electronics Society (IECON)Nov. 5-8, 2007, Taipei, Taiwan

A Fast PLL Method for Power ElectronicSystems Connected to Distorted Grids

Mu WEI1,2 Zhe CHEN'

IInstitute of Energy Technology, Aalborg University, Aalborg, Denmark2Faculty of Electronics and Information Engineering, Southwest University, Chongqing, P.R. China

mwegiet.aau.dk, zchgiet.aau.dk

Abstract- A phase-locked loop (PLL) for power electronicsystems is presented in this paper. The PLL system can fastdetect the voltage magnitudes, phase angles and frequency underdistorted power system conditions. A series of simulation studieshave been conducted. The results are presented and comparedwith some other PLL systems.

I. INTRODUCTION

In ac power systems, the phase, amplitude and frequency ofthe grid voltage are very important information for grid-connected operation. Especially for power electronicconverters which are more and more used as the interface fordistributed generation (DG) units, the information of gridvoltage is essential for operation and control of the powerelectronic converters and the interfaced DG units. With theincrease of the DG units and the renewable energy generationunits, such as wind and solar energy conversion system, theaccurate grid voltage information becomes crucial for systemsecurity and quality power supply.

Therefore the phase-locked loop (PLL) can be considered tobe an important part of grid-connected power generationsystems. The PLL technique has been used as a common wayof obtaining the phase and frequency information in electricalsystems. For power electronic applications, the PLL techniquehas been adopted for the speed control of electric motors. Ithas also been used for generating the reference signalssynchronized with the utility voltages in power conversionsystems. A simple method of obtaining the phase informationis the zero-crossing method, which detects the zero crossingpoints of the utility ac voltages. However, the zero crossingpoints can only be detected at every half-cycle of the acfrequency, the phase tracking becomes impossible betweenthe detecting points, consequently, the fast trackingperformance cannot be achieved. In three-phase systems, thedq transform of the three-phase variables has the quadraturefeature, as the "synchronous d-q frame reference" SRF PLL[1], which can be used in various applications for thedetection of the phase or angular position. But the waveformsof the grid voltage may be the distorted with harmonics andunbalanced voltages, which could seriously affect theaccuracy of the obtained grid voltage information.

This paper firstly briefs the principle of the SRF-PLL,discusses the concept used for extracting fundamental positivesequence component [2] and the Software based PLL [3].Then the proposed PLL is introduced. The simulation studies

have been conducted. The performances of the proposed PLLhave been investigated and compared with the SRF-PLL andthe software based PLL systems.

II. SYNCHRONOUS REFERENCE FRAME (SRF)-PLL

The synchronous d-q reference frame PLL is a simple andstable three-phase PLL system which detects the phase anglein the synchronous d-q reference frame, the reference frame issynchronized to the input voltage frequency [1]. A blockdiagram of SRF-PLL is shown in Fig. 1.

V~

Vb~ |M|+

iffs

S

*0

-fFig. 1 Basic structure of SRF-PLL

The closed loop transfer function of this system can berepresented as a generalized second order system in (1):

(1)Hclose(S) = 2Gw(n s + tq9ns2 + 2 s+w 2

Where, K = 2 /o)E ,K=o2 Em, Ti==l/Kand Kp is the proportional gain and Ki is the integral gain ofthe PI controller, and Em is the magnitude of the input signal.Depending on the pre-conditioning applied on the signals,

the signal entering the system may be normalised or non-normalised. If the normalised PLL system is adopted by usingthe output of M , then the Em for the parameters of PI

controller may be taken as unity. Consequently, the PIcontroller parameters may not be affected by the variations ofinput utility voltage value.However, the measured waveform may be unbalanced with

negative and zero sequence components, the harmonics anddistortions could deteriorate the performance of the simpleSRF PLL system. Thus the conventional methods are notsufficient to cope with various distortions of the measuredvoltage signals.

1-4244-0783-4/07/$20.00 C 2007 IEEE 1702

Page 2: A Fast PLL Method for Power Electronic

III. FUNDAMENTAL POSITIVE SEQUENCECOMPONENT EXTRACTION FOR PLL SYSTEMS

Due to the poor performance of SRF-PLL under unbalancedor distorted conditions, various PLL systems have beenproposed to overcome the problem [2-5]. A basic concept isto extract the fundamental positive sequence component byprocessing the signal, and then to obtain the angle andfrequency of the fundamental positive sequence componentfor the operation and control ofpower conversion systems.The unbalanced three phase voltage may be expressed as (2)

basic structure of the software based PLL is shown in Fig. 2.In this PLL system, the three phase input voltage signals areconverted to o-P system. The o-P components can also beexpressed as their positive and negative components as

Va Vpa + Vna= Vpm cos(O + Op ) + Vnm cos(O +On)

V8= V p8+ Vn6= Pp/i ni

= pm sin(O+OSP) Vnm *sin(O+OSn)

(4)

Differentiating Eqn. (4) with respect to 0, to obtain

cos(cd+- +) cos( T + cos()

2 2~~~~~~~~~~2

Where vprn ~vnrn and v0 r denote the magnitudes of the

positive, negative and zero sequence terms respectively.The positive sequence component is extracted as an input of

the PLL system to eliminate the effects of unbalanced andharmonics. Reference [2] presented a d-q synchronous PLLsystem which produces phase angle and frequency locked topositive sequence components. The three positive sequencecomponents ( ve, ,avn,z) are related to three phase voltages

va (vbV ) by

avp a

[ 2

a a V

a- v

a2 1

2J Lv

- vI

(Vb-C- a _ A/ (b vc )2 a21i31

(Vap +vcp )1 1-v

a(VaVb)2 C .r2V (j

(3)

2fT

Where,a= + or a = e 32 2

It can be seen that a phase shift of 90 degree is required forall three phase components to extract the positive phasesequence components.

In reference [2], three all-pass filters are respectivelyapplied on three phase voltage signals to perform 90 degreephase shift. Then a second-order low-pass filter is added toreduce the effects of high-order harmonics. The extractedpositive sequence components are then fed into a SRF PLLwhich produces the phase angle locked to the positivesequence component.

IV. SOFTWARE BASED PLL

In reference [3], a software based PLL is proposed. The

dd Va = Vpi + Vn/

d(5)

d v = Vpa + V,a

By using (5) the positive sequence components in o-P framecan be calculated as shown in (6), where the derivative termsare calculated with numerical methods which is the main taskof the first stage in the reported software based PLL [2].

dvp = 0.5 (va + dS v , )

dv Pf O.5 (v, V~a)

d 0

(6)

The second stage transforms the o-P components of thepositive sequence to the rotating synchronous frame. Thequadrature axis component is then regulated by a PI controller.The second stage tracks the phase angles and angularvelocities ofthe positive and negative sequence components.The third stage is essentially a lead-lag compensator with

good filtering properties. In this stage, the parameter o- At iscalculated, filtered and fed back to the first stage.

..V aq_a oc-+vcdv- ,O

Ic- c 6 v13-_dv1 Vpg

AU~~ ~ ~~~~~1AO

, UA - _ Lead-Lag =k-_P Compnao S A9

Th71e thEk taggeFig.2 Basic structure of Software based PLL

Such a system can provide fast response to follow thesystem frequency variations and voltage magnitude variations.However, the derivative calculation could be sensitive tocertain types of waveform distortions, such as harmonics. Inthe following section, a PLL with the improving ability ofworking under distortion condition is proposed.

1703

Page 3: A Fast PLL Method for Power Electronic

Bode Diagram

V. TUE PROPOSED FAST PHASE DETECTINGMETHOD

A Basic structure of the proposed fast phase detectingmethod

The basic structure of the proposed fast phase detectingmethod is shown in Fig. 3, where two band pass filters areused as the conditioning part for the input signal in o-P frame.Also a phase locked loop for negative sequence component isestablished in the voltage detection system.

Fa aL( Badps7Flte.r

b-D _..B pso Filte

AS

sv1 -_dv13

pa

.1P#VIanV Frequency (rad/sec)

Fig.4 Band pass filter characteristics

f

C Negative phase angle calculationThe information about the negative phase component may

be used for control or power quality identification. Based on

equations (5) and (6), the negative phase component can becalculated as

d

Vn .5(v,, v,

Fig. 3 Structure ofthe proposed PLL

B Bandpass filterThe transfer function of the band-pass filters used in the

proposed PLL system may be expressed as

G (-)Y(s) = co

I + 2 ( s +() )2)c )c

(8)

Vn# = -0.5(V0 + d Va )

AI Therefore, with the phase shifted components, the negativecomponents in o-P frame can be found, then they can beconverted into the d-q frame in a similar way to the positivesequence component. The negative phase sequence angle andmagnitude can be obtained with the PLL as shown in Fig. 3.

VI. SIMULATION STUDY

Simulation studies have been performed to investigate theperformance of the proposed PLL system. In this section, thesimulation conditions and results are presented.

A Description ofthe test conditionsTwo tests are reported in this paper. Assuming the normal

positive sequence component voltage has a phase peak valueof 1000 V, and the utility voltage has balanced harmonicswhich can be formulated as follows:

Va =vl cos0+v5 cos50+v7 cos70+ *+v25 cos2502 2 2

Vb =V COS(- fZ)+V5COo5(0 -z)+v7 cos7O+.. +v25cos25(0--Z)3 3 3

2 2 2 2

V, =VI COS(O+-z)+V5 cos5(0+-zr)+v7 cos7(0+-zr)+. +v25 cos25(0+-z)3 3 3 3

(9)

(7)

Where ; is the damping ratio, 0) is the characteristic

frequency and G is the gain. In this study, the band pass filteris such designed,; is 0.5, ()O is 314.159 radians /s (50 Hz)and G is 1.0. The frequency characteristics of the filter are

plotted in Fig. 4.It can be seen that the filter can effectively attenuate signals

at frequencies other than the characteristic frequency wherethe signal has no phase shift.

The used harmonics components are as specified inEN50160 and scaled down to 8% THD. The harmonics lastfor the whole simulation period and their magnitudes have thesame dip in the percentage of the positive sequence

1704

V

Vb

Page 4: A Fast PLL Method for Power Electronic

components in Test 1. The other used test conditions aregiven in Table 1. The test waveforms are illustrated in Fig.5(a)-(d). Fig. 5 (a) shows a part of the three phase test voltagesignals in Test 1, Fig.5 (b)-(d) show three parts of the testsignals in Test 2 respectively, i.e. the first frequency ramping-down part, the frequency ramping-up part, and the secondfrequency ramping-down part.The output frequency is observed after a 2nd order low pass

filter with damping ratio of 0.707and characteristic frequencyof 10lHz.

B SRF-PLL performanceFig. 6 shows the tracked angle and the angle error of the

SRF-PLL under Test 1. It can be seen that the angle errorincreases dramatically to approximate ± 50 degrees duringthe period when the negative sequence components emerge.

Table 1 Some test conditionsTest Conditions

The positive sequence component voltage dip from 100% toTest 1 15% for 0.3s, during the same period, 15%, negative

__________ |sequence component present with a 30 degrees phase shiftThe frequency ramps down from 50.0Hz to 47.5Hz within

Test 2 0.25s, maintains at 47.5Hz for 0.3s, then it ramps up from47.5Hz to 51.5Hz within 0.4s, maintains at 51.5Hz for 0.2s,

|________ |and then ramps down from 51.5Hz to 50.0Hz within 0.15s

Fig.7 shows the voltage magnitude output of the SRF-PLL.The envelope of the magnitude curve reflects the signalmagnitude; however it is combined with harmonics.

Fig.8 shows the SRF-PLL test results under the second testcondition. The frequency output follows the referencefrequency ramps very well; the frequency error is in a rangeof about ± 0.0050. The negative sequence component cannot be detected with SRF-PLL.

C Software based PLL performanceThe results from the Software based PLL are presented in

Figs.9-12. Fig.9 shows the tracked positive sequence angleand angle error under Test 1. In the steady state the angleerror is in the range of-0.5 to 2 degrees in steady state.

Fig. 10 shows the tracked negative sequence angle and angleerror under Test 1. It can be seen that the angle error is nomore than 2 degrees.

Fig. 11 shows the positive and negative sequencecomponents magnitudes respectively. Compared with thereference magnitudes (in green), the voltage magnitudeoutputs of the software based PLL are always affected byharmonics. In particular the negative magnitude is influencedseriously by the harmonics.

Fig. 12 shows that the frequency output can follow thereference frequency ramps in Test 2 and the frequency error isin a range of about ± 0.015o%.D The performance ofthe proposed PLL

Figs. 13-17 show the results of the proposed PLL. Under theTest 1 condition, the tracked positive sequence angle and theangle error are shown in Fig. 13. In steady state the angle erroris in a range of -0.1 to 0.2 degrees. Fig. 14 presents thenegative sequence angle which have been tracked very well,and the steady state angle error is no more than 0.5 degrees. InTest 2, the frequency output can follow the reference

frequency ramps well. Particularly the steady state frequencyerror can be kept within 0.01o%.

The First Test Condition

Fig.5(a) A part of the three phase test voltage signals in Test 1.The Second Test Condition

1500i-1000 {iIlill

,5

0°. 25 0.3 0-35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.7

Fig.5(b) The first frequency ramping-down part in Test 2

The Second Test Condition15001

1000|

Soo

-1000

-150010.8 0.9 1 1.1 1.2 1.3 1.4

Fig.5(c) The frequency ramping-up part in Test 2

The Second Test Condition15001

0. .1

-1500 _ ----

1.4 1.45 1.5 1.55 1.6 1.65

Fig.5(d) The second frequency ramping-down part in Test 2

1705

1500

1000

0

.. ..

-1000 .............m

-1500.0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 O.Y-..7

75

1 .7

Page 5: A Fast PLL Method for Power Electronic

Locked Angle, SRF and Ref(rad.)

0.3 0.4 0.5 0.6 0.7 0.8

Angle error, Ref-SRF(deg.)

0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65

Fig. 10 Negative angle and angle error ofSoftware based PLL under Test 1

Positive Magnitude, Software based and RefI_1znn

0.3 0.4 0.5 0.6 0.7

Fig.6 Angle and angle error of SRF-PLL under Test 1

-VagstueSF adFe

0.8

.M u0 0

Fig.7 Magnitude of SRF-PLL unde~rTest 1 400

200 U

Frequency, SRF and Ref 0

0.3 0.4 0.5 0.6 0.7 o.

Negative Magnitude, Software based and Ref

02... 03II04 0507 08

0.2 0.3 0.4 0.5 0.6 0.7 0.8

Fig. 11 Positive and Negative magnitude of software based PLL in Test 1

Frequency, SoftwareBased and Ref

v 50

450.4 0.6 0.8

I5v- 50

1.2 1.4 1.6 1.8

0.010.4 0.6 0.8 1 1.2 1.4 1.6 1.8

0.005 _

-0.005

-0.010.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Fig.8 Frequency and frequency error of SRF-PLL under test 2

Locked Angle, SoftwareBased and Ref(rad.)

0.3 0.4 0.5 0.6

Angle error, Ref-SoftwareBased(deg.)

0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Fig. 12 Frequency and frequency error ofSoftware basedPLL under Test 2Locked Angle, Improved and Ref(rad.)

0.7 0.8

0.2 0.3 0.4 0.5 0.6

Angle error, Ref-Improved(deg.)

0.7 0

023

01~~~~~~~~~~~~~~~~~11

k l

0.2 0.3 0.4 0.5 0.6 0.7 0.

Fig. 13 Positive angle and angle error ofthe proposed PLL under Test 1

1706

-50.2

40

20

< -20

-40

-600.2

55

-500.2

21.

-1.50 10.2 0.3 0.4 0.5 0.6 0.7 0.8

Fig.9 Positive angle and angle error of Software based PLL under Test 1

Negative Angle, SoftwareBased and Ref(rad.)

0

0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7

1500

1000a

SS .,

4D5 ._

5

-5

.8

.8

).8

Page 6: A Fast PLL Method for Power Electronic

Fig. 14 Negative angle and angle error ofthe proposed PLL under Test 1

Positive Magnitude, Improved and Ref

1000 77- /

VII. CONCLUSION

A fast PLL has been proposed, where a band-pass filteris designed to make the system immune to distortedwaveforms, such as harmonic distortions. Therefore thesystem performance can be significantly improvedwithout sacrificing the responding speed.

Simulations under various conditions have beenconducted, including system voltage dips and frequencyvariations under distorted conditions. The comparisonswith the synchronous reference frame (SRF)-PLL and thesoftware based PLL has been made. The proposed PLLhas demonstrated significant improvements.The proposed PLL system can be used for the power

electronic interfaces of renewable energy and energystorage technologies, including wind energy conversionsystems and solar PV systems, etc.

> 600 REFERENCES

400

200

O _0.2

250

200

150

100 _

50 1,.

0.2Fig. 15 Positiv

55-

50-

[1]. S.-K. Chung "Phase-locked loop for grid-connected three-phasepower conversion systems", IEE Proceedings-Electric PowerApplications, Volume 147, Issue 3, May 2000 Page(s):213-219.

0.3 0.4 0.5 0.6 0.7 0.8 [2]. Sang-Joon Lee; Jun-Koo Kang; Seung-Ki Sul; A new phasedetecting method for power conversion systems considering

Negative Magnitude, Improved andRef distorted conditions in power system, Industry ApplicationsConference, 1999. Thirty-Fourth IAS Annual Meeting. ConferenceRecord of the 1999 IEEE, Volume 4, 3-7 Oct. 1999 Page(s):2167 -

2172 vol.4.[3]. S.R. Naidu, A.W Mascarenhas,.; D. A. Fernandes, "A software

phase locked loop for unbalanced and distorted utility conditions";International Conference on Power System Technology, PowerCon2004. Vol. 2, pp 999 -1004.

[4]. M. Karimi-Ghartemani, M.R. Iravani, "A method for03 0*4 0*5 0*6 0.7 0'8 synchronization of power electronic converters in polluted and

le and Negative magnitude ofproposed PLL under Test Ivariable-frequency environments", IEEE Transactions on Power

Frequency, Improved and Ref Systems, Volume 19, Issue 3, Aug. 2004 Page(s): 1263 - 1270.[5]. P. Rodriguez, R. Teodorescu, I. Candela, A. Timbus, M. Liserre, F.

Blaabjerg, "New Positive-sequence Voltage Detector for GridSynchronization of Power Converters under Faulty GridConditions", in Proc. IEEE Power Electronics Specialists 37thConference on, pp. 1942-1948, June 18-22, 2006.

0.4 0.6 0.8 1.2 1.4 1.6 1.8

.0104 0.6 0.8 1 1.2 1.4 1.6 1.8

Fig. 16 Frequency and frequency error ofthe proposed PLL under Test 2

1707

45

0.01 r

0.005

0 00

-0.005

Negative Angle, Improved and Ref(rad.)

0

L0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7