THE BEST PATH FROM IDEAS TO PRODUCTION SILICON ®THE BEST PATH FROM IDEAS TO PRODUCTION SILICON ®

A Difference Logic Formulationand SMT Solver for Timing-DrivenPlacement

Andrew MihalSMT 2013

Programmable Logic Devices

2

Performance

Programmability

ASICs

CPUs

PLDs

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

LUT

C = firmware configuration bit

a b c out0 0 00 0 10 1 0

0 1 11 0 01 0 11 1 0

1 1 1

CCCCCCCC

Lookup Table Fabric

3

Interconnect

4

LUT

LUT LUT

LUT

MU

X

MU

X

MU

X

MU

X

MU

X

MU

X

MU

X

MU

X

MU

X

MU

X

MU

X

MU

X

MU

X

MU

X

MU

X

MU

X

MU

X

MU

X

MU

X

Programming

5

Input: Circuit Netlist

Output: Config Bits Mapping

Programming

6

DetailedPlacement

Programming Toolchain

7

Synthesis

GlobalPlacement

DetailedPlacement

Routing

VerilogVHDL

Config

No Overlaps Congestion, Routability Timing

Detailed Placement

8

Fixing an Overlap

9

Everybody Shuffle

10

Steps Look Bad in Isolation

11

Problem space is too big– Components Sites– LUT Permutations– Multiple Routing Variations– Retiming– 3D Fabric with Transparent Latches

Optimization Goals– Timing– Congestion

Why not SAT?

12

SMT Formulation of Timing Constraints Practicality

– Domain-specific variable selection order– A*-style future cost clauses– Dynamic constraint generation

Solutions

13

Netlist Comps

Placement Variables

14

Fabr

ic S

ites

AexactlyOne

atMostOnevAXX

Placement Delays

15

A B C

E

D

F

Y

X

DBC

(vBX vCY) DBC = dXY

Timing Constraints

16

A B C

E

D

F

DBCDAB DCD

DBE

DEC

DEF

DFE

Path ConstraintABCD DAB + DBC + DCD ≤

ABECD DAB + DBE + DEC + DCD ≤

ABEF DAB + DBE + DEF ≤

FEF DFE + DEF ≤

FECD DFE + DEC + DCD ≤

0

17

A B C

E

D

F

DBCDAB DCD

DBE

DEC

DEF

DFE

Slack

ArrivalC

RequiredC

ArrivalC = max ( DAB + DBC,DAB + DBE + DEC,DFE + DEC)

RequiredC = min ( - DCD,...)

Static Timing Analysis

Arrival and Required Equations

18

A B C

E

D

F

DBCDAB DCD

DBE

DEC

DEF

DFE

ArrC = max( ArrB + DBC, ArrE + DEC)

ReqC = min (ReqD – DCD)

ArrC ≥ ArrB + DBC

ArrC ≥ ArrE + DEC

ReqC ≤ ReqD – DCD

Difference Logic Formulation

19

A B C

E

D

F

Y

X

DBC

(vBX vCY) (ArrC – ArrB ≥ dXY)

(ReqB – ReqC ≤ -dXY)

ArrN ≤ ReqN

Edge Placement Options

20

A B C

E

D

F

DBC

(vBX vCY) (…)

BC

Dynamic Constraint Generation

21

B

subspace where (¬VBX + ¬VCY + ...) is relevant

VBX

VCY

C (vBX vCY) (…)(vBX + vCY + …)

Components

Site

s 0 0 0 0 0 0 00000

00

1

Timeline

22

SimulatedAnnealing

DLFormulation

Pure BooleanEncoding

Custom SMTSolver

Arr / ReqNumber Line

E+1 = T

E-1 = F (Arr ≥ -1)

.

.

.

.

.

.

(Req < 1)

MiniSAT 1.12b+ dynamic clauses

Solver Flow Chart

23

select

propagate

done?

return

analyze

backtrack

conflict

Propagation Phase

24

propagate_b

propagate_dl

propagate_dyn

conflict

conflict

conflict

20%

1%

50%

ArrA d ReqB d ArrD – ArrC d

ReqC – ReqD -d

Batch DL Propagation

25

A

schedule fanout updates

B

schedule fanin updates

D

C

update fanins and fanouts

Tighter consistent bounds Or a conflict: ArrA > ReqA Or a positive-weight cycle

DL Propagation Results

26

Search-and-Repair Strategy

27

Select Window

BuildSMT Instance Custom

SMTSolver

Apply Solution

Select aProblem

Done?

Annealing vs. SAT and SAT vs. SMT

28

Annealing Boolean FormulationDesign LUTs Runtime Freq Runtime Freqcamellia256 89341 1.0 1.0 0.054 1.14

sudoku 17784 1.0 1.0 0.266 1.49

dct 17199 1.0 1.0 2.526 1.52

wishbone 12775 1.0 1.0 0.028 1.03

Boolean Formulation SMT FormulationDesign LUTs Runtime Freq Match Best Freqsha256 3283 1.0 1.0 0.71 1.01 1.03

aes 5236 1.0 1.0 0.57 0.79 1.03

r2000sc 5807 1.0 1.0 0.93 7.34 1.32

fpudouble 10300 1.0 1.0 0.38 0.48 1.05

SAT vs. SMT: Reduction in Problem Size

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Boolean Formulation SMT FormulationDesign LUTs Bvars Clauses Bvars DLvars Clausesmancala 287 146k 393k 13k 160 60k

rs_enc 1373 189k 59k 23k 467 55k

aeMB 3066 285k 233k 24k 411 81k

sha256 3283 283k 489k 28k 470 132k

aes 5236 233k 94k 29k 510 80k

warp 5560 283k 729k 24k 375 88k

r2000sc 5807 294k 238k 26k 398 86k

minimips 5855 231k 252k 27k 425 91k

fpudouble 10300 327k 126k 32k 327 78k

Results: Dynamic Clauses

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Boolean FormulationDynamic No Dynamic

Design LUTs Runtime Clauses Runtime Clausesmancala 287 1.0 393k 13.8 76590k

rs_enc 1352 1.0 59k 12.7 1029k

aeMB 3045 1.0 233k 8.7 20116k

SMT FormulationDynamic No Dynamic

Design LUTs Runtime Clauses Runtime Clausesmancala 287 0.40 60k 12.2 28545k

rs_enc 1352 0.30 55k 48.2 16487k

aeMB 3045 0.58 81k 15.7 20531k

First use of SMT for Place & Route Straightforward difference logic formulation Take advantage of natural subdivisions in the problem

space to make the system practical Deployed in a production placement tool at Tabula today More details on Thursday at 9:00

Summary

31