a design methodology to extend bandwidth for regulated ... · a design methodology to extend...

A design methodology toextend bandwidth forregulated cascodetransimpedance amplifier

Sheng Xie1a), Sicong Wu1, Luhong Mao1, and Haiou Li21 School of Microelectronics, Tianjin University,

Tianjin 300072, China2 Guangxi Key Laboratory of Precision Navigation Technology and Application,

Guilin University of Electronic Technology, Guilin, 541004, China

a) [email protected]

Abstract: This brief analyzes the performance of regulated cascode (RGC)

topology and develops a broadband transimpedance amplifier (TIA) incor-

porated with a novel dual shunt-feedback configuration. Compared to tradi-

tional RGC circuit, the proposed TIA improves the natural frequency and

optimizes the damping factor. Furthermore, the common source auxiliary

amplifier is replaced by an inverter amplifier to provide extra gain and reduce

the equivalent input noise current. Based on 0.18-µm CMOS technology,

a TIA with enhanced RGC structure was optimized and implemented, and

the fabricated chip was mounted on a Rogers 4003C printed circuit board.

The experimental results demonstrate a 5.2GHz bandwidth and a 60.5 dBΩ

transimpedance gain for 0.5 pF photodetector capacitance. The fluctuation of

group delay is less than 50 ps, and the measured average equivalent input

noise current density is about 14.99 pA/√Hz. The chip consumes 28.4mW

using 1.8V supply.

Keywords: transimpedance amplifier, regulated cascode, dual shunt-feed-

back, inverter, CMOS

Classification: Integrated circuits

References

[1] P. Lu, et al.: “Highly efficient data migration and backup for big dataapplications in elastic optical inter-data-center networks,” IEEE Netw. 29(2015) 36 (DOI: 10.1109/MNET.2015.7293303).

[2] R. Y. Chen and Z. Y. Yang: “CMOS transimpedance amplifier for gigabit-per-second optical wireless communications,” IEEE Trans. Circuits Syst. II, Exp.Briefs 63 (2016) 418 (DOI: 10.1109/TCSII.2015.2505264).

[3] I. Kwon, et al.: “A high-gain 1.75-GHz dual-inductor transimpedance amplifierwith gate noise suppression for fast radiation detection,” IEEE Trans. CircuitsSyst. II, Exp. Briefs 63 (2016) 356 (DOI: 10.1109/TCSII.2015.2503583).

[4] S. Chen, et al.: “A monolithically-integrated chip-to-chip optical link in bulkCMOS,” IEEE J. Solid-State Circuits 50 (2015) 828 (DOI: 10.1109/JSSC.2014.2382101).

© IEICE 2017DOI: 10.1587/elex.13.20161098Received November 7, 2016Accepted December 2, 2016Publicized December 20, 2016Copyedited January 25, 2017

1

LETTER IEICE Electronics Express, Vol.14, No.2, 1–12

http://dx.doi.org/10.1109/MNET.2015.7293303




http://dx.doi.org/10.1109/TCSII.2015.2505264








http://dx.doi.org/10.1109/JSSC.2014.2382101




[5] H. Y. Jung, et al.: “Design optimization of hybrid-integrated 20-Gbs opticalreceivers,” J. Semicond. Technol. Sci. 14 (2014) 443 (DOI: 10.5573/JSTS.2014.14.4.443).

[6] J. Lee, et al.: “A 6Gb/s low power transimpedance amplifier with inductorpeaking and gain control for 4-channel passive optical network in 0.13 µmCMOS,” J. Semicond. Technol. Sci. 15 (2015) 122 (DOI: 10.5573/JSTS.2015.15.1.122).

[7] M. Seifouri, et al.: “Design of broadband trans-impedance for opticalcommunication systems,” Microelectronics J. 46 (2015) 679 (DOI: 10.1016/j.mejo.2015.05.007).

[8] M. H. Taghavi, et al.: “On the use of multi-path inductorless TIAs for largertransimpedance limit,” Analog Integr. Circuits Signal Process. 77 (2013) 221(DOI: 10.1007/s10470-013-0140-9).

[9] Z. H. Lu, et al.: “An inductor-less broadband design technique fortransimpedance amplifiers,” Proc. IEEE ISIC (2009) 232.

[10] M. Atef, et al.: “8Gbits/s inductorless transimpedance amplifier in 90 nmCMOS technology,” Analog Integr. Circuits Signal Process. 79 (2014) 27(DOI: 10.1007/s10470-013-0242-4).

[11] M. Atef and H. Zimmermann: “Low-power 10Gb/s inductor-less inverterbased common-drain active feedback transimpedance amplifier in 40 nmCMOS,” Analog Integr. Circuits Signal Process. 76 (2013) 367 (DOI: 10.1007/s10470-013-0117-8).

[12] E. Säckinger: “The transimpedance limit,” IEEE Trans. Circuits Syst. I, Reg.Papers 57 (2010) 1848 (DOI: 10.1109/TCSI.2009.2037847).

[13] B. Razavi: Design of Integrated Circuits for Optical Communication (Chicago,McGraw-Hill, 2005) 1st ed. 8.

[14] S. B. Amid, et al.: “Fully differential, 40Gb/s regulated cascode transimpe-dance amplifier in 0.13 µm SiGe BiCMOS technology,” Proc. IEEE BCTM(2010) 33 (DOI: 10.1109/BIPOL.2010.5667977).

[15] L. L. Chen, et al.: “A 10-Gb/s CMOS differential transimpedance amplifier forparallel optical receiver,” Proc. IEEE ISSSE (2010) 345 (DOI: 10.1109/ISSSE.2010.5607130).

[16] Y. H. Kim, et al.: “Bandwidth enhancement technique for CMOS RGCtransimpedance amplifier,” Electron. Lett. 50 (2014) 882 (DOI: 10.1049/el.2014.0612).

1 Introduction

With the rapid development of the Internet of Things (IoT), cloud computing, and

mobile Internet, the data volume grows dramatically, and high-speed information

communicate between board-to-board, chip-to-chip and on-chip has become nec-

essary [1, 2]. However, due to the bottleneck effect, traditional electrical inter-

connect is difficult to solve the problem. As an alternative solution, optical

interconnection was proposed and became the hot issues in the field of optoelec-

tronic integration [3, 4].

As the first active building block in optical receiver link, transimpedance

amplifier (TIA) directly determines the whole performance, such as sensitivity,

speed, and dynamic range [5]. Therefore, the design of TIA is one of critical steps

to realize the high-performance optical interconnection system. To meet the

requirements of low cost, high integration, and high manufacturability, TIAs based


2

IEICE Electronics Express, Vol.14, No.2, 1–12

http://dx.doi.org/10.5573/JSTS.2014.14.4.443












http://dx.doi.org/10.1016/j.mejo.2015.05.007







http://dx.doi.org/10.1007/s10470-013-0140-9

http://dx.doi.org/10.1007/s10470-013-0140-9

http://dx.doi.org/10.1007/s10470-013-0242-4

http://dx.doi.org/10.1007/s10470-013-0242-4

http://dx.doi.org/10.1007/s10470-013-0117-8

http://dx.doi.org/10.1007/s10470-013-0117-8

http://dx.doi.org/10.1007/s10470-013-0117-8

http://dx.doi.org/10.1109/TCSI.2009.2037847




http://dx.doi.org/10.1109/BIPOL.2010.5667977




http://dx.doi.org/10.1109/ISSSE.2010.5607130




http://dx.doi.org/10.1049/el.2014.0612

http://dx.doi.org/10.1049/el.2014.0612

http://dx.doi.org/10.1049/el.2014.0612

http://dx.doi.org/10.1049/el.2014.0612

on CMOS technology have been actively investigated in the past decade. Due to the

features of wide bandwidth and low power consumption, TIAs with regulated

cascode (RGC) topology are widely explored in broadband optical receiver system

[6, 7, 8, 9, 10, 11]. Nevertheless, the input impedance of conventional RGC TIA

needs to be further modified to provide enough bandwidth. Up to now, numerous

approaches to achieving wide bandwidth have been proposed, such as series

inductor peaking [6], T-matching network [7], multi-path TIAs [8], and capacitive

degeneration technique [9]. Yet, wide-band obtained by these techniques is at the

expense of large chip area or/and gain reduction. Besides, along with the scale-

down of CMOS technology, designers began to use advanced technology to

improve the performance of TIA [10, 11]. However, there still have many prob-

lems, such as high cost, large leakage current, and constrained circuit structure

caused by low supply voltage.

To relax the input parasitic effects affecting the bandwidth for Gigabit class

links, the RGC input stage needs to be further enhanced. In this brief, we exploit a

novel dual shunt-feedback structure to isolate the large photodetector (PD) capaci-

tance and enhance the bandwidth of RGC circuit. Furthermore, the common source

(CS) auxiliary amplifier is replaced by an inverter amplifier to compensate the gain

reduction and reduce the input noise current.

In Section 2, the proposed structure is discussed in detail, including aspects of

bandwidth, gain, and noise. Section 3 presents the building blocks of the proposed

TIA. In Section 4 the measurement results are presented and analyzed. And finally

the conclusion is given in Section 5.

2 Circuit design and analysis

2.1 Conventional RGC structure

As show in Fig. 1(a), the conventional RGC topology is combined by a common

gate (CG) main amplifier and a CS auxiliary amplifier. Due to the active feedback

network formed by M2 and R2, the input resistance of RGC circuit is smaller than

the CG amplifier, so the bandwidth is extended. To simulate the PD’s behavior, the

input node is connected with a capacitance (Cpd ¼ 0:5 pF) and an AC current

source (Ipd).

Fig. 1. Schematic of (a) conventional RGC circuit; (b) the enhancedRGC circuit


3


Neglecting the body-effect of transistor M2 and the channel length modulation

of transistor M1 and M2, the input resistance of RGC topology can be found easily

as

Rin ¼ R1

1 þ GM2R1ðGM1R3 þ 1Þ ð1Þ

where GM1 and GM2 are the transconductance values of M1 and M2, respectively.

Compared to other part, the gate-drain capacitance (Cgd2) of M2 is negligible, the

transfer function of RGC topology in Fig. 1(a) can be derived by

ACðsÞ ¼ VO

IPDðsÞ ¼ GM2R2ðGM1R3 þ 1Þ

CfCiR3

1

s2 þ 2�!ns þ !2n

ð2Þ

where the damping factor ¦ and the natural frequency !n, which determine the

bandwidth of RGC topology, can be expressed as

� ¼ R1R3CfGM1 þ CiR1 þ CfR3 þ CfR1

2ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiCfCiR3R1½1 þ GM2R1 þ GM1GM2R1R3�

p ð3Þ

!n ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1 þ GM2R1 þ GM1GM2R1R3

CfCiR3R1

rð4Þ

where, Ci ¼ Cpd þ Cpad þ CESD þ Cgs1, Cpd is the PD capacitance, Cpad and CESD

are respectively the parasitic capacitances of bonding pad and electro-static

discharge circuit, Cgs1 is the gate-source capacitance of M1. Cf ¼ Cgs2 þ Cgd1, Cgs2

is the gate-source capacitance of M2, Cgd1 is the gate-drain capacitance of M1.

According to (2), the low-frequency transimpedance gain of the RGC is given by

ACð0Þ ¼ VO

IPDðsÞ ¼ R2 1 � 1

1 þ GM2R1ðGM1R3 þ 1Þ� �

ð5Þ

Since there is only a single-loop feedback, the input transistor (M2) would

operate in linear region when the input current experiences a large variation, which

introduces much nonlinearity. Since equation (2) is a typical second-order system,

the values of R1, R3 or/and GM2 should be increased to obtain the Butterworth

response [12], but it would affect the bias conditions and deteriorate the linearity

performance of RGC circuit.

2.2 Dual shunt-feedback structure

To solve the above problems, a novel RGC topology is proposed, as shown in

Fig. 1(b). A local feedback stage, consisting of Rf , M3 and IS, has been added in

conventional RGC circuit. This dual shunt-feedback structure not only enhances the

dynamic range of input current, but also makes the input node more virtual ground,

which means that the modified circuit is more stable and the input resistance

becomes smaller than before. Moreover, the feedback stage can also raise the

natural frequency and optimize the damping factor.

Since the source follower (SF) composed of transistor M3 and current source ISapproximately has a unity voltage gain, the feedback resistor Rf can be regarded as

a direct connection between the feedback signal input and output in the AC

analysis. The input resistance of the proposed RGC topology is about© IEICE 2017DOI: 10.1587/elex.13.20161098Received November 7, 2016Accepted December 2, 2016Publicized December 20, 2016Copyedited January 25, 2017

4


RinE ¼ R1ðR3 þ RfÞRf þ R1 þ R3 þ GM2R1Rf þ GM1R1R3 þ GM2GM1R1R3Rf

ð6Þ

As above, neglecting the effect of the gate-drain capacitance (Cgd2) of M2, the

transfer function of enhanced RGC circuit can be derived as

ACEðsÞ ¼ VO

IPDðsÞ ¼ GM2R2ðGM1R3 þ 1Þ

CfCiR3

1

s2 þ 2�E!nEs þ !2nE

ð7Þ

where

�E ¼ R1R3CfRfGM1 þ CiRfR1 þ CfRfR3 þ CfR1Rf þ R3R1Ci

2ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiCfCiR3RfR1½Rf þ R1 þ R3 þ GM1R1R3 þ GM2R1Rf þ GM1GM2R1R3Rf�

pð8Þ

!nE ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiRf þ R1 þ R3 þ GM1R1R3 þ GM2R1Rf þ GM1GM2R1R3Rf

CfCiR3RfR1

rð9Þ

Comparing (9) with (4), we can obviously find that the numerator of the natural

frequency !nE is added with a term of [ðR1 þ R3 þ GM1R1R3Þ=Rf ]. Suppose all

other conditions to be the same for both topologies except for Rf , the pole

frequency of the enhanced RGC, which equals to !nE when �E � 1 [12], must

be higher than that without Rf . The relationship between Rf and the pole of

enhanced RGC is shown in Fig. 2, where Rf increases in the direction of arrows.

As can be seen, both the real part and the absolute of imaginary part of the two

complex conjugate poles increase with increasing Rf , and the pole frequency is

always higher than that of conventional RGC circuit. Although the poles derived

from (7) have a little deviation from the results of HSPICE simulation, it still

confirms our circuit analysis and design procedure.

Fig. 3 shows the variation of damping factor �2E with Rf based on (8). The

damping factor �E gradually approaches 1=p2 as Rf increases, so the introduction

of Rf is beneficial to achieve a maximally flat frequency response. In practice,

considering the effects of other high frequency poles of the circuit, the desired value

of �E is usually less than 1=p2 for Butterworth response. The inset in Fig. 3 shows

the normalized frequency response based on (9). The results show that the

bandwidth of the enhanced RGC is significantly improved with increasing Rf in

a certain extent.

Fig. 2. Rf versus poles of the enhanced RGC circuit (arrows show thedirection of increasing Rf )


5


Combining Fig. 2 with Fig. 3, we can obtain the following results: when Rf is

small, the pole frequency can reach a maximum and �E > 1=p2, which leads to

a severe high frequency attenuation before reaching the pole frequency, so a

low −3 dB bandwidth is created. When Rf is large, a low pole frequency and

�E < 1=p2 result in a greater gain ripple near the poles and reduce the loop

stability. Therefore, to obtain maximum bandwidth and best flatness, an appropriate

value of Rf should be selected.

2.3 TIA input stage implementation

As we know, it is an important way to improve the performance of RGC by

boosting the auxiliary amplifier gain, which has a significant effect on the RGC gain

and noise performance. Therefore, the CS auxiliary amplifier in Fig. 1(a) is

replaced by an inverter amplifier, as shown in Fig. 4. Although the RGC with an

inverter auxiliary amplifier has been reported in 40-nm CMOS technology [11], it is

not suitable to the 0.18-µm CMOS technology platform due to the different supply

voltage. To insure the transistor M5 operates in the saturation region and has a

proper gate voltage, a SF, consisting of a PMOS transistorM4 and the resistor R4, is

introduced (like a high-pass filter). Through reusing the bias current, the auxiliary

amplifier gain is boosted without consuming extra power.

Fig. 3. The simulation of Rf versus �2E (the insert shows the frequencyresponse with different Rf )

Fig. 4. Schematic of the proposed TIA input stage


6


Since the voltage gain of the SF is about unity, so we ignore the effects of M4

and R4 in the AC analysis. Neglecting the gate-drain capacitance (Cgd2) of M2, the

complete transfer function of the proposed TIA input stage can be expressed as

ACE allðsÞ ¼ VO

IPDðsÞ ¼ GM2R1RfR2ððGM1 þ GM5ÞRO þ 1Þ

As2 þ Bs þ Dð10Þ

where,

A ¼ CfCiROR1Rf ;

B ¼ R1RORfCfðGM1 þ GM5Þ þ CiRfR1 þ CfRORf þ CfR1Rf þ ROR1Ci;

D ¼ Rf þ R1 þ RO þ GM2R1Rf þ ðGM1 þ GM5ÞR1RO þ GM2ðGM1 þ GM5ÞR1RORf ;

RO ¼ RM1RM5=ðRM1 þ RM5Þ;RM1 and RM5 are respectively the channel length modulation resistance of M1 and

M5, and GM5 represents the transconductance of M5. The low-frequency transi-

mpedance can be obtained from (10) and written as

ACE allð0Þ ¼ R2R1GM2ð1 þ AinvÞ

RO þ R1ð1 þ AinvÞRf

þ 1 þ GM2R1ð1 þ AinvÞð11Þ

where, Ainv ¼ ðGM1 þ GM5ÞRO. Comparing (11) with (5), the low-frequency tran-

simpedance of conventional RGC is reduced by Rf , resulting from the denominator

of (11) increased a term of [ðR1 þ RO þ R1AinvÞ=Rf ]. Since the voltage gain of the

inverter amplifier is much higher than the gain of the CS amplifier, the proposed

TIA input stage could be compensated for the reduced gain caused by Rf . The

calculated frequency response is shown Fig. 5. The −3 dB bandwidth enhancement

is from 4GHz to 6GHz while maintaining almost the same transimpedance gain.

2.4 Noise analysis

Since the proposed circuit operates in gigabit-per-second optical interconnection

link, the flicker noise is neglected, and only the thermal noise of resistance and the

channel thermal noise of MOS transistor are considered. Due to the large input

Fig. 5. Frequency response of the conventional RGC and the proposedTIA input stage


7


resistance and the small output load, the effect of the SF stage on noise analysis can

also be ignored [13]. Thus, the small-signal circuit model for noise analysis of the

proposed TIA input stage can be described as in Fig. 6.

Assuming all the noise sources are independent, and satisfy the theory of linear

superposition, the output noise voltage can be initially evaluated from Fig. 6, then

the equivalent input noise current can be derived from I2n inE ¼ V2n out=A

2CE allðsÞ,

and can be described as follow

I2n inE ¼ 4kT

R1þ 4kT

Rf

ROðsCiR1 þ 1ÞR1ððGM1 þ GM5ÞRO þ 1Þ þ 1

� �2

þ 4kT�GM2R2

ACE allðsÞ � 1

� �2

þ 4kT

R2

R2

ACE allðsÞ� �2

þ 4kT�ðGM1 þ GM5Þ ROðsCiR1 þ 1ÞR1ððGM1 þ GM5ÞRO þ 1Þ

� �2

ð12Þ

where k is the Boltzmann constant, T is the absolute temperature, £ is the noise

factor of the MOSFET and ACE allðsÞ is the transimpedance gain of proposed TIA

input stage. From the Fig. 1(a), we can also derive the equivalent input noise

current spectral density of conventional RGC as follow.

I2n in ¼4kT

R1þ 4kT�GM1

R3ðsCiR1 þ 1ÞR1ðGM1R3 þ 1Þ

� �2

þ 4kT

R2

R2

ACðsÞ� �2

þ 4kT�GM2R2

ACðsÞ � 1

� �2

ð13Þ

Comparing (13) with (12), the input-referred noise of the proposed RGC has a

slight increase at low frequency, resulted from the feedback resistor Rf , but it has

almost the same values at high frequency because ACE allðsÞ is far more than ACðsÞ,as shown in Fig. 5, and ROðsCiR1 þ 1Þ=ðROR1ðGM1 þ GM5Þ þ R1) is much less than

unity due to R1ðGM1 þ GM5Þ � 1. For RM5 � R3, the noise level of the proposed

TIA input stage is also reduced by increasing the load (RO) of auxiliary amplifier.

The simulation results of equivalent input noise current density spectrum of the two

circuits are shown in Fig. 7. As can be seen, the equivalent input noise current

density of the proposed TIA input stage is only a little more than that of conven-

tional RGC. Within the interesting bandwidth, the average noise current density of

the proposed RGC is about 12.59 pA/pHz.

Fig. 6. Small-signal circuit model of the proposed TIA input stage fornoise analysis


8


3 TIA circuit implementation

To suppress common-mode noise from power supply and substrate, and ensure the

electrical properties of input stage [14], a TIA circuit incorporating the proposed

dual shunt-feedback configuration is presented, and a simple PD model is included,

as shown in Fig. 8. A CS amplifier is inserted between TIA input stage and output

buffer to enhance the reverse isolation (S12). Additionally, the CS amplifier can also

eliminate the low-frequency pole introduced by the inter-stage parasitic capaci-

tance. In Section II, we ignored the gate-drain capacitor Cgd2 in analyzing the

transfer function of RGC input stage. In fact, when the proposed input stage is

connected to the following stage (like buffer or limiting amplifier), the low-

frequency pole might be introduced at the output node due to high resistance

and parasitic capacitance, thus reducing the overall bandwidth. To eliminate this

low-frequency pole, the capacitive degeneration technique was used in CS ampli-

fier [13].

To enlarge the driving capability of signals from the TIA for addressing the

testing instruments load of 50Ω, an output buffer is included in our implementa-

tion. The passive inductors, LA and LB, are added to form a ³-matching network,

which alleviates the bandwidth limitation of output buffer. Once subsequent circuit

Fig. 7. The simulation results of equivalent input noise current spectraldensity of the conventional RGC and the proposed TIA inputstage

Fig. 8. The TIA circuit architecture


9


blocks are integrated together with the TIA, the buffer and the inductors ðLA; LBÞwould not be needed.

4 Chip fabrication and measurement results

As a proof of concept, the proposed circuit was implemented in 0.18-µm CMOS

technology (fT ¼ 30GHz) with an on-chip MIM capacitor of Cpd ¼ 0:5 pF which

used to mimic the effect of the PD capacitance. Fig. 9 shows the chip microphoto-

graph, where the core area of TIA is only 0.036mm2. The chip is mounted on a

Rogers 4003C printed-circuit board with 50Ω transmission lines for measurement,

it draws a current of 15.78mA from 1.8V supply.

S-parameters measurement with single-ended is shown in Fig. 10 by using

Agilent E5071C vector network analyzer, where the unused ports are terminated at

50Ω. The input reflection coefficient (S11) and the return loss (S22) are less than

−10 dB in the frequencies below 5.5GHz, which mean the input/output network

matches quite well. The transimpedance gain derived from the measured S-

parameters is also shown in Fig. 10. A −3 dB bandwidth of 5.2GHz with a

transimpedance of 54.5 dBΩ can be achieved. The transimpedance rolls off to

the −3 dB bandwidth with less than 2 dB in-band ripple. Considering the differ-

ential structure of the proposed TIA, an extra 6 dB should be added to the single-

ended gain, the actual transimpedance gain should be 60.5 dBΩ.

The phase response and group-delay variation are shown in Fig. 11. The whole

measured group-delay variation is about 50 ps over the −3 dB bandwidth.

Fig. 9. Chip microphotograph of the proposed differential TIA

Fig. 10. Measured S-parameters and calculated transimpedance gain ofTIA


10


The output integrated noise measured by Agilent DSA-K 93204A oscilloscope

is shown in Fig. 12 [2, 14]. The measured output noise voltage is 0.431mVpp. After

subtracting the background noise of 0.322mVpp contributed by the oscilloscope,

the calculated input referred noise current density is equal to 14.99 pA/pHz.

A 231-1 pseudorandom bit sequence (PRBS) is generated from Agilent

M8041B pulse pattern generator, and the eye diagram demonstrated using Agilent

DSA-K 93204A oscilloscope. The measured eye diagrams for data rate of 5Gb/s

and 7.5Gb/s with different input current swing are shown in Fig. 13. The TIA

takes on good eye-opening and thinner eyelids, and the whole eye diagram is clear

Fig. 11. Measured group delay and phase response

Fig. 12. Output integrated noise voltage

Fig. 13. Differential electrical eye diagrams (a) input swing of250 µAp-p at 5Gb/s (b) input swing of 350 µAp-p at 5Gb/s(c) input swing of 250 µAp-p at 7.5Gb/s (d) input swing of350 µAp-p at 7.5Gb/s


11


and symmetrical. Based on the measurements, the maximum output swing of the

TIA is about 200mVP-P. The estimated sensitivity of the proposed TIA for bit error

rate (BER) of 10�12 is 15.13 µA for 7.5Gb/s operation by extrapolation using the

Q function [13, 15].

A performance summary of the present TIA and comparison with previously

published works are shown in Table I. Obviously, the proposed TIA can achieve

high gain, wide-band and high electrical sensitivity simultaneously.

5 Conclusion

In this brief, a dual shunt-feedback topology based on conventional RGC has been

proposed for enhancing bandwidth and implemented in 0.18-µm CMOS technol-

ogy. The TIA shows a good eye performance up to 7.5Gb/s with −3 dB bandwidth

of 5.2GHz. By adopting an inverter as the auxiliary amplifier, the transimpedance

gain can be up to 60.5 dBΩ, and the equivalent input noise current density is about

14.99 pA/pHz. Considering the effects of parasitic capacitance and the bonding

wire of PCB, there is a little different between the experimental results and the

simulation results, but it still confirm the feasibility of the design of the proposed

circuit.

Acknowledgments

The authors would like to thank Keysight opening laboratory for providing the

laboratory facilities which made this work possible. This work was supported in

part by the National Natural Science Foundation of China under Grant

No. 61474081, and in part by Guangxi Key laboratory of precision Navigation

Technology and application, Guilin University of Electronic Technology under

Grant No. DH201513.

Table I. Comparison of the proposed RGC TIA performance withother works

Parameter Ref. [10] Ref. [15] Ref. [16] This work

Technology CMOS/nm 90 180 180 180

Cpd/pF 0.3 0.5 0.5 0.5

Gain/dB³ 63.5 50 56.7 60.5

Speed/Gbps 8 10 - 7.5

Bandwidth/GHz 6 7 5 5.2

Power dissipation (mW) 12 29.2 27.2 28.4

Input noise current 2µArms 29.9 pA/pHz - 14.99 pA/

pHz

Sensitivity at BER ¼ 10�12 −16 dBm 35µA - 15.13 µA

Area/mm2 0.46 0.023 - 0.036 (Core)

Input stage with inductor No No Yes No

Single or Differential Differential Differential Single Differential


12


a design methodology to extend bandwidth for regulated ... · a design methodology to extend...

Documents