A DC–5 GHz NMOSFET SPDT T/R switch in 0.25-mmSiGe BiCMOS technology

Paolo Crippa, Simone Orcioni*, Francesco Ricciardi, Claudio TurchettiDEIT—Dipartimento di Elettronica, Intelligenza Artificiale e Telecomunicazioni,

Universita Politecnica delle Marche, Via Brecce Bianche, I-60131 Ancona, Italy

Abstract

In this paper, the design of a fully integrated DC–5 GHz NMOS single-pole double throw (SPDT) transmit/receive (T/R)

switch for radio-frequency (RF) applications in a 0.25-mm SiGe BiCMOS/RFCMOS technology, is presented. The switch

insertion loss is <1.4 dB, the isolation is >30.1 dB, all over the 0–5 GHz band, and the return loss is >19.9 dB in the 0.8–1 GHz

band and is >10.2 dB in the 0–0.8 GHz and 1–5 GHz bands.

# 2003 Elsevier B.V. All rights reserved.

PACS: 85.40.-e; 85.40.Bh; 84.32.Dd

Keywords: CMOS; RF; SiGe; SPDT; T/R switch

1. Introduction

At present, the dramatic growth of the market of the

wireless and wireline communication systems is put-

ting an increasing pressure on industry to fabricate

low-cost radio-frequency (RF) front-ends. Addition-

ally, the performance requirements of these systems

are steadily increasing as the demand for extremely

large Tx/Rx bandwidth is forcing to use higher and

higher frequency bands. Thus, for those RF front-ends

that adopt time-division duplexing (TDD), high-qual-

ity transmit/receive (T/R) switches are key building

blocks.

In this paper, we describe a fully integrated, 0.25-

mm NMOS single-pole double throw (SPDT) T/R

switch design, for multi-standard/multi-frequency

RF applications working on DC–5 GHz band. This

entirely MOSFET-based SPDT switch uses no inte-

grated inductors thus allowing small die area con-

sumption. In order to make possible the integration of

the switch in a single-chip RF transceiver, it has been

designed in the latest 0.25-mm SiGe RFCMOS process

(i.e. by using the MOS transistors available within the

BiCMOS technology) that is well-suited for low cost,

high volume products. This technology marries the

advantages of silicon–germanium (speed, low noise,

low power consumption) with the CMOS state-of-the-

art in large volume fabrication systems [1]. This

technology offers high-frequency n–p–n bipolar tran-

sistors with fT ¼ 70 GHz and fMAX ¼ 90 GHz, high-

voltage n–p–n bipolar transistors, lateral and vertical

p–n–p transistors, 1.4 kO=& and 50 O=& resistors,

varactor diodes, electrostatic discharge diodes (ESD),

MIM and MOS capacitors, and MOS transistors with

minimum channel length of 0.25 mm. This SPDT

switch, which uses a 3 V power supply, 0–3 V control

Applied Surface Science 224 (2004) 434–438

* Corresponding author. Tel.: þ39-071-220-4543;

fax: þ39-071-220-4835.

E-mail address: sim@ea.univpm.it (S. Orcioni).

0169-4332/$ – see front matter # 2003 Elsevier B.V. All rights reserved.

doi:10.1016/j.apsusc.2003.09.020

voltages, and a 1.6 V of bias voltage, extends all over

the 0–5 GHz band the performances that are usually

achievable only by narrow-band 0.8–1 GHz MOSFET-

based switches.

2. Device design and optimization

Even if bipolar devices are generally faster than

MOS transistors, due to the requirements of a sub-

stantially symmetrical behavior and a high degree of

linearity, NMOSFETs have been chosen as active

devices to implement the SPDT RF T/R switch.

Recent works report narrow-band SPDT switches that

use integrated inductors to improve their impedance

matching and hence their performance. This technique

is not possible in our design, due to the DC–5 GHz

operating frequency range, thus only resistors and

NMOSFETs are used.

Fig. 1 reports the circuit schematic of the switch.

MOS transistors M1 and M2 are used to connect one of

the two unidirectional branches (Tx or Rx) to the

common, bidirectional branch (which we call, for

simplicity, Comm) and to disconnect at the same time

the other unidirectional terminal thus performing the

main switching function. All the MOSFETs are used

as pass-transistors. The control voltage V1 and its

logical complement V2 are used to drive the gates

of the all four MOSFETs. When the switch has a low

insertion loss state between Tx and Comm ports, V1 is

set to 3 V and V2 is set to 0 V. These voltages are

reversed to create a low loss path from the Comm to the

Rx port. The shunt transistors M3 and M4 are used to

improve the isolation of the switch by grounding RF

signals on the side that is turned off. The DC voltage at

all terminals is assumed to be 1:6 V, while the bias

circuit is omitted for simplicity.

The device parameters have been optimized to meet

these goals. The MOSFET’s sizes have been chosen to

obtain high isolation while also maintaining good

values for both the insertion loss and return loss all

over the DC–5 GHz band.

The simplest qualitative approximation for the pass-

transistors in the on-state is an RC network constituted

by a resistor RON and by parasitic capacitances. The

transistor parasitic capacitances CGS, CGD, CDB, and

CSB, shorting the terminals to ground, degrade the per-

formance as frequency raises. A simple method to

partially avoid this negative effect, which acts on CGS

and CGD only, consists of isolating the gate of each

MOSFET from ground by placing a high-valued

impedance (resistor) between the gate and the control

signals. Additionally, the series of the two parasitic

capacitances also slightly improves the insertion loss

bypassing the RON (the admittance 1/RON is quite higher

than the module of the admittances of these parasitic

capacitances).

The sizes of NMOSFETs have been optimized by

considering that increasing the channel width reduces

RON (insertion loss decreases) and increases the capa-

citance coupling to the substrate (insertion loss increa-

ses) by means of CDB and CSB and vice versa [2].

The trade-off results in an aspect ratio of W/L ¼143:7/0.25 mm/mm for the multi-fingered series MOS-

FETs M1 and M2, and in an aspect ratio of W/L ¼ 40/

0.25 mm/mm for the shunt MOSFETs M3 and M4.

2.1. Design at layout level

At the layout level, several test prototypes have

been created, trying not to introduce additional signal-

to-ground parasitic capacitances. In the final layout,

the signals do not travel on excessively wide metal

areas (except the pad), and only top metal layers

(metal4 and metal5) have been used. Additionally,

some metal lines have been shielded from ground in

order to minimize parasitic capacitance to substrate.

We used a 3 V power supply to increase the maximum

voltage swing of the signal: in the best case, if there is

no DC signal component and 0–3 V control voltages

are used, the peak-to-peak input signal can be as high

as 2.5 dB.

M1 M2

M3M4

G1R G2R

G3RG4R

Tx Rx

1V 2V

Comm

Fig. 1. Simplified circuit schematic of the SPDT T/R switch.

P. Crippa et al. / Applied Surface Science 224 (2004) 434–438 435

Fig. 2. Circuit layout (including pads and ESD devices) of the SPDT T/R switch.

Fig. 3. Simulated performances (isolation, return loss, and insertion loss) for the SPDT T/R switch.

436 P. Crippa et al. / Applied Surface Science 224 (2004) 434–438

The Momentum electromagnetic simulator has

been used to analyze the effects of the substrate finite

admittance to ground: there is a non-zero impedance

between substrate and ground. This did not seem to

affect insertion loss, as a higher impedance to ground

in series to the signal-to-substrate parasitics is useful

in this circuit. Only the isolation is degraded by these

parasitics: in fact an ideal isolator would connect the

isolated branch directly to ground, but this is not the

case due to substrate non-ideality.

As a final step, the pad effects (also including the

ESD structures) have been taken into account and

investigated. At the layout level, the pads introduce

large parasitic capacitances: the post-layout simula-

tion has shown a significant performance degradation.

The parasitics have been probed to detect the cause of

the performance drop; it was found that the signal-to-

ground capacitances introduced by the pads were

responsible for it. As a consequence, multiple changes

to the original structure of the signal pads have been

introduced to drastically reduce the signal-to-ground

capacitive coupling: the metal1 shield between the pad

plate and the substrate has been connected to ground

with a 10 kO resistor in order to decrease the signal-to-

ground admittance. These improvements increase the

return loss of 1–1.5 dB; very small improvements have

affected the insertion loss.

The extraction of the ESD diode parasitic capaci-

tances and their inclusion in the post-layout simulation

caused a dramatic performance degradation. The

reduction of both the area and the perimeter of the

diodes has demonstrated to be the only effective way

to solve (at least partially) this problem.

To improve performance a double-well structure

has been used to contain the two switching MOSFETs

M1 and M2, improving their isolation from the sub-

strate. Thus, all the connections to the power supply

and to ground are done through resistors having high

resistance values, to reduce the impact of the parasitic

capacitances associated to the double well. Fig. 2

shows the final layout.

3. Performance description

Using a 0.25-mm single-poly, five-metal SiGe

BiCMOS/RFCMOS technology, 3 V supply, and

0–3 V control voltages, post-layout simulation results

(including the pads and the parasitic components) are

shown in Fig. 3 where isolation, return loss, and

insertion loss of the SPDT T/R switch are reported

as functions of the frequency.

In the DC–2 GHz frequency range, the isolation is

>37.8 dB, the return loss is >16.5 dB, and the inser-

tion loss is <0.96 dB. Although the performances

are degraded at very high frequency, good values

are achieved all over the DC–5GHz frequency

range. These performances are comparable or even

better than those of GaAs SPDT switches or, also,

than those of narrow-band CMOS SPDT switches

[3–5,2].

The achieved performances of the SPDT T/R switch

are summarized below.

Isolation: >30.1 dB (full band).

Return loss: >19.9 dB (@ 0.8–1 GHz).

Return loss: >10.2 dB (@ 0–0.8, and 1–5 GHz).

Insertion loss: <1.4 dB (full band).

4. Conclusions

An NMOS SPDT T/R switch, for multi-standard

multi-frequency RF front-ends operating in the 0–5

GHz frequency range, has been designed and inves-

tigated using a 0.25-mm SiGe BiCMOS/RFCMOS

process. It exhibits a 37:8 dB isolation, a 16:5 dB

return loss, and a 0:92 dB insertion loss at 2 GHz.

Up to 5 GHz isolation is >30.1 dB, return loss is

>10.2 dB, and insertion loss is <1.4 dB.

Acknowledgements

This work was partially supported by Thales Com-

munications S.p.A.

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