ACPUFOR EASYTECHNOLOGY MIGRATION

Dr.RichardHerveille3rd RISC-VWorkshop

Roa Logic

• Privatelyheldandfinancedconsultancyfirm• SpecializedincustomIPandFPGAmigrations• Incorporatedin2014• Strongindustrybasis– FoundedbyoneoftheoriginalOpenCores members– EngagedinFPGAmigrationssince2003.– Largelyacademicteam

FreedomofDesign• Differenthardwareplatformsaresuitedfordifferent

needs– FPGAs:prototyping,lowvolume,noNRE,fastTTM– PlatformASIC:highperformance,lowpower,fastTTM– Std.cell ASICs:highestperformance,lowestpower,lowestunit

price• Marketconditionsdictatefreelymigratingbetweenthese

technologiesishighlydesirable– E.g.pricepressure,powerreduction,ASICEOL,security

• FPGAVendorspecificmacroslimitthemigrationtoanothervendor/technology.– MostnotablyFPGAvendorprovidedCPUs(e.g.Nios,

Microblaze)restricttheirusageinothertechnologies.

WhyMigrateFPGAstoASICs?

• 4P’s– Price– Performance– Power– Protection• IPtheftbycopyingbitstream• Securitybreachbysnoopingbitstream orhijackingFPGA• SEU/MBUsensitivity• Platformavailability

AlternativesStudy

• Manyproprietaryandopensourcealternatives– ARM,MIPS,ARC– OpenRisc,Leon2/3– OpenSparc,T1

• Allhavelimitationsonusability– HighNREs,limitingROI– Technologyapplicability/availability– OutdatedISAs– Potentiallegalissuesdueto(L)GPLlicensing

WhyRISC-V

• CPUrequirements– Royaltyfree– Targettechnologyindependent– EquallywellsuitedforFPGAandASIC– Lowresourcerequirements– Flexibleinstruction/featureset– Supportformultiplebusinterfaces

• TheRISC-VISAallowsustofulfillalloftheabove

RV11• Roa Logic’sRVI32/64implementation

– RV11=in-order,singleissue,singlethread– RV22=in-order,dualissue,dualthread

• ‘Folded’optimizing,5stagePipeline– SomeclassicRISCstagesarefoldedtogetherforperformance

reasons– IDstagedecidesifinstructionsequencecanbeoptimized.

ImprovesIPCbyhidingstalls• DesignedforFPGAtoASICmigration

– Technologyindependent– Parametersallowstradeoffsbetweenfeatures,ISAextensions,

andperformancevs area– Flexiblebusinterfaceallowsvirtualdrop-inintoanyexisting

system

Architecture

CPU State

Register File

Instruction Cache

Fetc

h

Dec

ode/

Opt

imiz

e

Exec

ute

Writ

e Ba

ck

Memory

Execution Pipeline

BranchPredictor

DataCache

RISC-V CoreInstruction Interface

DataInterface

ConfigurableInterface

OptionalUnit

Pre-

Dec

ode

DebugUnit

CustomerCaseStudy

• ReplaceNIOS-II32-bitControlPlaneCPU– >100DMIPS– NoMMU,NoCaches– AHB3Interfaces

• ReplacedNIOSintheFPGA– HW/SWdevelopment,test anddebug

• MigrationtoeASIC’s Nextreme-3PlatformASIC

ReplacementFlow

• Parallel flow– Verify&DebugonFPGA– ImplementPlatformASIC

• OnceFPGAverificationcompletedPlatformASICcanbetaped-out

Replace additional technology specific

blocks

ExistingFPGA or ASIC

design

ReplaceCPU Subsystem

FPGASynthesis

Nextreme Synthesis

FPGAPlace & Route

NextremePlace & Route

FPGAVerification

NextremePhysical Verification

NextremeTape-out

ImplementationResultsLogicCells Flipflops bRAM Fmax Power

Cyclone-V 1923ALMs 1561 4 114MHz 556mW

Nextreme-3 7924eCells 2386 1 649MHz 170mW

64bit 14721eCells 4249 1 578MHz 221mW

• Cyclone-Vwascustomer’scurrentFPGA• Nextreme-3chosenforprice,performance,andpower

– 5.7xperformanceincreasewhilereducingpowerby70%

• ToDo:– Nextreme implementsregisterfileinflipflops

Summary

• ImplementedRISC-Vinatechnologyindependentmanner

• SuccessfullyreplacedexistingFPGACPU• SuccessfullymigratedFPGAtoPlatformASICtherebyimprovingCPUperformanceby5xandpowerby70%

• Nextsteps– Improveresourceutilization– Increaseextensionsofferings– Addmulti-threading,multi-issue

QUESTIONS?

THANK YOU