<Tu4B>-<293-BG650>

A 64.5-88 GHz Coupling-Concerned

CMOS LNA with >10 dB Gain

and 5 dB Minimum NF

Kaijuan Zhang1, Chunqi Shi1, Guangsheng Chen2,

Jinghong Chen3, and Runxi Zhang1

1IMCS, East China Normal University, Shanghai, China 2Shanghai Eastsoft Microelectronics Co. Ltd., Shanghai, China

3ECE, University of Houston, Houston, USA

<Tu4B>-<293-BG650>

• Motivation

• Low Noise Amplifier Design

• Measurement Results

• Conclusion

2

Outline

<Tu4B>-<293-BG650>

• The mm-Wave is a promising candidate for the 5G

communication owing to its rich spectrum resources and

high data-rate.

• The CMOS technology offers high integration density,

cost-efficient and high-yield.

• The design should be suitable for extensive E-band

applications.

3

Motivation

<Tu4B>-<293-BG650>

• Motivation

• Low Noise Amplifier Design

• Measurement Results

• Conclusion

4

Outline

<Tu4B>-<293-BG650>

AV

DD

1

VB

M1

S

G

G

M2

RF in

M3

M4

AV

DD

1

Cp

Cp

CP

AD

VB

M5

M6

S

G

G

RF out

CP

AD

M7

M8

AV

DD

2

AVDD2

R1C3

R2C4

AVDD2

VB

L3

L4TF1 TF2

TF3 TF4

Transformer-baseddual-coupling gm-boosted

Capacitiveneutralization

Common-gate-shorting

Interstagecoupling

Interstagecoupling

5

64.5-88GHz CMOS LNA

3 stage : 2 CS+1 cascode, differential topology, single-ended input and output

<Tu4B>-<293-BG650> 6

Inter-Stage Coupling Network

50 60 70 80 90 10035

40

45

50

k is fixed

|Z21|(

dB

Ω)

Freq (GHz)

Q=18 Q=16

Q=13 Q=11

Q=8

50 60 70 80 90 10030

40

50

60

Q is fixed

k

|Z21|(

dB

Ω)

Freq (GHz)

k=0.7 k=0.6 k=0.5 k=0.4

50 60 70 80 90 10020

40

60

80

100

84GHz78GHz

1st Inter-stage network

2nd Inter-stage network

Overall

|Z2

1|(

dB

Ω)

Freq (GHz)

58GHz

62.5GHz

|Z21|>87dBΩ@58.5-84.5GHz

(a) Step-up transformer (b) Trans-impedance when k varies

(c) Trans-impedance when Q varies (d) Trans-impedance response

<Tu4B>-<293-BG650>

AV

DD

1

M1

S

G

G

M2

RF in

CP

AD Bg BsBp

7

Transformer-Based Dual-Coupling

(TBDC) Gm-Boosted Technique

(a) TBDC CS circuit

(c) Equivalent circuit

Cgs

+

-Vgs gmVgs

Lpg

Lps

Big

Bis

vin

1:ng

1:ns

ioZpg

Zps

(b) Input balun

Effective trans-conductance:

Noise figure:

<Tu4B>-<293-BG650> 8

Simulation Results of TBDC Gm-Boosted

60 70 80 900

2

4

6

Gm

ax(d

B)

Frequency (GHz)

TSID Gmax

TBDC Gmax

2

4

6

8

Δ=0.8dB

TSID NFmin

TBDC NFmin

NF

min(d

B)

Δ=2.8dB

60 70 80 90-40

-30

-20

-10

0

<-10dB@62-84.8GHz

<-10dB@70.8-87.4GHz

TSID

TBDC

S11(d

B)

Frequency (GHz)

TSID: Traditional source inductive degeneration

TBDC: Transformer-based dual-coupling gm-boosted, Gmax improved by 0.8-2.8dB

<Tu4B>-<293-BG650> 9

Common-Gate-Shorting (CGS)-1

Conventional cascode:

CGS cascode:

=𝐼𝑜𝑢𝑡𝑔𝑚2𝐼𝑖𝑛

𝑠(𝐶2 + 𝐶3) + 𝑠𝑅𝐶2𝐶3 + 𝑔𝑚2

=𝐼𝑜𝑢𝑡𝑔𝑚2𝐼𝑖𝑛

𝑠(𝐶2 + 𝐶3) + 𝑔𝑚2

(a)CGS (green color) cascode (b) CGS 3D layout

(c) Equivalent half-circuit model

<Tu4B>-<293-BG650> 10

Common-Gate-Shorting (CGS)-2

60 70 80 908

10

12

14

16

Δ=4.3dB

MS

G (

dB

)

Frequency (GHz)

With CGS

Without CGS

Δ=5.3dB

60 70 80 902

4

6

Δ=0.9dB

Δ=1.3dB

NF

min(d

B)

Frequency (GHz)

Without CGS

With CGS

MSG improved by 4.3-5.3 dB, NFmin improved by 0.9-1.3 dB.

<Tu4B>-<293-BG650>

• Motivation

• Low Noise Amplifier Design

• Measurement Results

• Conclusion

11

Outline

<Tu4B>-<293-BG650> 12

Die Photo of the Proposed LNA

Process: 55-nm CMOS, Area: 958*177um2.

<Tu4B>-<293-BG650>

60 70 80 90-90

-60

-30

0

3023dB@83GHz

-10dBS

-pa

ram

ete

rs(d

B)

Freq (GHz)

S11_Simu S11_Meas

S12_Simu S12_Meas

S21_Simu S21_Meas

S22_Simu S22_Meas

10dB-5dB BW 64.5-88GHz

15dB@83GHz

13

Simulated and Measured S-parameters

<Tu4B>-<293-BG650> 14

NF and K Factor Measurement Results

5dB@82GHz

60 70 80 904

6

8

10

NF_Meas

NF

(dB

)

Freq (GHz)

0

50

100

150

K_Meas

K (

facto

r)

<8dB@64.5-88GHz

Kf>2.5

<Tu4B>-<293-BG650> 15

Large Signal Measurement Results

-22 -20 -18 -16 -14 -12 -10 -8-15

-10

-5

0

5

10 Pout@70GHz_Meas

Pout@80GHz_Meas

Pout

(dB

m)

Pin (dBm)

10

11

12

13

14

15 Gain@70GHz_Meas

Gain@80GHz_Meas

Gain

(d

B)

-12.8dBm@80GHz

-12.2dBm@70GHz

<Tu4B>-<293-BG650>

• Motivation

• Low Noise Amplifier Design

• Measurement Results

• Conclusion

16

Outline

<Tu4B>-<293-BG650>

Employs the step-up transformer inter-stage coupling network

and co-optimized the inter-stage trans-impedance responses

to achieve wide bandwidth.

Employs the transformer-based dual-coupling gm-boosted

input balun to simultaneously obtain high gain and low noise.

Employs capacitive neutralization and common-gate-shorting

techniques.

Achieves a minimum NF of 5 dB, and >10 dB gain over 64.5-88

GHz.

17

Conclusion

<Tu4B>-<293-BG650> 18

LNA Performance ComparisonRef [2] RFIC 2016 [3] TMTT 2016 [5]JSSC 2017 [13] TMTT 2020 This Work

Technology 40nm CMOS 28nm CMOS 28nm CMOS22nm FDSOI

CMOS55nm CMOS

Topology2-stage

Cascode3-stage Cascode

1-stage CG+

4 stage CS

3-stage

Cascode

2-stage CS+

1-stage Cascode

Structure Single-ended Single-ended Single-ended Single-ended Differential

Peak Gain(dB) 15 28.2 25.4 29.6 24 15

BW3dB(GHz)13

(48-61)

7.2

(51-58.2) #

7.8

(50.8-58.6) #

28.3

(68.1-96.4)

13

(70.5-83.5) #

7.6

(78.9-86.5)

BW5dB(GHz) 16(46-62) # 11(49-60) # 9(50-59) # 33(65-98) # 24(67-91) # 23.5(64.5-88)

Minimum NF(dB) 3.6 3.6 3.8 6.4 4.6 5

IP1dB(dBm) -25 -29.4# -27.5# -28.1 -26.8 -12.2

PDC(mW) 20.4 19.8 19.8 31.3 16 72.7

Area(mm2) 0.195 0.112* 0.141* 0.675 0.35 0.106*

FOM1 0.0088 0.0083 0.0093 0.0125 0.0143 0.0155

FOM2 0.0108 0.0127 0.0108 0.0147 0.0162 0.0507

# Estimated values from papers ,

* Area excluding bondpads,𝐹𝑂𝑀1 = Τ𝐺𝑎𝑖𝑛[lin] · 𝐵𝑊−3𝑑𝐵[GHz] · 𝐼𝑃1𝑑𝐵[lin] 𝑃𝑑𝑐[mW] · 𝐹 − 1𝐹𝑂𝑀2 = Τ𝐺𝑎𝑖𝑛[lin] · 𝐵𝑊−5𝑑𝐵[GHz] · 𝐼𝑃1𝑑𝐵[lin] 𝑃𝑑𝑐[mW] · 𝐹 − 1

<Tu4B>-<293-BG650>

[1] A. Arbabian and A. Niknejad, “A three-stage cascaded distributed amplifier with GBW exceeding 1.5THz,”

IEEE RFIC Symposium, Montreal, QC, 2012, pp. 211-214.

[2] H. Gao et al., “A 48-61 GHz LNA in 40-nm CMOS with 3.6 dB minimum NF employing a metal slotting

method,” IEEE RFIC Symposium, San Francisco, CA, 2016, pp. 154-157.

[3] S. Guo, T. Xi, P. Gui, D. Huang, and T. Fan, “A transformer feedback Gm-boosting technique for gain

improvement and noise reduction in mm-Wave cascode LNAs,” IEEE Transactions on Microwave Theory and

Techniques, vol. 64, no. 7, pp. 2080-2090, July 2016.

[4] W. Shin, S. Callender, S. Pellerano and C. Hull, “A compact 75 GHz LNA with 20 dB gain and 4 dB noise

figure in 22nm FinFET CMOS technology,” IEEE RFIC Symposium, Philadelphia, PA, 2018, pp. 284-287.

[5] M. Vigilante and P. Reynaert, “On the design of wideband transformer based fourth order matching

networks for E-Band receivers in 28-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 52, no. 8, pp.

2071-2082, August 2017.

[6] ITU, “IMT identification including possible additional allocations to the mobile services on a primary basis

in portion(s) of the frequency range between 24.25 and 86 GHz for the future development of IMT for 2020

and beyond (WRC-19 1.13),” 2015.

19

References

<Tu4B>-<293-BG650>

[7] R. Levinger et al., “High-performance E-band transceiver chipset for point-to-point communication in SiGe

BiCMOS technology,” IEEE Transactions on Microwave Theory and Techniques, vol. 64, no. 4, pp. 1078-1087,

April 2016.

[8] H. Chen, Y. Lin and S. Lu, “Analysis and design of a 1.6-28 GHz compact wideband LNA in 90 nm CMOS

using a π-match input network,” IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 8, pp.

2092-2104, Aug 2010.

[9] Y. Natsukari and M. Fujishima, “36 mW 63 GHz CMOS differential low noise amplifier with 14 GHz

bandwidth,” IEEE VLSI Symposium, Kyoto, Japan, 2009, pp. 252-253.

[10] S. Kong, H. Lee, M. Lee and B. Park, “A V-Band current-reused LNA with a double-transformer-coupling

technique,” IEEE Microwave and Wireless Components Letters, vol. 26, no. 11, pp. 942-944, Nov 2016.

[11] Z. Chen, H. Gao, D. Leenaerts, D. Milosevic and P. Baltus, “A 29-37 GHz BiCMOS low-noise amplifier

with 28.5 dB peak gain and 3.1-4.1dB NF,” IEEE RFIC Symposium, Philadelphia, PA, 2018, pp. 288-291.

[12] H. Jia, C. Prawoto, B. Chi, Z. Wang and C. Yue, “A 32.9% PAE, 15.3 dBm, 21.6-41.6 GHz power amplifier

in 65nm CMOS using coupled resonators,” IEEE A-SSCC, Toyama, 2016, pp. 345-348.

[13] L. Gao, E. Wagner and G. M. Rebeiz, “Design of E- and W-Band Low-Noise Amplifiers in 22-nm CMOS

FD-SOI,” IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 1, pp. 132-143, Jan 2020.

20

References

<Tu4B>-<293-BG650>

A 64.5-88 GHz Coupling-Concerned

CMOS LNA with >10 dB Gain

and 5 dB Minimum NF

Kaijuan Zhang, Chunqi Shi, Guangsheng Chen,

Jinghong Chen, and Runxi Zhang

Thank you!