a 6 gb/s low power transimpedance amplifier with …...arrayed transimpedance amplifiers (tia) with...

http://dx.doi.org/10.5573/JSTS.2015.15.1.122 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.1, FEBRUARY, 2015

Manuscript received Jul. 31, 2014; accepted Dec. 2, 2014 Sungkyunkwan University -College of Information and Communication Engineering, Seoul, Republic of Korea E-mail : [email protected]

A 6 Gb/s Low Power Transimpedance Amplifier with Inductor Peaking and Gain Control for 4-channel

Passive Optical Network in 0.13 mm CMOS

Juri Lee, Hyung Gu Park, In Seong Kim, YoungGun Pu, Keum Cheol Hwang, Youngoo Yang, Kang-Yoon Lee, and Munkyo Seo

Abstract—This paper presents a 6 Gb/s 4-channel arrayed transimpedance amplifiers (TIA) with the gain control for 4-channel passive optical network in 0.13 mm complementary metal oxide semiconductor (CMOS) technology. A regulated cascode input stage and inductive-series peaking are proposed in order to increase the bandwidth. Also, a variable gain control is implemented to provide flexibility to the overall system. The TIA has a maximum 98.1 dBΩ gain and an input current noise level of about 37.8 pA/Hz. The die area of the fabricated TIA is 1.9 mm x 2.2 mm for 4-channel. The power dissipation is 47.64 mW/1ch. Index Terms—Transimpedance amplifiers (TIA), passive optical network, regulated cascode, gain control

I. INTRODUCTION

Recently, the demand for high data rate access network services has facilitated a rapid increase in the development of an economical optical access system. The time-and wavelength-division multiplexed passive optical network (TWDM-PON) and PtP-PON architecture with centralized VCSEL at the optical line terminal (OLT) has emerged as an attractive solution for low-cost implementation. As shown in Fig. 1, next

generation-passive optical network2 (NG-PON2) utilizes WDM and time division multiplexing (TDM) methods to assign a private wavelength between the OLT and the optical network unit (ONU) in order to support PtP-PON as well as TWDM-PON through a time division system. All transmission from the PON is performed between the provider and user, those mean OLT and ONU respectively. The OLT resides in the primary outlet and connects from the optical access network to the metro backbone. To provide a service, PtP WDM technology uses different wavelengths of the optical signals between users, and TWDM-PON technology follows a PtP structure, which is based on its wide area access and broadband service, and is applied mainly to home and business users. The solution to the obstacle of high costs for the commercial use of WDM-PON is to create a one-chip optical transmission module of OLT equipment through the application of CMOS Photonics technology, thus lowering costs, power consumption, and achieving miniaturization, as well as lowering the unit cost of the

Fig. 1. NG-PON2 System.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.1, FEBRUARY, 2015 123

line card production. Fig. 2 shows the optical access system in terms of the

components. High-speed TIA as an optical receiver is often implemented in SiGe technology because of the better current driving capability with higher operating frequency of a bipolar process. However, CMOS technologies become very attractive due to their low cost and area. Also, in order to use inexpensive optical technology, the parallelized optical channels have been considered an efficient way to increase the capacity of the data link.

In this paper, a 6 Gb/s 4-channel TIA for an optical receiver is implemented in 0.13 mm CMOS technology with the gain control. In order to achieve the high gain and bandwidth of 6 Gb/s at the same time in the CMOS process, a multi-stage TIA architecture with the inductor peaking technique is proposed. Also, the variable gain control is implemented to provide flexibility to the overall system.

II. 6 GB/S TRANSIMPEDANCE AMPLIFIER

Fig. 3 shows a block diagram of 6 Gb/s TIA. Firstly, TIA Core receives the input current from the photo diode (PD) and converts the current into the voltage. The single to differential converter (SDC) block is needed for differential output since the input is single-ended. For the wide dynamic range, the gain control function is implemented in the limiting amplifier (LA) stages. The Gain Control Bit<1:0> is controlled by the serial peripheral interface (SPI) controller. The gain of LA and output buffer is controlled by adjusting their bias voltage from the bias generator block. When the input current is very small, the TIA should provide a sufficiently high transimpedance.

Fig. 4(a) is a schematic of the proposed TIA Core. To

enhance the bandwidth, the TIA Core is designed as a three stage topology: regulated cascode (RGC), inverter, and common source with feedback [1]. The RGC circuit provides the characteristics of high output impedance and wide output voltage range [1]. It also has another important feature, which is useful for high-speed low-noise preamplifier design, i.e., the virtual-ground input impedance when the input transistor is replaced with a current source. The photodiode is used as an optical detector that converts the incoming optical power to a signal photocurrent. The photocurrent is amplified to be a voltage at the drain of M1. The M2 and R2 stage operates as a local feedback and thus reduces the input impedance by the amount of its own voltage gain. In the first stage, the three inductors (L1, L2, and L3) are used for the inductor peaking to increase the bandwidth by cancelling the parasitic capacitances at the gates of M2, M1, and M4,

Fig. 2. System configuration with 6 Gb/s 4-channel TIA.

Fig. 3. Block diagram of 6 Gb/s TIA.

(a)

(b)

Fig. 4. (a) Schematic of TIA Core, (b) equivalent circuit of photo diode (PD).

124 JURI LEE et al : A 6 GB/S LOW POWER TRANSIMPEDANCE AMPLIFIER WITH INDUCTOR PEAKING AND GAIN CONTROL …

and M5, respectively. The inverter type second stage is implemented to provide the additional voltage gain. The third stage is the common source amplifier with the resistive feedback for high bandwidth.

We included a bonding wire for chip-on-board (COB), PD parasitic capacitance, and pad capacitance when simulating this TIA, which can have a great impact on the performance. The parasitic capacitances and resistances in the PD shown in Fig. 4(b) can limit the bandwidth in addition to the parasitic capacitances due to the PADs. Thus, they should be minimized in the layout and measurement board to achieve the bandwidth of 6 Gb/s.

Fig. 5 shows a schematic of the SDC. Since the output of the TIA Core is single-ended, the SDC is designed to minimize the even-order harmonic and reject the common mode noise. It should maintain the wide bandwidth of the TIA Core. To guarantee the wide bandwidth and differential balancing quality, it is composed of two stages. In the first stage, load resistors are used instead of the active inductor to achieve the small area. The resistors, R1 and R2, can implement the resistive feedback and equal common mode level of differential outputs, respectively. The second stage compensates for the mismatches caused by the first stage, resulting in an improved differential balancing.

Fig. 6(a) and 6(b) show a schematic of the LA and output buffer, respectively. The output of the TIA Core is amplified at the LA and transferred to the output buffer. The negative impedance converter (NIC) can cancel the parasitic capacitance of the following stage to improve the bandwidth.

The negative impedance can be written in Eq. (1). A NIC transforms Cc to negative capacitance between X

and Y. If the gate-drain capacitance of M7 and M8 are neglected, the impedance seen on the drain side is explained as

( )21 m gs c

NICc m gs

g s C CZ

sC g sC

+ += -

- (1)

where ZNIC, gm, Cgs, and Cc represent the negative impedance, transconductance of M7 and M8, gate-source capacitance of M7 and M8, and coupling capacitance, respectively [3]. If the MOSFET loads are used to increase the voltage gain, the bandwidth of the LA is limited due to the parasitic capacitances of the MOSFETs. In this work, the resistor loads are adopted instead of the inductor loads since the inductor loads increase the die area and parasitic capacitance due to the long length of the routing line, although the inductor itself can increase the bandwidth of the LA. The LA is composed of multi-stages to improve the bandwidth and voltage gain. The voltage swing at the final output of the TIA can be adjusted by controlling the tail currents of the LA and output buffer with a 2-bit digital code.

Fig. 7(a) and (b) show the schematic of a low voltage bandgap reference (BGR) and bias generator, respectively. The BGR generates the constant bias

Fig. 5. Schematic of single to differential converter (SDC).

(a)

(b)

Fig. 6. Schematic of (a) limiting amplifier (LA), (b) output buffer.


voltage with respect to the process, supply voltage, and temperature (PVT) variations. The conventional BGR cannot be used under the supply voltage of 1.2 V since it generates the output voltage of 1.2 V. Thus, a low voltage BGR is designed to generate the output voltage of 0.4 V, which is used for the bias circuits. Q2 has an emitter area that is larger by a factor n than that of Q1. M5 and M6 are matched, and the transistor size of M9 is m times of M5 and M6. Also, transistor size of M10 is m times of M7 and M8.

The output voltage of the low voltage BGR can be written in Eq. (2) [8].

15 5

1 3

ln( )BE TOUT

V V nV IR m RR R

æ ö= = +ç ÷

è ø (2)

where the first term and second term in the parenthesis are the proportional to absolute temperature (PTAT) and the complementary to absolute temperature (CTAT), respectively. The BJTs in the BGR can implement the PTAT and CTAT circuits to generate the temperature independent output voltage. The operational amplifier renders the differential input equal in order to provide the stable output voltage under the PVT variations. The two

stage operational amplifier (OP AMP) with the high voltage gain is designed to improve the power supply rejection ratio (PSRR) and minimize the variation of output voltage due to the temperature. Also, the start-up circuit is implemented to guarantee the stable operation at the moment of power up. As shown in Fig. 7(b), the LA_BIAS and the OB_BIAS are selected by the Gain Control Bit<1:0> which determines the gain.

III. EXPERIMENTAL RESULTS

Fig. 8 shows the chip layout of the proposed TIA. The die area is 1.9 mm x 2.2 mm. Since the circuit is operating at high speed, the length of the routing line is minimized at the layout level. Fig. 9 shows the measurement board of the proposed TIA. The length of the signal line is minimized at the measurement board level as well as at the die level. The internal control bits can be programmed through the SPI.

Fig. 10 shows the AC simulation result of the TIA. The simulated total gain from the input to output buffer is 98.6 dBΩ at 5 GHz. The output of TIA can be

(a)

(b)

Fig. 7. Schematic of (a) a low voltage bandgap reference, (b) a bias generator.

TIA Core

Single to Differential Converter

LimitingAmplifier

OutputBuffer

1 Ch.

Fig. 8. Chip layout pattern of the proposed TIA.

INPUT

Output

SPI

VDD/GND

TIA

ExternalBias

Fig. 9. Measurement board of the proposed TIA.


amplified gradually by the LA1, 2, 3 and output buffer. The bandwidth of TIA Core is wide enough to cover the bandwidth of 5 GHz. LA1_OUT, LA2_OUT, LA3_OUT, and BUF_OUT are the output of LA1, LA2, LA3, and output buffer, respectively. The bandwidths at the outputs of the LA1, LA2, LA3, and Output Buffer are still high although they are degraded compared with those at the output of SDC (SDC_OUT).

Fig. 11 shows the transient simulation result of the TIA. As shown in Fig. 11, the output swing is adjusted when the Gain Control Bit<1:0> are changed. Also, we can see that it can amplify the random input pattern of 5 GHz.

Fig. 12 shows input referred noise (IR noise) simulation result of the proposed TIA. When connected to a load capacitance of 0.2 pF at the input and output, the input referred noise is 37.8 pA/√Hz at the frequency range of 1 MHz to 5 GHz.

Fig. 13(a) and (b) show the simulated output voltage and PSRR of the BGR with respect to the PVT variations, respectively. The worst case variation is 1.4 mV when the temperature is swept from -30 °C to 120 °C. The PSRR is defined as the ability of the circuit to maintain its output voltage as its supply voltage is varied. The PSRR for a BGR circuit can be calculated by the Eq. (3) [9].

( ) 20log BGR OUTPUT

SUPPLY

VPSRR dB

V-æ öD

= ç ÷Dè ø

(3)

where ∆VBGR-OUTPUT and ∆VSUPPLY are the variations of BGR output voltage and supply voltage, respectively.

The worst case of the PSRR is -82.5 dB at the low frequency when the condition is the SS process, the supply voltage variation of – 10% (1.08 V), and the high temperature (120 °C).

Fig. 14(a) and (b) show measurement setup and equipment of the proposed TIA, respectively. The data pattern from BERT scope is applied to VCSEL driver. The optical power from the VCSEL array is transferred to PD array before the TIA. The TIA takes the input

BUF_OUT

Frequency (Hz)

100

Gain (dB)

80

60

40

20

0

-20

-40

-605G 10G 100G100M

LA3_OUT

LA2_OUT

LA1_OUTTIA_OUT

SDC_OUT

Block AC Gain @5GHz

TIA_OUT 50.0dBΩ

SDC_OUT 47.2dBΩ

LA1_OUT 61.8dBΩ

LA2_OUT 77.1dBΩ

LA3_OUT 93.4dBΩ

BUF_OUT 98.6dBΩ

1G

Fig. 10. AC simulation result of the proposed TIA.

BUF_VOUTP,N

BUF_VB: 400mVSwing: 243.6mVGain Control Bit <00>

BUF_VB: 480mVSwing: 577mVGain Control Bit <10>


BUF_OUT,OUTB


800m

300m

1.30

( V

)

1.30

900m

500m

( V

)

700m

1.00

1.30

( V

)

900m

1.10

1.30

( V

)

Time (s)

1.0n 2.0n 3.0nTime (s)

( A

)

20u

10u15u

5u0

TIA input : 20uA

11 00 1 0 1 0

11 00 1 0 1 0

11 00 1 0 1 0

11 00 1 0 1 0

11 00 1 0 1 0

BUF_OUT,OUTB

BUF_OUT,OUTB

BUF_OUT,OUTB

Fig. 11. Transient simulation result of the proposed TIA.

Fig. 12. Input referred noise simulation result of the proposed TIA.

(a) (b)

Fig. 13. (a) Temperature variation of BGR, (b) PSRR simulation result of BGR.


current from the PD array. Also, the output of TIA is applied to the BERT scope, oscilloscope, and spectrum analyzer.

Fig. 15 shows the measured transimpedance gain of the proposed TIA. The measured total gain from the input to output buffer is 98.1 dBΩ at 5 GHz.

Fig. 16 shows the measured waveform of the proposed TIA. The output signal level is 97.73 mVp-p at the data rate of 6 Gb/s. Fig. 17 shows the measured jitter of the proposed TIA. The proposed TIA output jitter is smaller than the result of [6, 7]. The proposed output jitter is

13.875 ps (0.04 UI) at the data rate of 6 Gb/s. The data Jitter of [7] is 50.3 ps (0.14 UI) at 5.5 Gb/s and that of [6] is 0.55 UI at 5 Gb/s. Fig. 18 shows the measured dynamic range of the proposed TIA. Therefore, The output swing can be controlled from 64 mVp-p to 191 mVp-p by the Gain Control Bit<1:0>.

Table 1 shows a performance comparison of TIA with prior works. The goal of this work is to integrate the 4-channel TIAs in the 0.13 mm CMOS process. Thus, the die area per channel is smaller than that given in [6, 7] that can support only one channel.

(a)

BERTHigh Freq.Oscilloscope

NetworkAnalyzer

DataInput

DataOutput

Test Board

1.2V Supply

(b)

Fig. 14. (a) Measurement setup, (b) Measurement equipment for the proposed TIA.

40

50

60

70

80

90

100

110

120

0.1 1 10

BUF_OUT

Frequency(GHz)

Gai

n(dB

Ω)

98.1 dBΩ @ 5 GHz

Fig. 15. Measured transimdepance of the proposed TIA.

TIA Output(6 Gbps) = 97.73 mVp-p (@Input = -13 dBm)

97.73 mVp-p

Fig. 16. Measured waveform of the proposed TIA.

Jitter Histogram

Jitterp-p =13.875 ps020406080

100120140160180

-6 ps

Y : Hits

( Time )-4 ps -2 ps 0 s 2 ps 4 ps 6 ps

MAX:7.127 ps

MIN:-6.748 ps

Fig. 17. Measured jitter of the proposed TIA.

[00][01]

[10]

[11]

191mVp-p

Time (t)

Volta

ge (v

)

64mVp-p

Fig. 18. Measured dynamic range of the proposed TIA by the gain control bit<1:0>.


The power consumption per channel is 47.64 mW from the supply voltage of 1.2 V. The bandwidth can be enhanced with the small power consumption since the parasitic capacitances of the 1.2 V MOSFET devices are smaller than those of the 3.3 V MOSFET devices. The total gain of the TIA Core, SDC, 3-stage LA, and Output Buffer is 98.1 dBΩ, which is larger than that given in [4-7]. Also, the proposed TIA can get variable gain. Output jitter is smaller than the result of [6, 7].

IV. CONCLUSIONS

In this paper, the design of 6 Gb/s 4-channel arrayed TIA with gain control using 0.13 μm CMOS process technology for optical receiver is implemented.

The TIA is composed of a TIA Core, a single to differential converter, 3 stage of limiting amplifiers, and an output buffer. To enhance the bandwidth and gain, inductive peaking techniques, regulated cascode and common source with feedback and series inductor are adopted. The TIA has gain of 98.1 dBΩ over an optical bandwidth in 5 GHz. The area occupied for the 4-channel is 1.9 mm x 2.2 mm and the power consumption is only 47.64 mW/1 ch.

ACKNOWLEDGMENTS

This research was supported by Global PH.D Fellowship Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (2013H1A2A1034225).

REFERENCES

[1] Hammoudi, E., Imad, B., Mohamed, D., "High Bandwidth 0.35μm CMOS Transimpedance Amplifier", Complex Systems (ICCS), International Conference on Digital Object Identifier, pp. 1-6, 2012

[2] Xiao-Xia Wang, Zhi-Gong Wang, Jii-Shun, Xue-Mei Lei, “10-Gb/s high-density trans-impedance amplifier in 0.18-um CMOS”, Wireless Communi- cation & Signal Processing Conference, pp. 1-4, 2009.

[3] Sherif Galal, Behzad Razavi, “10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology”, IEEE J. Solid-State Circuits, Vol. 38, No. 12, pp. 2138-2146, Dec. 2003

[4] Chia-Hsin Wu, Chih-Hun Lee, Wei-Sheng Chen, Shen-luan Liu, “CMOS wideband amplifiers using multiple inductiveseries peaking technique,” IEEE J. Solid-State Circuits, Vol. 40, pp.548–552, Feb. 2005.

[5] A. K. Peterson, K. Kiziloglu, T. Yoon, F.Williams, and M. R. Sandor Jr, “Front-end CMOS chipset for 10 Gb/s communications”, IEEE RFIC Dig. Papers, pp. 93–96, Jun. 2002.

[6] Mohsine Menouni, Tianzue Xi, Ping Gui, Paulo Moreira, “A 5-Gb/s Radiation-Tolerant CMOS Optical Receiver”, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, Vol. 60, No. 4, Aug. 2013

[7] W.-Z. Chen et al., “A 1.8 V 10-Gb/s fully integrated CMOS optical receiver analog front-end,” IEEE J. Solid-State Circuits, Vol. 40, pp.1388–1396, Jun. 2005.

Table 1. Performance comparison of TIA with prior works Parameter [4] [5] [6] [7] This Work

Technology 0.18 μm CMOS 0.18 μm CMOS 0.13 μm CMOS 0.18 μm CMOS 0.13 μm CMOS Data Rate (Gb/s) 10 10 5 10 6

Gain (dBΩ) 61 62.3 66 87 98.1 Supply Voltage (V) 1.8 1.8 1.2 1.8 1.2 Bandwidth (GHz) 7.2 9 N.A. 7.6 5

Area (Package or Die) 0.14 mm² / (1 Ch) N.A. (0.75 mm x 1.25 mm) / (1 Ch)

(1.028 mm x 1.796 mm) / (1 Ch)

(1.9 mm x 2.2 mm) / (4 Chs)

Power (mW/Ch) 70 108 120 210 47.64 Sensitivity (dBm) N.A. N.A. -19 -12 -27

Input Referred Noise Current (/√Hz) 8.2pA N.A. N.A. N.A. *37.8 pA

* Simulation result


[8] Yeong-Tsair Lin, Mei-Chu Jen, Dong-Shiuh Wu, and Huan-Ren Cheng, “A Low-Variation, Low-Voltage CMOS Bandgap Reference Circuit”, Dept. of Electronic Eng., Lunghwa Univ. of Science and Technology., Issue 25, Jun. 2008

[9] B. Razavi, “Design of Analog CMOS Integrated Circuits”, McGraw-Hill, 2001.

Juri Lee received his B.S. degree from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2013, where she is currently working toward the combined Ph.D. & M.S degree in School of Information and Commu-

nication Engineering, Sungkyunkwan University. Her research interests include VCSEL driver and CMOS RF transceiver.

Hyung-Gu Park received his B.S. degree from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2010, where he is currently working toward the Ph.D. degree in College of Information and Communication

Engineering, Sungkyunkwan University. His research interests include high-speed interface IC and CMOS RF transceiver.

In-seong Kim was born in Seoul, Korea. He received his B.S degree from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2014, and he is currently working toward the Combined Ph.D. & M.S. Course in

School of Information and Communication Engineering, Sungkyunkwan University. His research interests include high-speed interface IC and CMOS RF transceiver.

YoungGun Pu received his B.S., M.S. and Ph.D. degrees from the Department of Electronic Engi- neering at Konkuk University, Seoul, Korea, in 2006, 2008 and 2012, respectively. His research interest is focused on CMOS fully integrated

frequency synthesizers and oscillators and on transceivers for low-power mobile communication.

Keum Cheol Hwang received his B.S. degree in electronics engineering from Pusan National University, Busan, South Korea in 2001 and M.S. and Ph.D. degrees in electrical and electronic engineering from Korea Advanced Institute of

Science and Technology (KAIST), Daejeon, South Korea in 2003 and 2006, respectively. From 2006 to 2008, he was a Senior Research Engineer at the Samsung Thales, Yongin, South Korea, where he was involved with the development of various antennas including multiband fractal antennas for communication systems and Cassegrain reflector antenna and slotted waveguide arrays for tracking radars. He was an Associate Professor in the Division of Electronics and Electrical Engineering, Dongguk University, Seoul, South Korea from 2008 to 2014. In 2015, he joined the Department of Electronic and Electrical Engineering, Sungkyunkwan University, Suwon, South Korea, where he is now an Associate Professor. His research interests include advanced electromagnetic scattering and radiation theory and applications, design of multi-band/broadband antennas and radar antennas, and optimization algorithms for electromagnetic applications. Prof. Hwang is a life-member of KIEES, a senior member of IEEE and a member of IEICE.


Youngoo Yang (S'99-M'02) was born in Hanyang, Korea, in 1969. He received the Ph.D. degree in electrical and electronic engineering from the Pohang University of Science and Technology(Postech), Pohang, Korea, in 2002. From 2002

to 2005, he was with Skyworks Solutions Inc., Newbury Park, CA, where he designed power amplifiers for various cellular handsets. Since March 2005, he has been with the School of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea, where he is currently an associate professor. His research interests include power amplifier design, RF transmitters, RFIC design, integrated circuit design for RFID/USN systems, and modeling of high power amplifiers or devices.

Munkyo Seo received the Ph.D. degree in electrical engineering from the University of California, Santa Barbara (UCSB), in 2007. From 1997 to 2002, he was a RF Engineer with LG Electronics Inc., designing RF/microwave subsystems for wireless

communication. He was an Assistant Project Scientist with UCSB from 2008 to 2009. His research at UCSB focused on signal processing techniques for time-interleaved analog-to-digital converters, novel millimeter-wave communication/sensor network systems, and millimeter-wave IC designs in advanced CMOS and HBT technologies. In 2009, he joined Teledyne Scientific Company, Thousand Oaks, CA, where he worked on the design of mixed-signal and sub-millimeter-wave circuits. Since Mar. 2013, he has been with Sungkyunkwan University, Korea, as an assistant professor.

Kang-Yoon Lee received the B.S., M.S. and Ph.D. degrees in the School of Electrical Engineering from Seoul National University, Seoul, Korea, in 1996, 1998, and 2003, respectively. From 2003 to 2005, he was with GCT Semiconductor Inc., San Jose,

CA, where he was a Manager of the Analog Division and worked on the design of CMOS frequency synthesizer for CDMA/PCS/PDC and single-chip CMOS RF chip sets for W-CDMA, WLAN, and PHS. From 2005 to 2011, he was with the Department of Electronics Engineering, Konkuk University as an Associate Professor. Since 2012, he has been with College of Information and Communication Engineering, Sungkyun- kwan University, where he is currently an Associate Professor. His research interests include implementation of power integrated circuits, CMOS RF transceiver, analog integrated circuits, and analog/digital mixed-mode VLSI system design.

a 6 gb/s low power transimpedance amplifier with …...arrayed transimpedance amplifiers (tia) with...

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