a 53%-pte and 4-mbps power and data telemetry circuit
TRANSCRIPT
A 53%-PTE and 4-Mbps Power and Data Telemetry Circuit based on
Adaptive Duty-cycling BPSK Modulated Class-E AmplifierA 53%-PTE and
4-Mbps Power and Data Telemetry Circuit based on Adaptive
Duty-cycling BPSK Modulated Class-E Amplifier
Siyao Zhu, Jian Zhao, Yongfu Li and Mingyi Chen [email protected]
Department of Micro-Nano Electronics and MoE Key Lab of Artificial Intelligence, Shanghai Jiao Tong University, China
ABSTRACT Implantable medical microsystems need an efficient power and data transmission link. The demand for increasing the battery life requests for higher power transfer efficiency (PTE), whereas the increasing functionality of the implantable chip demands a higher data-rate. The traditional single-pair-of-coil link based on Amplitude-Shift keying (ASK) modulated Class-E amplifier tends to have limited immunity on the interference. In addition, due to the conflict on the quality factor (Q) between the power transmis- sion and data transmission band, high PTE and high data rates are difficult to achieve at the same time. This paper proposes a power and data transmission link based on the adaptive duty-cycling bi- nary phase-shift keying (BPSK) modulated Class-E amplifier. The Class-E works alternatively between two modes determined by two clocks with different duty-cycles. The variation of the duty-cycle modulates the phase of the carrier through the resonant networks of the Class-E amplifier. A low-power Costas Loop is adopted to efficiently synchronize the carrier and recover the data from an inductive received signal. The whole link has been implemented and simulated in a 350-nm CMOS process. The simulation shows under date-rate of 4 Mbps, the link achieves a PTE of 53% with an energy efficiency of 600 pJ/bit.
CCS CONCEPTS •Hardware→Very large scale integration design;Radio fre- quency and wireless circuits.
KEYWORDS Power and data transmission,Binary phase-shift keying (BPSK), Duty-cycle, Class-E Power Amplifier, Costas Loop.
ACM Reference Format: Siyao Zhu, Jian Zhao, Yongfu Li and Mingyi Chen. 2020. A 53%-PTE and 4-Mbps Power and Data Telemetry Circuit based on Adaptive Duty-cycling BPSK Modulated Class-E Amplifier. In GLSVSLI ’20: ACM Great Lakes Sym- posium on VLSI, July 27–29, 2020, Beijing, China. ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/XXXXXXX.XXXXXXX
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1 INTRODUCTION Various types of implanted medical devices (IMDs) have been pro- posed for different diseases, such as cochlear implants [1, 2], retinal prosthesis [3–6], and deep brain stimulators (DBS) [7, 8]. The wire- less link can be established between the inside and outside of the body thanks to the magnetic field, which enables wireless power and data telemetry through the link.
The wireless link based on two respective pairs of overlapping coils has been proposed in [9–11]. It has advantages of increasing the PTE and data transmission rate simultaneously by introducing different quality factor Q between the coils. However, the system with two coils is bulky, which unavoidably raises the risk of the implantation. In addition, due to the cross coupling between the power and the data colis, the whole system suffers from strong cross talk between two links. Besides, it is complicated to opti- mize the structural parameters of all the coils to achieve the best performance.
In [12–15], the system based on a single pair of coils has been proposed. Amplitude-shift keying (ASK) is commonly adopted for data modulation because of its simplicity of circuit implementation. However, the movement of the subjects with the IMDs will have a negative impact on the signal quality across the received coil [16]. Moreover, due to the intrinsic drawback of ASK, high PTE and high data-rate are difficult to achieve at the same time because of the conflict on the Q between the power transmission and data transmission band [10]. Higher Q is generally preferable for effi- cient power transfer, however, this leads to narrower transmission bandwidth and thus lowers data rate.
In prior work [17] of our team, the PSK modulated Class-E ampli- fier has been proposed for data modulation. Although the data can be transmitted through the Class-E amplifier, the PSK modulation completely destroys its optimal operation point, which tends to reduce the PTE significantly. In this paper, we present a new type of BPSK modulator based on the adaptive duty-cycling BPSK mod- ulated Class-E amplifier, which ensures the sub-optimal operation of the Class-E amplifier. Hence, the TX has higher PTE under a higher data-rate. At the same time, the BPSK demodulator [18, 19] is realized through a low-power Costas loop so that the total energy efficiency can be improved. Fig. 1 illustrates the application of the proposed circuit.
This paper is organized as follows: Section II explains the princi- ple of the phase modulator. The circuit implementation is shown in Section III. Experimental results are provided in Section IV and Section V concludes the paper.
Figure 1: Wireless Energy and Data Transmission Model.
Data
Clk1
Clk2
Vgate
1
2
3
4
Data
Vgate
Lrf
Cp
Cn
S0
M0
(a)
Data
0
MUX
0
1
Figure 2: (a) Block diagram of the proposed phase modula- tor and (b) phasemodulation by controlling the resonant fre- quency.
2 ADAPTIVE DUTY-CYCLING BPSK MODULATOR
Class-E power amplifiers (PAs) have been widely used due to its 100% PTE [20, 21] under ideal operation. However, the previous PSK [17] modulated Class-E amplifier deviates its optimal operation point so that the PTE decreases dramatically.
Fig. 2 (a) illustrates the schematic of the proposed modulator based on the typical Class-E PAs. Lrf is an RF choke inductor which supplies stable DC current to the resonant tanks. R1 is an equivalent resistor including the parasitic resistances of L1 and the reflected impedance from the secondary coil into L1. In this design, Clk1 and Clk2 are off-chip clock signals with 20-MHz frequency, whose duty-cycles are 56% and 10%, respectively. The duty-cycle control
circuit proposed in [22] can regenerate pre-set duty-cycle signal based on phase-locked-loop circuits or crystal oscillators from the same clock source.
The resonant frequency can be expressed by (1):
ωi = 1
(i = 1, 2, 3, 4) (1)
where the Ci is the total resonant capacitance of the resonant net- work.
For the circuit shown in Fig. 2(a), there can be four different resonant frequencies as follows, depending on the on/off state of M0 and switch S0.
State 1: Data=0, Clk1=1, S0 is off,M0 is on, the capacitor Cp is shorted, the total resonant capacitance C1 is equal to Cs.
State 2: Data=0, Clk1=0, S0 andM0 are both off, the total reso- nant capacitor C2 is the series combination of Cp and Cs.
State 3: Data=1, Clk2=1, S0 and M0 are both on, the capacitor Cp and Cn are both shorted, the total capacitor C3 is equal to Cs.
State 4: Data=1, Clk2=0, S0 is on, M0 is off, the total resonant capacitor C4 is Cs in series with the parallel combination of Cp and Cn.
As a result, the resonant frequencies adaptive to the data meets the following relationship as given by (2):
ω1 = ω3 < ω4 < ω2 (2)
In phase modulation/demodulation, data is encoded through modulating the phase of the primary coil current and recovered through detecting the corresponding changes of the phase on the secondary coil. As the carrier phase is the integral of angular fre- quency, it will be changed by changing resonance frequency under different transmission data, whereas the current amplitude of coil L1 will not be affected theoretically. According to (3) [23]:
Q = 2π Stored Enery
Dissipated Enery in Each Cycle (3)
The stored/dissipated energy in the magnetic field is proportional to the square of the coil current if other parameters are all kept constant. Hence, PSKmodulator canmodulate the data independent of the Q , in the prevention of the conflict on Q between the power transmission and data transmission band, and leading to higher PTE.
In terms of PSK, both QPSK and BPSK can be adopted. The QPSK modulation has higher PTE since only a slight deviation exists from the optimal operation of the Class-E PAs. However, the QPSK demodulator is complicated while consuming higher power and chip area. In contrast, the BPSK enables a demodulator with much lower consumption overhead at the cost of lower PTE. With the consideration of the demand for low-power and small-area IMDs, BPSK is chosen in this design. The value of the components should be carefully chosen as there is a trade-off between the PTE and the power consumption of the demodulation circuit.
Fig. 2 (b) shows the modulation process. Clk1 and Clk2 have the same frequency with different duty-cycles. The driving voltage Vate ofM0 is from eitherClk1 orClk2, selected by the transmitted data. At the same time, the data also adaptively changes the on/off state ofM0 an S0, which modulates the resonant capacitance and in turn changes the resonant frequency of the Class-E PAs as shown
Power and Data Telemetry Circuit GLSVSLI ’20, May 27–29, 2020, Beijing, China
by (1). By controlling the switch, the resonant frequency can be changed instantly while the phase of the coil current cannot be changed immediately. As shown in Fig. 2(b), the slopes of phase change represent the resonant frequencies. Hence, the current phase can be adjusted by choosing suitable resonant frequency. The points (A, B) represent the phases of coil L1 current whenClk1 falling edges are taken as the reference lines. When data is 0, the phase of the coil current is θ ; when data is 1, the phase of the coil current is φ, the BPSK modulation will be achieved when the difference between θ and φ is 180. This leads to the design of the values of T1, T3 and ωi as follows:
The phase of point A:
θ = ω1 ·T1 (4)
φ = ω3 ·T3 + ω4 · (T1 −T3) (5)
The phase is shifted from A to B:
φ − θ = π (6)
Substituting the above equations (4) and (5) into equation (6):
(ω4 − ω1) · (T1 −T3) = π (7)
The carrier frequency of 20 MHz is adopted in the design [17]. To ensure high PTE, the Class-E PAs are required to meet zero- voltage switching (ZVS) and zero-derivative switching (ZDS) con- ditions [24]. With these conditions, the value of Cs (396 pF) and Cp (35 pF) can be calculated under a fixed coil L1 inductance value (1 µH). The value of Cn (2 pF) can be determined afterward by choosing a suitable value of ω4 that meets (2). It is noteworthy that in contrast to [17], where it is impossible to achieve zero turning on condition due to the coexistence of deceleration and acceleration, the proposed adaptive duty-cycling BPSK modulated Class-E Power amplifier avoids such issue and hence achieves higher PTE.
3 CIRCUIT IMPLEMENTATION 3.1 Inductive Coils Design This Section depicts a specific inductive coils design procedure with the HFSS electromagnetic simulation tool. As references [16, 25], the air gap between the primary coil and the secondary coil is 6 mm. Hence, in this design, we aim to design a coil with a coupling distance of 8 mm, leaving sufficient margin in real sceneries. The attention should be paid to the design of the secondary coil, whose parasitic resistance will cause tissue damage by excessive heating. The primary coil dimensions (Dout ) defines the effective radiation distance D:
Dout ≤ 2 √ 2D (8)
And there are mathematical relationships between two coupling coils [26]:
= dout − din dout + din
(9)
where din and dout are the inner and outer diameters of the coils, is a parameter called fill factor. is changed to 0 when the turns of the coil are present on the perimeter such as filament coils, while it is changed to 1 when the coil turns spiral to the center.
(Rout ,T ) 2−(Rout ,R )
2 = X 2 (10)
-0.5
0
0.5
1.5
2.5
5
8
10
dout
din
Figure 3: The coils simulation. (a) The coil models in HFSS. (b) The geometry of the circular planar coil. (c) The induc- tance simulation results of inductive coils.
k = Rout ,T
2Rout ,R 2√
2 + X 2) 3 (11)
where k is the coupling factor(0 ≤ k ≤ 1), Rout ,T and Rout ,R are the transmitting coil and receiving coil radius, respectively, X is the mutual distance of the above two coils. Based on equations (8-11), the coupling coils are optimized as follows:
Step 1: With a reasonable k(= 0.25) and X (= 8 mm), the rela- tionship between Rout ,T and Rout ,R can be obtained.
Step 2: The number of design variables can be reduced for sim- plicity through the relationship between the inner diameter and outer diameter of the coil [27]. In our design, din,T = 0.6dout ,T , din,R = 0.7dout ,R ,the corresponding fill factors: T = 25%,R = 18%.
Step 3: The initial values of the coil parameters can be obtained according to the above conditions.The performance of the primary coil and the secondary coil can be improved by sweeping differ- ent parameters in a wide range around their initial values. These parameters include line widthW , fill factor and diameter d .
Under the aforementioned considerations, the parameters of the coupling coils can be calculated through the iterative methods with HFSS tool. Fig. 3 and Table 1 show these parameters, which are used later in the circuit simulation.
GLSVSLI ’20, May 27–29, 2020, Beijing, China Siyao Zhu, Jian Zhao, Yongfu Li and Mingyi Chen
Cs
Table 1: Inductive Coils Parameters
Parameter Symbol Coil 1* Coil 2* Outer Diameter (mm) dout 13.12 9.96 Inner Diameter (mm) din 8.53 5.38
Fill Factor 0.21 0.3 Number of Turns N 5 5 Turn Spacing (mm) S 0.25 0.25
Conductor Width (mm) W 0.32 0.32 Inductance (µH) L 1.032 0.499
Parasitic Resistance () RP 0.482 0.404 Conductor Thickness (µm) t 35
Conductor Resistivity (n·m) ρ 17.2 Mutual Distance (mm) X 8 Coupling of Coefficient k 0.252 Link Frequency (MHz) ω 20
Coil 1*: Primary Coil. Coil 2*: Secondary Coil.
3.2 The Design of Internal Circuits Fig. 4 shows the systematic schematic of the power and data teleme- try circuit.
The top-left corner of Fig. 4 shows the BPSK modulation circuit. In the multiplexer (Mux) block, the data is synchronized by the falling edge of the Clk1 to avoid any glitches at the NAND output. The right plane of Fig. 4 shows the Costas loop circuit adopted
for data demodulation, which mainly consists of mixers, low-pass filters, and a phase-locked loop (PLL) including a loop filter and a quadrature voltage-controlled oscillator (VCO).
The working mechanism is illustrated as follows: The BPSK modulated signal (RFp ) is multiplied by quadrature phases from VCO respectively. The high-frequency components are filtered out with the low-pass filter, whereas the low-frequency components are sent to the mixer for phase detection. The mixer’s output is low- pass filtered with an active loop filter and then used to control the VCO frequency. Ring-VCO [28,29] based on cross-coupled inverters as shown in the lower-left corner is adopted. Its output is level- shifted up and then divided by two to ensure 50% duty-cycle.The open-loop gainGOL(s) of the Costas loop is shown in equation (12):
|GOL(s)| = KVCOKd
1 1 + sR4C4
(12)
where KVCO is VCO gain, Kd is the phase detector gain. Fig. 5 shows the Bode plots of the open-loop gain. The low-
frequency zero introduced by the active loop filter cancels VCO’s pole at zero frequency. To ensure the loop stability, the first non- dominant pole should be pushed to a higher frequency than the gain-bandwidth product (GBW) so that a sufficient phase margin can be guaranteed. Bode plots show that the GBW is 1MHz with a phase margin of 71°. The passive low pass filter (LPF) is used to filter the high-frequency components from the mixer. The cut-off frequency of LPF has a trade-off between the loop stability and
Power and Data Telemetry Circuit GLSVSLI ’20, May 27–29, 2020, Beijing, China
-100
-50
0
50
100
150
Figure 5: Open loop gain Bode plots of demodulated circuit.
ripple filtering capability. It can be a good compromise to set its cut- off frequency to twice the data rate. To recover the modulator data, a slicing comparator is required. The dynamic comparator with lower consumption and higher speed compared to the static comparator is adopted [30, 31]. The slicing clock is from the frequency divider following the VCO, which has a quadrature-phase to the carrier signal.4 EXPERIMENTAL RESULTS The power and data telemetry circuit has been implemented and simulated in a standard 350-nm CMOS process.
Fig. 6 shows the wireless transmission simulation results. The (b) panel is the current phase response of the load resistor at high/low input signal (Data). The vertical dash lines (V1-V2) present the load resistor current phase when data is 0; the vertical dash lines (V3-V4) show the load resistor current phase when data is 1, the simulation results indicate that the phase difference is equal to 180, as indicated in Section 2. Fig. 6 (c) and (d) panels represent the original data and demodulated data, respectively. The recovered carrier signal rClk1Q from the frequency divider is shown in Fig. 6-(e) panel, indicating the function of the Costas loop.
Fig. 7 shows the eye diagrams of the recovered signals, achieving 2.5 Mbps and 4 Mbps data transmission rate. The eye-openings are
-10
0
10
1
3
/V
Time/us
0
3.3V
rData
(c)
Clk1
rClk1Q
Figure 6: System simulation results. (a) Off–chip signal “Clk1”. (b) The current of load resistor. (c) Input signal “Data”. (d) Recovered data signal “rData”. (e) Recovered clock signal “rClk1Q ”.
1.66 V and 1.48 V, respectively, presenting a sufficient noise margin for the data recovery.
Table 2 is the comparison table with state-of-the-art. The circuits proposed in [16,25] are implemented using commercial off the shelf (COTS) components. Thanks to the proposed BPSK modulation scheme based on the adaptive duty-cycling BPSK modulated Class- E power amplifier and the demodulation circuit with the Costas loop, the design achieves a higher data rate, PTE as well as the figure of merit (FOM). Although the transmission power (4.5 dBm) is lower compared to the previous work, the normalized transmis- sion power is higher since lower power supply of Class-E power amplifier (1 V) is used in the design. The transmission power can be further extended by increasing the power supply under the same architecture.
5 CONCLUSION This paper proposes a power and forward data telemetry circuit for IMDs with a single pair coil. A power and data transmission link based on the adaptive duty-cycling BPSK modulated Class-E power amplifier has been proposed. Compared to the traditional ASK modulation, it has a higher data transmission rate and better immunity for noise. Moreover, the carrier and data are accurately recovered by the demodulator based on the Costas loop. The whole link has been implemented and simulated in a standard 350-nm CMOS process. The simulation shows the PTE and FOM of the proposed system are 53%, 600 pJ/bit, respectively, under a rate of 4 Mbps.
ACKNOWLEDGMENTS This work was supported in part by the National Key Research and Development Program of China under Grant No. 2019YFB2204500
0.25 0.5 0.75 1.0 1.25 1.5 1.70 0.5
1.0
1.5
2.0
2.5
Time/us
4Mbps 1.48 V
Figure 7: Eye diagrams of recovered signals. (a) 2.5Mbps data rate. (b) 4 Mbps data rate.
GLSVSLI ’20, May 27–29, 2020, Beijing, China Siyao Zhu, Jian Zhao, Yongfu Li and Mingyi Chen
Table 2: Comparison with Prior Work
Publication [16] [25] [32] [33] [34] This Work Data Source Measured Measured Measured Measured Simulation Simulation Link Type Power+Data Power+Data Data Power+Data Data Power+Data Modulation FSK ASK BPSK BPSK ASK BPSK Process COTS COTS 130 nm 800 nm 350 nm 350 nm
Carrier Freq.(MHz) 2&4 10 21 48 2 20 Data Rate (Mbps) 1 1 1.3125 3 0.02 2.5 4
PTE(%) 25 42∗ N/A N/A N/A 53∗∗
(Normalized TX Power)+(dBm/V2)
1.0 1.2 1.0 N/A N/A 4.3 4.5
FOM++(pJ/bit) N/A 4942 3960 N/A 10400 930 600 42∗: Without considering the driver buffer of Class-E. FOM++: (Demodulator power consumption)/(data rate). (Normalized TX power)+: (Transmitted power )/VDD2. 53∗∗: TX PTE, including the power consumption of the Class-E amplifier and the digital block .
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Abstract
3 Circuit Implementation
4 Experimental Results
Siyao Zhu, Jian Zhao, Yongfu Li and Mingyi Chen [email protected]
Department of Micro-Nano Electronics and MoE Key Lab of Artificial Intelligence, Shanghai Jiao Tong University, China
ABSTRACT Implantable medical microsystems need an efficient power and data transmission link. The demand for increasing the battery life requests for higher power transfer efficiency (PTE), whereas the increasing functionality of the implantable chip demands a higher data-rate. The traditional single-pair-of-coil link based on Amplitude-Shift keying (ASK) modulated Class-E amplifier tends to have limited immunity on the interference. In addition, due to the conflict on the quality factor (Q) between the power transmis- sion and data transmission band, high PTE and high data rates are difficult to achieve at the same time. This paper proposes a power and data transmission link based on the adaptive duty-cycling bi- nary phase-shift keying (BPSK) modulated Class-E amplifier. The Class-E works alternatively between two modes determined by two clocks with different duty-cycles. The variation of the duty-cycle modulates the phase of the carrier through the resonant networks of the Class-E amplifier. A low-power Costas Loop is adopted to efficiently synchronize the carrier and recover the data from an inductive received signal. The whole link has been implemented and simulated in a 350-nm CMOS process. The simulation shows under date-rate of 4 Mbps, the link achieves a PTE of 53% with an energy efficiency of 600 pJ/bit.
CCS CONCEPTS •Hardware→Very large scale integration design;Radio fre- quency and wireless circuits.
KEYWORDS Power and data transmission,Binary phase-shift keying (BPSK), Duty-cycle, Class-E Power Amplifier, Costas Loop.
ACM Reference Format: Siyao Zhu, Jian Zhao, Yongfu Li and Mingyi Chen. 2020. A 53%-PTE and 4-Mbps Power and Data Telemetry Circuit based on Adaptive Duty-cycling BPSK Modulated Class-E Amplifier. In GLSVSLI ’20: ACM Great Lakes Sym- posium on VLSI, July 27–29, 2020, Beijing, China. ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/XXXXXXX.XXXXXXX
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]. GLSVSLI ’20, May 27–29, 2020, Beijing, China © 2020 Association for Computing Machinery. ACM ISBN 978-1-4503-5700-5/18/06. . . $15.00 https://doi.org/10.1145/XXXXXXX.XXXXXXX
1 INTRODUCTION Various types of implanted medical devices (IMDs) have been pro- posed for different diseases, such as cochlear implants [1, 2], retinal prosthesis [3–6], and deep brain stimulators (DBS) [7, 8]. The wire- less link can be established between the inside and outside of the body thanks to the magnetic field, which enables wireless power and data telemetry through the link.
The wireless link based on two respective pairs of overlapping coils has been proposed in [9–11]. It has advantages of increasing the PTE and data transmission rate simultaneously by introducing different quality factor Q between the coils. However, the system with two coils is bulky, which unavoidably raises the risk of the implantation. In addition, due to the cross coupling between the power and the data colis, the whole system suffers from strong cross talk between two links. Besides, it is complicated to opti- mize the structural parameters of all the coils to achieve the best performance.
In [12–15], the system based on a single pair of coils has been proposed. Amplitude-shift keying (ASK) is commonly adopted for data modulation because of its simplicity of circuit implementation. However, the movement of the subjects with the IMDs will have a negative impact on the signal quality across the received coil [16]. Moreover, due to the intrinsic drawback of ASK, high PTE and high data-rate are difficult to achieve at the same time because of the conflict on the Q between the power transmission and data transmission band [10]. Higher Q is generally preferable for effi- cient power transfer, however, this leads to narrower transmission bandwidth and thus lowers data rate.
In prior work [17] of our team, the PSK modulated Class-E ampli- fier has been proposed for data modulation. Although the data can be transmitted through the Class-E amplifier, the PSK modulation completely destroys its optimal operation point, which tends to reduce the PTE significantly. In this paper, we present a new type of BPSK modulator based on the adaptive duty-cycling BPSK mod- ulated Class-E amplifier, which ensures the sub-optimal operation of the Class-E amplifier. Hence, the TX has higher PTE under a higher data-rate. At the same time, the BPSK demodulator [18, 19] is realized through a low-power Costas loop so that the total energy efficiency can be improved. Fig. 1 illustrates the application of the proposed circuit.
This paper is organized as follows: Section II explains the princi- ple of the phase modulator. The circuit implementation is shown in Section III. Experimental results are provided in Section IV and Section V concludes the paper.
Figure 1: Wireless Energy and Data Transmission Model.
Data
Clk1
Clk2
Vgate
1
2
3
4
Data
Vgate
Lrf
Cp
Cn
S0
M0
(a)
Data
0
MUX
0
1
Figure 2: (a) Block diagram of the proposed phase modula- tor and (b) phasemodulation by controlling the resonant fre- quency.
2 ADAPTIVE DUTY-CYCLING BPSK MODULATOR
Class-E power amplifiers (PAs) have been widely used due to its 100% PTE [20, 21] under ideal operation. However, the previous PSK [17] modulated Class-E amplifier deviates its optimal operation point so that the PTE decreases dramatically.
Fig. 2 (a) illustrates the schematic of the proposed modulator based on the typical Class-E PAs. Lrf is an RF choke inductor which supplies stable DC current to the resonant tanks. R1 is an equivalent resistor including the parasitic resistances of L1 and the reflected impedance from the secondary coil into L1. In this design, Clk1 and Clk2 are off-chip clock signals with 20-MHz frequency, whose duty-cycles are 56% and 10%, respectively. The duty-cycle control
circuit proposed in [22] can regenerate pre-set duty-cycle signal based on phase-locked-loop circuits or crystal oscillators from the same clock source.
The resonant frequency can be expressed by (1):
ωi = 1
(i = 1, 2, 3, 4) (1)
where the Ci is the total resonant capacitance of the resonant net- work.
For the circuit shown in Fig. 2(a), there can be four different resonant frequencies as follows, depending on the on/off state of M0 and switch S0.
State 1: Data=0, Clk1=1, S0 is off,M0 is on, the capacitor Cp is shorted, the total resonant capacitance C1 is equal to Cs.
State 2: Data=0, Clk1=0, S0 andM0 are both off, the total reso- nant capacitor C2 is the series combination of Cp and Cs.
State 3: Data=1, Clk2=1, S0 and M0 are both on, the capacitor Cp and Cn are both shorted, the total capacitor C3 is equal to Cs.
State 4: Data=1, Clk2=0, S0 is on, M0 is off, the total resonant capacitor C4 is Cs in series with the parallel combination of Cp and Cn.
As a result, the resonant frequencies adaptive to the data meets the following relationship as given by (2):
ω1 = ω3 < ω4 < ω2 (2)
In phase modulation/demodulation, data is encoded through modulating the phase of the primary coil current and recovered through detecting the corresponding changes of the phase on the secondary coil. As the carrier phase is the integral of angular fre- quency, it will be changed by changing resonance frequency under different transmission data, whereas the current amplitude of coil L1 will not be affected theoretically. According to (3) [23]:
Q = 2π Stored Enery
Dissipated Enery in Each Cycle (3)
The stored/dissipated energy in the magnetic field is proportional to the square of the coil current if other parameters are all kept constant. Hence, PSKmodulator canmodulate the data independent of the Q , in the prevention of the conflict on Q between the power transmission and data transmission band, and leading to higher PTE.
In terms of PSK, both QPSK and BPSK can be adopted. The QPSK modulation has higher PTE since only a slight deviation exists from the optimal operation of the Class-E PAs. However, the QPSK demodulator is complicated while consuming higher power and chip area. In contrast, the BPSK enables a demodulator with much lower consumption overhead at the cost of lower PTE. With the consideration of the demand for low-power and small-area IMDs, BPSK is chosen in this design. The value of the components should be carefully chosen as there is a trade-off between the PTE and the power consumption of the demodulation circuit.
Fig. 2 (b) shows the modulation process. Clk1 and Clk2 have the same frequency with different duty-cycles. The driving voltage Vate ofM0 is from eitherClk1 orClk2, selected by the transmitted data. At the same time, the data also adaptively changes the on/off state ofM0 an S0, which modulates the resonant capacitance and in turn changes the resonant frequency of the Class-E PAs as shown
Power and Data Telemetry Circuit GLSVSLI ’20, May 27–29, 2020, Beijing, China
by (1). By controlling the switch, the resonant frequency can be changed instantly while the phase of the coil current cannot be changed immediately. As shown in Fig. 2(b), the slopes of phase change represent the resonant frequencies. Hence, the current phase can be adjusted by choosing suitable resonant frequency. The points (A, B) represent the phases of coil L1 current whenClk1 falling edges are taken as the reference lines. When data is 0, the phase of the coil current is θ ; when data is 1, the phase of the coil current is φ, the BPSK modulation will be achieved when the difference between θ and φ is 180. This leads to the design of the values of T1, T3 and ωi as follows:
The phase of point A:
θ = ω1 ·T1 (4)
φ = ω3 ·T3 + ω4 · (T1 −T3) (5)
The phase is shifted from A to B:
φ − θ = π (6)
Substituting the above equations (4) and (5) into equation (6):
(ω4 − ω1) · (T1 −T3) = π (7)
The carrier frequency of 20 MHz is adopted in the design [17]. To ensure high PTE, the Class-E PAs are required to meet zero- voltage switching (ZVS) and zero-derivative switching (ZDS) con- ditions [24]. With these conditions, the value of Cs (396 pF) and Cp (35 pF) can be calculated under a fixed coil L1 inductance value (1 µH). The value of Cn (2 pF) can be determined afterward by choosing a suitable value of ω4 that meets (2). It is noteworthy that in contrast to [17], where it is impossible to achieve zero turning on condition due to the coexistence of deceleration and acceleration, the proposed adaptive duty-cycling BPSK modulated Class-E Power amplifier avoids such issue and hence achieves higher PTE.
3 CIRCUIT IMPLEMENTATION 3.1 Inductive Coils Design This Section depicts a specific inductive coils design procedure with the HFSS electromagnetic simulation tool. As references [16, 25], the air gap between the primary coil and the secondary coil is 6 mm. Hence, in this design, we aim to design a coil with a coupling distance of 8 mm, leaving sufficient margin in real sceneries. The attention should be paid to the design of the secondary coil, whose parasitic resistance will cause tissue damage by excessive heating. The primary coil dimensions (Dout ) defines the effective radiation distance D:
Dout ≤ 2 √ 2D (8)
And there are mathematical relationships between two coupling coils [26]:
= dout − din dout + din
(9)
where din and dout are the inner and outer diameters of the coils, is a parameter called fill factor. is changed to 0 when the turns of the coil are present on the perimeter such as filament coils, while it is changed to 1 when the coil turns spiral to the center.
(Rout ,T ) 2−(Rout ,R )
2 = X 2 (10)
-0.5
0
0.5
1.5
2.5
5
8
10
dout
din
Figure 3: The coils simulation. (a) The coil models in HFSS. (b) The geometry of the circular planar coil. (c) The induc- tance simulation results of inductive coils.
k = Rout ,T
2Rout ,R 2√
2 + X 2) 3 (11)
where k is the coupling factor(0 ≤ k ≤ 1), Rout ,T and Rout ,R are the transmitting coil and receiving coil radius, respectively, X is the mutual distance of the above two coils. Based on equations (8-11), the coupling coils are optimized as follows:
Step 1: With a reasonable k(= 0.25) and X (= 8 mm), the rela- tionship between Rout ,T and Rout ,R can be obtained.
Step 2: The number of design variables can be reduced for sim- plicity through the relationship between the inner diameter and outer diameter of the coil [27]. In our design, din,T = 0.6dout ,T , din,R = 0.7dout ,R ,the corresponding fill factors: T = 25%,R = 18%.
Step 3: The initial values of the coil parameters can be obtained according to the above conditions.The performance of the primary coil and the secondary coil can be improved by sweeping differ- ent parameters in a wide range around their initial values. These parameters include line widthW , fill factor and diameter d .
Under the aforementioned considerations, the parameters of the coupling coils can be calculated through the iterative methods with HFSS tool. Fig. 3 and Table 1 show these parameters, which are used later in the circuit simulation.
GLSVSLI ’20, May 27–29, 2020, Beijing, China Siyao Zhu, Jian Zhao, Yongfu Li and Mingyi Chen
Cs
Table 1: Inductive Coils Parameters
Parameter Symbol Coil 1* Coil 2* Outer Diameter (mm) dout 13.12 9.96 Inner Diameter (mm) din 8.53 5.38
Fill Factor 0.21 0.3 Number of Turns N 5 5 Turn Spacing (mm) S 0.25 0.25
Conductor Width (mm) W 0.32 0.32 Inductance (µH) L 1.032 0.499
Parasitic Resistance () RP 0.482 0.404 Conductor Thickness (µm) t 35
Conductor Resistivity (n·m) ρ 17.2 Mutual Distance (mm) X 8 Coupling of Coefficient k 0.252 Link Frequency (MHz) ω 20
Coil 1*: Primary Coil. Coil 2*: Secondary Coil.
3.2 The Design of Internal Circuits Fig. 4 shows the systematic schematic of the power and data teleme- try circuit.
The top-left corner of Fig. 4 shows the BPSK modulation circuit. In the multiplexer (Mux) block, the data is synchronized by the falling edge of the Clk1 to avoid any glitches at the NAND output. The right plane of Fig. 4 shows the Costas loop circuit adopted
for data demodulation, which mainly consists of mixers, low-pass filters, and a phase-locked loop (PLL) including a loop filter and a quadrature voltage-controlled oscillator (VCO).
The working mechanism is illustrated as follows: The BPSK modulated signal (RFp ) is multiplied by quadrature phases from VCO respectively. The high-frequency components are filtered out with the low-pass filter, whereas the low-frequency components are sent to the mixer for phase detection. The mixer’s output is low- pass filtered with an active loop filter and then used to control the VCO frequency. Ring-VCO [28,29] based on cross-coupled inverters as shown in the lower-left corner is adopted. Its output is level- shifted up and then divided by two to ensure 50% duty-cycle.The open-loop gainGOL(s) of the Costas loop is shown in equation (12):
|GOL(s)| = KVCOKd
1 1 + sR4C4
(12)
where KVCO is VCO gain, Kd is the phase detector gain. Fig. 5 shows the Bode plots of the open-loop gain. The low-
frequency zero introduced by the active loop filter cancels VCO’s pole at zero frequency. To ensure the loop stability, the first non- dominant pole should be pushed to a higher frequency than the gain-bandwidth product (GBW) so that a sufficient phase margin can be guaranteed. Bode plots show that the GBW is 1MHz with a phase margin of 71°. The passive low pass filter (LPF) is used to filter the high-frequency components from the mixer. The cut-off frequency of LPF has a trade-off between the loop stability and
Power and Data Telemetry Circuit GLSVSLI ’20, May 27–29, 2020, Beijing, China
-100
-50
0
50
100
150
Figure 5: Open loop gain Bode plots of demodulated circuit.
ripple filtering capability. It can be a good compromise to set its cut- off frequency to twice the data rate. To recover the modulator data, a slicing comparator is required. The dynamic comparator with lower consumption and higher speed compared to the static comparator is adopted [30, 31]. The slicing clock is from the frequency divider following the VCO, which has a quadrature-phase to the carrier signal.4 EXPERIMENTAL RESULTS The power and data telemetry circuit has been implemented and simulated in a standard 350-nm CMOS process.
Fig. 6 shows the wireless transmission simulation results. The (b) panel is the current phase response of the load resistor at high/low input signal (Data). The vertical dash lines (V1-V2) present the load resistor current phase when data is 0; the vertical dash lines (V3-V4) show the load resistor current phase when data is 1, the simulation results indicate that the phase difference is equal to 180, as indicated in Section 2. Fig. 6 (c) and (d) panels represent the original data and demodulated data, respectively. The recovered carrier signal rClk1Q from the frequency divider is shown in Fig. 6-(e) panel, indicating the function of the Costas loop.
Fig. 7 shows the eye diagrams of the recovered signals, achieving 2.5 Mbps and 4 Mbps data transmission rate. The eye-openings are
-10
0
10
1
3
/V
Time/us
0
3.3V
rData
(c)
Clk1
rClk1Q
Figure 6: System simulation results. (a) Off–chip signal “Clk1”. (b) The current of load resistor. (c) Input signal “Data”. (d) Recovered data signal “rData”. (e) Recovered clock signal “rClk1Q ”.
1.66 V and 1.48 V, respectively, presenting a sufficient noise margin for the data recovery.
Table 2 is the comparison table with state-of-the-art. The circuits proposed in [16,25] are implemented using commercial off the shelf (COTS) components. Thanks to the proposed BPSK modulation scheme based on the adaptive duty-cycling BPSK modulated Class- E power amplifier and the demodulation circuit with the Costas loop, the design achieves a higher data rate, PTE as well as the figure of merit (FOM). Although the transmission power (4.5 dBm) is lower compared to the previous work, the normalized transmis- sion power is higher since lower power supply of Class-E power amplifier (1 V) is used in the design. The transmission power can be further extended by increasing the power supply under the same architecture.
5 CONCLUSION This paper proposes a power and forward data telemetry circuit for IMDs with a single pair coil. A power and data transmission link based on the adaptive duty-cycling BPSK modulated Class-E power amplifier has been proposed. Compared to the traditional ASK modulation, it has a higher data transmission rate and better immunity for noise. Moreover, the carrier and data are accurately recovered by the demodulator based on the Costas loop. The whole link has been implemented and simulated in a standard 350-nm CMOS process. The simulation shows the PTE and FOM of the proposed system are 53%, 600 pJ/bit, respectively, under a rate of 4 Mbps.
ACKNOWLEDGMENTS This work was supported in part by the National Key Research and Development Program of China under Grant No. 2019YFB2204500
0.25 0.5 0.75 1.0 1.25 1.5 1.70 0.5
1.0
1.5
2.0
2.5
Time/us
4Mbps 1.48 V
Figure 7: Eye diagrams of recovered signals. (a) 2.5Mbps data rate. (b) 4 Mbps data rate.
GLSVSLI ’20, May 27–29, 2020, Beijing, China Siyao Zhu, Jian Zhao, Yongfu Li and Mingyi Chen
Table 2: Comparison with Prior Work
Publication [16] [25] [32] [33] [34] This Work Data Source Measured Measured Measured Measured Simulation Simulation Link Type Power+Data Power+Data Data Power+Data Data Power+Data Modulation FSK ASK BPSK BPSK ASK BPSK Process COTS COTS 130 nm 800 nm 350 nm 350 nm
Carrier Freq.(MHz) 2&4 10 21 48 2 20 Data Rate (Mbps) 1 1 1.3125 3 0.02 2.5 4
PTE(%) 25 42∗ N/A N/A N/A 53∗∗
(Normalized TX Power)+(dBm/V2)
1.0 1.2 1.0 N/A N/A 4.3 4.5
FOM++(pJ/bit) N/A 4942 3960 N/A 10400 930 600 42∗: Without considering the driver buffer of Class-E. FOM++: (Demodulator power consumption)/(data rate). (Normalized TX power)+: (Transmitted power )/VDD2. 53∗∗: TX PTE, including the power consumption of the Class-E amplifier and the digital block .
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Abstract
3 Circuit Implementation
4 Experimental Results