a 500mhz mp dll clock generator for a 5gbps backplane transceiver in 0.25um cmos

7/27/2019 A 500MHz MP DLL Clock Generator for a 5Gbps Backplane Transceiver in 0.25um CMOS

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ISSCC 2003 / SESSION 26 / EMBEDDED AND DIGITAL SYSTEMS / PAPER 26.4

26.4 A 500MHz MP/DLL Clock Generator for a 5Gb/sBackplane Transceiver in 0.25m CMOS

Gu-Yeon Wei1, John T. Stonick2, Dan Weinlader2, Jeff Sonntag2,Shawn Searles2

1Harvard University, Cambridge, MA2Accelerant Networks, Beaverton, OR

The desire for higher network bandwidth drives the developmentof high-speed data communication links for backplanes inrouters and switch boxes. Backplane transceivers require clockgeneration with low jitter characteristics to ensure robust oper-ation. This paper describes the implementation of the 500MHzsystem clock generator for a 5Gb/s backplane transceiver designdescribed in [1] and a follow-on 5x5Gb/s version. The clock gen-erator multiplies a 125MHz reference clock to 500MHz utilizinga block that is configured to operate either as a multiplyingphase-locked loop (MPLL) or a multiplying delay-locked loop(MDLL) depending on the noise characteristics of the off-chipreference clock signal. For a low-jitter input reference clock, theMDLL configuration is chosen since it avoids the clock jitteraccumulation of an oscillator. However, under noisy conditions,the MPLL configuration is chosen to filter the input clock noise.

Figure 26.4.1 presents a block diagram of the loop that is config-ured as either an MPLL or MDLL through a select signal(sel_mode). In MPLL mode, the delay elements are configured asa ring oscillator by fixing the multiplexer to always select the fedback output of the delay line. In MDLL mode, a Mux Controlblock periodically flips between the multiplexers two inputs theinput ref clock or delay-line output. Its operation is similar to themultiplying DLLs described in [2] and [3]. A divide-by-fourcounter is also used to select and pass one of four clock edges outof the voltage-controlled delay lines (VCDL) to the phase-fre-quency detector (PFD).

The delay elements are nearly full-swing pseudo-differentialcells, slightly modified versions in [4]. As shown in Fig. 26.4.2,

modifications are made to reduce VCO gain and to control thetuning range. First, to both reduce size requirements for the loopfilter capacitor and sensitivity to noise in the signal path of theloop, the cells delay is controlled by split tuning the current in aset of PMOS current sources. The current sources on each sideare split into two devices (e.g., M1a andM1b) with a 3:1 widthratio. The larger device is controlled through a lower-bandwidthcoarse tuning path while the smaller device is controlled througha higher-bandwidth fine-tuning path. Split tuning reduces the

VCOs gain by 4. Second, a current source (M3), controlled by aprocess monitoring circuit, is added. At the fast corner, current isreduced to weaken the cross-coupling strength of the PMOS pairand decrease the oscillation frequency. The opposite occurs forthe slow corner.

Thesel_mode signal also configures the loop filter to incorporate

a resistor (for zero compensation) and capacitor for MPLL modeor just a capacitor for MDLL mode. To avoid the up and downcurrent mismatches in conventional single-ended charge-pumpcircuits, the high-speed differential charge pump (CP) shown inFig. 26.4.3 is employed. When the UP andDNsignals out of thePFD are both low or high, equal 50A current exist in both sidesof the CP. When either input is high and the other is low, the dif-ferential pair steers a 50A differential current onto the loop fil-ter. The loop filter is realized using Metal-Insulator-Metal (MIM)capacitors, poly Si resistors, and a set of switches. In MPLLmode, the switches are configured to create an RC loop filter. InMDLL mode, the resistor is switched out and the capacitors areconnected in series to reduce the filter cap by a factor of 4 andincrease the MDLLs bandwidth.

Although the PFD and fully differential CP are ideally balanced,device mismatches, primarily due to threshold voltage offsets, andfinite output impedance create imbalances. The continuous currentin this CP exacerbates these effects. In MPLL mode, the imbalancecreates a static phase error, which is tolerated by the system.However, in MDLL mode, this phase error accumulates every fourcycles and creates a tone in the output clock signal at the referenceclock rate. To combat this error, a low-bandwidth secondary loop isadded to compensate for current mismatches. The compensation

loop is digital, comprising a bang-bang phase detector and an accu-mulator to implement an integrator with infinite dc gain. The out-put of the integrator controls a current DAC that leaks current fromeither side of the differential CP.

Lastly, the CP output, which is a differential signal, sets theVCDL delay. However, the delay elements are controlled with sin-gle-ended control signals. Hence, as shown in Fig. 26.4.3, a differ-ential-to-single-ended (D2S) voltage converter required. Theamplifier has two sets of differential inputs: One set is in a unity-gain configuration driven by a reference voltage (VREF). The secondset comes from the CP and skew the output about VREF. To accom-modate a range of operating frequencies and process corners, theD2S is self-biased by driving VREF with a filtered version of the out-put. This manifests itself as an additional integrator and zero atthe filter cut-off frequency. Therefore, the filter cut-off must be low

enough to guarantee stability. The D2S also introduces a low-passfilter in the signal path and its bandwidth must be set well abovethe unity-gain frequency of the loop. The output of the D2S drivesthe fine control of the split-tuned delay elements while the filteredversion, VREF, drives the coarse tuning control. In lock, both controlvoltages drive to a common voltage and the CPs differential out-put approaches zero to mitigate output impedance effects.

Figure 26.4.4, presents the jitter histogram plots of the MP/DLLmeasurements from a production 5x5Gb/s transceiver chip in bothMPLL and MDLL modes. One of five transmitters is configured toput out a regular clock pattern while the other links transmittedand received random 5Gb/s data. A low-noise reference clock leadsto slightly lower jitter in MDLL mode. However, when high fre-quency noise (15MHz) of varying amplitudes is injected into theclock reference, the resulting root-mean-square (rms) jitter mea-

surements in Fig. 26.4.5 show that the MPLL provides noise fil-tering to reject the added noise as opposed to the all-pass natureof the MDLL. Lastly, Fig. 26.4.6 presents the MDLLs output clocksignal with and without CP mismatch compensation enabled.Without compensation (and with the oscilloscope triggered from a250MHz source), two distinct clock edges are seen arising from thephase offset induced by mismatches (measured as 81ps). Withcompensation enabled, the secondary loop successfully eliminatesthis phase offset.

The MP/DLL is fabricated in a 0.25m triple-well TSMC CMOSprocess, measures 420 x 500m2 in area, and consumes approxi-mately 28mW under normal operation from a 2.5V supply. Giventhe uncertainty of input clock source fidelity in real systems, theexperimentally measured results suggest the MPLL as thedefault configuration for most cases.

AcknowledgementsThe authors would like to thank J. Gorecki, U.-K. Moon and Y. Yang fortheir invaluable advice, analog circuit design contributions, and initialanalysis of loop dynamics and noise. We are also grateful to A. Sengir forlayout and G. Lemire for test measurements.

References[1] J. Sonntag, et al, An Adaptive PAM-4 5Gb/s Backplane Transceiver in0.25mm CMOS, CICC, 2002.[2] R. Farjad-Rad, et al, A 0.2-2GHz 12mW Multiplying DLL for Low-Jitter Clock Synthesis in Highly-Integrated Data-Communication Chips,

ISSCC Dig. Tech. Papers, pp. 76-77, 2002.[3] A. Waizman, A Delay Line Loop for Frequency Synthesis of De-Skewed Clock,ISSCC Dig. Tech. Papers, pp. 298-299, 1994.[4] S.H. Wang, et al, A 500-Mb/s Quadruple Data Rate SRAM InterfaceUsing a Skew Cancellation Technique,J. Solid State Circuits, April 2001.

2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 2003 IEEE


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ISSCC 2003 / February 12, 2003 / Salon 10-15 / 3:15 PM

Figure 26.4.1: MP/DLL block diagram. Figure 26.4.2: Modified pseudo-differential delay element.

Figure 26.4.3: Differential CP, loop filter, and D2S block schematics.

Figure 26.4.5: Measured MP/DLL rms jitter vs. added input noise. Figure 26.4.6: Measured MDLL.

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Figure 26.4.4: 500-MHz clock jitter histograms in MPLL and MDLLmodes of operation.

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gure 26.4.3: Differential CP, loop filter, and D2S block schematics.



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gure 26.4.4: 500-MHz clock jitter histograms in MPLL and MDLL modes of operation.



gure 26.4.5: Measured MP/DLL rms jitter vs. added input noise.

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a 500mhz mp dll clock generator for a 5gbps backplane transceiver in 0.25um cmos

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