a 2.9-30.3ghz fourth-harmonic voltage-controlled oscillator in 130nm sige bicmos technology yang lin...
TRANSCRIPT
A 2.9-30.3GHz Fourth-Harmonic
Voltage-Controlled Oscillator in 130nm SiGe BiCMOS
Technology
Yang Lin and David E. KoteckiElectrical and Computer Engineering Department
University of Maine, USA
Dec.12-15, 2010 1
17th IEEE International Conference on Electronics, Circuits and Systems
Outline
Voltage-controlled oscillator (VCO)Wide-tuning VCO applicationsPrevious work on the state-of-the-art wide-
tuning VCOsDesign & Post-layout simulation of this work
Dec.12-15, 2010 2
17th IEEE International Conference on Electronics, Circuits and Systems
Voltage-Controlled Oscillator (VCO)
Dec.12-15, 2010 3
17th IEEE International Conference on Electronics, Circuits and Systems
Vdd
Gnd
Vtune
Vtune controls output frequencyVCO
Load
Gnd
fmin
fmax
Wide-tuning VCO applications
RadarBroadbandCommunication
Dec.12-15, 2010 4
17th IEEE International Conference on Electronics, Circuits and Systems
RemoteSensing
State-of-the-art wide-tuning VCOs
The widest tuning range in the 130nm ring VCOs reported
Frequency (GHz)
Topology Technology
1-9 Two-stage VCO CMOS 130nm
1.82-10.18 Two-stage digitally controlled
CMOS 130nm
3-10 Digitally-controlled ring CMOS 90nm
1-10 Four-stage VCO CMOS 90nm
0.23-6.3 Relaxation VCO CMOS 90nm
0.1-65.8 Triple-push with lumped devices
CMOS 90nm
3-11 Coupled two-stage CMOS 180nm
1.25-13.66 QVCO + two stages XOR AlGaAs/GaAs
2.9-30.3 QVCO + XOR + Push-push frequency doubler
BiCMOS SiGe 130nm
Dec.12-15, 2010 5
17th IEEE International Conference on Electronics, Circuits and Systems
This work
Dec.12-15, 2010 6
17th IEEE International Conference on Electronics, Circuits and Systems
For the XOR, differential inputs Ap and An (0o delay @ frequency f0 ) XOR differential inputs Bp and Bn (90o delay @ frequency f0) = differential outputs Zp and Zn (frequency 2f0 )
Base-collector-connected (level-shifting) NPN transistors: decrease the XOR input voltages for Bp and Bn
0
1
Architecture
Zp
Zn
ApAn
50 Ohm
ApAn
Bp’ Bn’
Zp
Znout
f0 2f0 4f02.9-30.3GHz1.45-15.15GHz0.725-7.575GHz
Ring Quadrature
VCO
BiCMOS Gilbert XORBp
Bn
Push-push frequency doubler
Ring Quadrature VCO (QVCO)
Gate width/length (µm)Buffer: Common source (amplified output) ‘Vctrl’ is high: low-frequency mode, T1 & T4 close to ‘off’, T2 & T3 provide most currents‘Vctrl’ achieves a specific high value, the oscillation freq. keeps the same‘Vctrl’ is low: high-frequency mode, |Vgs| of T1 & T4 increases, current and freq. boostIncreasing ‘Vdd’ boosts the output frequency
Dec.12-15, 2010 7
17th IEEE International Conference on Electronics, Circuits and Systems
Delay Cell
outp
outn
inp
inn
Delay Cell
outp
outn
inp
inn
Buffer
Buffer
Buffer
Buffer
0o
90o
180o
270o
Ap
An
Bp’
Bn’Delay cell
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems 8
BiCMOS Gilbert XOR
Logic part, Emitter followers & Current sourceDelays of Ap, An, Bp and Bn are 0o, 180o, 90o and 270o
Bp & Bn are ~0.7V lower than Ap & AnZp and Zn are differential outputsBiCMOS XOR outperforms CMOS XOR: high freq. & differential outputs CMOS XOR: up to ~5.5GHz input freq.
Emitter followers as buffers
Current Source
Logic Part
A B A XOR B
Ap<An(0)
Bp<Bn(0)
Zp<Zn(0)
Ap<An(0)
Bp>Bn(1)
Zp>Zn(1)
Ap>An(1)
Bp<Bn(0)
Zp>Zn(1)
Ap>An(1)
Bp>Bn(1)
Zp<Zn(0)
AC
VL
out
BE iV v
L/2
Push-push frequency doubler
Dec.12-15, 2010 9
17th IEEE International Conference on Electronics, Circuits and Systems
2 3
0
1 ...! 2! 3!
nx
n
x x xe x
n
( )
BE i BE
T T
V v V
V Vc c C Si I I I e e
2 3 4
2 3 4( ...)
2 6 24
BE
T
Vi i i iVc ST T T T
v v v vi I e
V V V V
for all x)
(
BE i
T
V v
Vc SI I e
BE
T
V
VC SI I e Half-circuit
Half-circuit model
2 3 4
2 3 4( ...)
2 6 24
BE
T
Vi i i iVc ST T T T
v v v vi I e
V V V V
Schematic
L
B C
E
πriv or+
-2
Ljci
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems 10
2 4
2 4
2 4 2 4 40 0 0 0 0
2 4 2 4 4
2 ( ...)2 24
( ...) ( ...) cos(2 2 ) ( ...) cos(4 4 )2 32 2 24 96
BE
T
BE
T
Vi iVc c ST T
V
VST T T T T
v vi i I e
V V
v v v v vI e
V V V V V
0cos( )iv v
Doubled frequency dominates !!
Zp & Zn out-of-phase: odd harmonics cancel, even harmonics add
2 20
1[1 cos(2 2 )]
2iv v
L
2 1 2 1 0n ni iv v 2 2 22n n ni i iv v v
0 0cos( ) cos( )i iv v v v Assuming
4 40
1 3 1[ 2cos(2 2 ) cos(4 4 )]
4 2 2iv v
Push-push frequency doubler (continued)
Microchip Layout
Size: 750µm×500µm
The ground & power planes are not shown for clarity.
Dec.12-15, 2010 11
17th IEEE International Conference on Electronics, Circuits and Systems
500µm
750µm
Vbuffer
Vctrl
Vdd!
Vxor
VL
out
Gnd!
QVCO
XOR
Push-push frequency doubler
Post-layout simulation resultsOscillation frequency
Dec.12-15, 2010 12
17th IEEE International Conference on Electronics, Circuits and Systems
30.3GHz
2.9GHz
Tuning range = 165%
VCO transient output at 30.3GHz(into a 50Ω load)
•Non-ideal 4th-harmonic output
•A small 2nd-harmonic signal still exists due to the incomplete cancellation of Zp and Zn signals
•Peak-peak voltage amplitude ~20mV
Dec.12-15, 2010 13
17th IEEE International Conference on Electronics, Circuits and Systems
4th-harmonic output power spectruminto a 50Ω load
30.3 GHz, -33.5 dBm
The rejections 23.5dB @7.575GHz8dB @15.15GHz12.5dB @22.725GHz
@30.3 GHz, Dissipated power: 34.2 mW, Output power: -33.5 [email protected] GHz, Dissipated power: 32.89 mW, Output power: -56.5 dBm
Dec.12-15, 2010 14
17th IEEE International Conference on Electronics, Circuits and Systems
Phase Noise (PN) versus offset frequency
At 10MHz offset frequency,PN= -86.04 dBc/Hz @ 30.3GHz oscillation frequencyPN= -102.2 dBc/Hz @ 2.9GHz oscillation frequency
Dec.12-15, 2010 15
17th IEEE International Conference on Electronics, Circuits and Systems
30.3GHz oscillation frequency, -86.04 dBc/Hz @10MHz offset frequency
Conclusions
Dec.12-15, 2010 16
17th IEEE International Conference on Electronics, Circuits and Systems
Topology A ring QVCO + An XOR + A push-push frequency doubler
Performance The widest tuning range in the 130nm ring VCOs reported
Tuning Range (GHz) 2.9 to 30.3 (165%)
Dissipated Power (mW) 34.2 @ 30.3GHz, 32.89 @ 2.9GHz
Output Power to a 50Ω load (dBm)
-33.5 @ 30.3GHz, -56.5 @ 2.9GHz
Phase noise @ 10MHz offset (dBc/Hz)
-86.04 @ 30.3GHz, -102.2 @ 2.9GHz
Microchip Area 750µm×500µm
Thank you very much!Thank you very much!
Dec.12-15, 2010 17
17th IEEE International Conference on Electronics, Circuits and Systems