a 1.25-gb/s digitally-controlled dual-loop clock and data recovery circuit with improved effective...

A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Improved Effective Phase Resolution

Chang-Kyung Seong1), Seung-Woo Lee2), and Woo-Young Choi1)

1)Department of Electronic and Electrical EngineeringYonsei University

2)Switching Technology TeamElectronics and Telecommunications Research Institute

High-Speed Circuits and Systems Lab. Yonsei Univ.

Contents

Introduction Conventional Dual-Loop CDR and Problems Proposed Dual-Loop CDR Simulation and Experimental Results Chip summary Conclusion


Introduction (1)

Multi-channel application (e.g. Switch) Dozens ~ Hundreds of CDRs integrated in single die

Requirements for CDR Small die area Low power consumption Robustness to noise coupled from adjacent blocks

Switch Core Logics

Tx / Rx for each channel

Switch Core Logics


Introduction (2)

CDR #1

Padexternal reference clock

Data#1

Data#2

Data#3

Data#4Retimed Data #4

Recovered Clock #4

Retimed Data #3Recovered Clock #3



Synthesized Reference Clock

CDR #2

CDR #3

CDR #4

Ref. PLL

Dual-loop CDR Shared Reference PLL Each CDR cores using phase interpolator

• No jitter accumulation• Digital control - no loop filter, robustness to noise


Conventional Digitally-Controlled Dual-Loop Structure

Phase Controller

Bang-BangPhase Detector

Phase Selection

Phase Interpolator

Multi-Phase Reference Clock from PLL

Data in.

PFD CP

VCO

LF

/M

External Reference ClockRef. PLL

CDR core

Two Selected Phases


Reference Clock from PLL


Phase Controller


Phase Selection

Phase Interpolator

Data in.

PFD CP

VCO

LF

/M


CDR core

Two Selected Phases

Phase Selection

Phase Interpolator

PhaseInterpolated



RetimedData

RecoveredClock

UP/DN

Phase Controller


Phase Selection

Phase Interpolator

Reference Clock from PLL

Data in.

PFD CP

VCO

LF

/M


CDR core

Two Selected Phases


UP

DN


Effect of Phase Resolution

Jitter Generation Quantization error

• Digitally-Controlled CDR generates “discontinuous phase”

Jitter generation 1 / Phase Resolution∝

< Behavioral Simulation using CPPSIM* >

Quantization error

* M. H. Perrott, “Fast and accurate behavioral simulation of fractional-N synthesizers and other PLL/DLL circuits,” Design Automation Conference, pp.498-503, Jun. 2002.


Effect of Phase Resolution

Jitter Suppression and Frequency Offset Tracking Higher (more fine) phase resolution

• Smaller phase steps

• Narrower Loop Bandwidth

• More jitter rejection and Slower offset tracking

Phase resolution

Jitter generation

Jitter suppression

Frequency offset tolerance

∴


Limit of Phase Resolution in Phase Interpolator

Two control methods Binary-weighted code

• 2N levels, Simple but Phase overshoot

Thermometer code• N+1 levels, Complex but no Phase overshoot

,where N = bit width of control word

< Phase overshoot when large current sources are instantly turned on>

Difficult to increase phase resolution of PI higher than 16-level, or 4-bit.∴


Design Goals

Achieving sufficiently high phase resolution with little additional power consumption and die area

By using only 4-phase reference clocks and 16-level thermometer coded PI


Proposed Structure

Digitally-Controlled Delay Buffer (DCDB) is inserted for higher phase resolution

Phase Controller


Phase Interpolator

Digitally-ControlledDelay Buffer

Up/DownFilter

4-Phase Reference Clock from PLL

Data in.

RecoveredClock

RetimedData 2:1 MUX 2:1 MUX


Digitally-Controlled Delay Buffer

Current-starved inverter, or buffer Linearly variable delay for control codes

Digitally-ControlledDelay Buffer

Control Code (2-bit)

InputClock

DelayedClock

Input Clock

Delayed Clock

Adjacent interpolated phases


Enhancement of Phase Resolution

4X higher phase resolution by combining PI and DCDB

Ntotal phase = Nreference phase × NPI resolution × NDCDB resolution

= 4-level × 16-level × 4-level = 256-level (8-bit)

Interpolatedphase

Delayedphase

Interpolated phases


Enhancement of Phase Resolution

4X higher phase resolution by combining PI and DCDB

Interpolatedphase

Delayedphase

Ntotal phase = Nreference phase × NPI resolution × NDCDB resolution

= 4-level × 16-level × 4-level = 256-level (8-bit)

Interpolated phases


Delay Error of DCDB

Interpolatedphase

Delayedphase

Interpolatedphase

Delayedphase

Negative error (shorter delay than desired one)

Positive error (longer delay than desired one)


Delay Error of DCDB

Interpolatedphase

Delayedphase

Interpolatedphase

Delayedphase

Negative error (Shorter delay than desired one)

Positive error (Longer delay than desired one)


Sensitivity - Jitter Generation vs. Delay Error of DCDB

Behavioral simulation - CPPSIM, Circuit-level simulation - HSPICE Relatively flat jitter generation for wide range of DCDB error Why?

Effect of enhanced phase resolution > Effect of locally wrong phase movements


Die Photo

< Die Photo >

255㎛

165㎛


Experiment – Jitter vs. Delay error of DCDB

DCDB error = -50% DCDB error = 0% DCDB error = +50%

Measured waveform of recovered clock at 200ppm frequency offset

(-50%) (0%) (+50%)


Experiment - Jitter Suppression

27-1 PRBS transmitted through 2m PCB trace and 3.5m cable. In 200ppm frequency offset

< Transmitted eye pattern > < Retimed data of CDR >

114.3psP-P

424psRMS

38.89 psP-P

212 psRMS


Summary of Prototype Chip

Process

Supply

Data Rate

Offset Tolerance

Power Consumption

0.18 ㎛ CMOS

17.8mW (CDR core)

2.0V

1.25-Gb/s

±400ppm

Die Area (CDR core) 255×165 ㎛ 2


Conclusion

A novel method to enhance phase resolution is proposed.

By combining PI and DCDB, phase resolution can be enhanced with little additional power consumption and die area.

In both simulations and chip measurement, jitter performance is not sensitive to delay error of DCDB.


Thank You !!

a 1.25-gb/s digitally-controlled dual-loop clock and data recovery circuit with improved effective...

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