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9/26/2016 IMS2015 | IEEE International Microwave Symposium | Sunday Workshop Descriptions

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Sunday Workshop Descriptions

WSA

Session: WSA RF Interference Mitigation TechniquesChair: Ranjit Gharpurey, Univ. of Texas at AustinCoChair: Chris Rudell, Univ. of WashingtonAbstract: This fullday workshop will consist of speakers that

address a wide range of problems related totransceiver interference management andsuppression. Topics will include general techniques toimprove receiver selectivity and reduce transmitterunwanted spurious spectrum. Speakers will come froma diverse set of backgrounds which include system,circuit, and technology design all with the goal ofinterference mitigation either through filtering orcancellation techniques. Presentations will focus ontransceiver circuit design to enhance linearity,dynamic range, improve synthesizer phase noise, andcancellation methods, all for improved selectivityperformance. Other topics which address emergingareas that attempt to improve overall spectralefficiency by realizing fullduplex systems capable ofsimultaneous transmit and receive (STARS) on thesame frequency are also discussed. In addition, somespeakers will focus on new MEMs technologies toimprove transceiver interference mitigation. Furtherpresentations on system/networking strategies relatedto integrating radios in the context of interferencemitigation will be given.

WSA1 ElectricalBalance Duplexing for RF SelfInterference Cancellation to Enable InBandFullDuplexBarend van Liempd; IMECInband full duplex is a relatively new communication paradigmwhere the TX and RX operate at the same time, using the samespectral resources. In this case, the local TX causes socalled selfinterference at exactly the same frequency as the wanted signaland with much higher magnitude than the wanted signal. Toenable such wireless links, the self interference must becancelled, suppressed or filtered at various stages throughout theRX chain.This talk discusses electrical balance duplexers as part of thesolution, providing high self interference cancellation directly atRF frequencies, thereby severely reducing receiver constraints.These duplexers mimic an antenna's impedance using an on chiptunable dummy impedance to ensure destructive cancellation ofthe self interference at the RX port. Systemlevel specificationsas well as design techniques are discussed, to give insight intoboth current state of the art and on going research on thispromising technique.

WSA2

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Micromechanical Filters: Fundamentals andApplication to Interference MitigationRoy H. Olsson III; DARPAThe radio frequency (RF) spectrum is becoming increasinglycrowded, with more users accessing an increasing amount ofbandwidth. As a result, wireless handsets are experiencing arapid increase in the number of frequencies and standardssupported on a single platform. While the other components thatcomprise the RF frontend such as amplifiers, mixers andswitches are experiencing higher levels of cointegration, amodern cellular radio includes > 30 discrete filter dies toaccommodate the growing number of RF bands. A miniature andadaptive filter technology that supports many wireless standardson a single chip is needed to continue the increase in wirelessdata and functionality seen over the past decade.Piezoelectric microresonators are an enabling technology forincreasing adaptability, improving performance andminiaturization of RF devices. This talk will present an overviewof piezoelectric microresonator and filter research. First, the needfor adaptive and reconfigurable filtering in next generationwireless devices will be described. The performance andadaptability advantages derived from micromachining ofpiezoelectric resonators will be presented, followed by acomparison with competing technologies. Reconfigurable filterarrays realized in thin film piezoelectric materials will bepresented along with the application of these components inadaptive wireless systems. Finally, a look toward next generationpiezoelectric materials and devices such as thin film lithiumniobate resonators and tunable acoustic filters will be discussed.

WSA3 Interference Rejection exploiting SwitchedRCTechniques Compatible with CMOSEric Klumperink; University of TwenteWith the increasing number of wireless users, interferencerejection is becoming the main design challenge in CMOSReceiver frontends. Techniques to improve the Spurious FreeDynamic Range (SFDR) of radio receivers and cancel interferenceare hence important. As CMOS technology offers switches thatimprove with technology, while highly linear capacitors andresistors are also available, these are the components of choiceto realize high SFDR. This contribution will review some recentlyproposed ideas to improve the SFDR of CMOS radio receivers.Examples are mixerfirst receivers exploiting switchedR orswitchRC circuits, and Npath filters that simultaneously realizespatial domain and frequency domain filtering. Also, an inbandfullduplex receiver will be discussed.

WSA4 Broadband channelizer architectures withdynamic range relaxationRanjit Gharpurey; University of Texas at AustinArchitectures for implementation of broadband channelizers willbe described. These architectures split a broad bandwidth intocontiguous subbands with a single fixed frequency LO source.Frequencytranslation based techniques for interferencesuppression in such broadband radios will be described. The useof channelizers for rapid interference detection will be discussed.

WSA5 SelfInterference Cancellation and FilteringTechniques for Reconfigurable FrequencyDivisionDuplex/FullDuplex/CoExisting RadiosHarish Krishnaswamy; Columbia UniversityMultiband frequencydivision duplex radios require numerousoffchip duplexers, which limit the form factor in mobileapplications. Selfinterference cancellation can relax duplexerisolation requirements, enabling compact/tunable duplexers. Fullduplex radios have recently emerged as a promising paradigm todouble network capacity and spectrum utilization. Selfinterference cancellation to the tune of >100dB is mandatory insuch systems, and must be pursued in the antenna, RF/analogand digital domains.

WSA6 SelfInterference Cancellation in the RF DomainSachin Katti; Stanford University



Selfinterference arises when radios are tightly packed in adevice, its experienced inband, adjacentband and out of band.These are commonly known as inband full duplex, frequencydivision full duplex and radio coexistence in industry parlance.This talk reviews our recent work on selfinterferencecancellation, and discusses how it can be applied to handle selfinterference problems in multiband multiprotocol devices.

WSA7 Interference in NearField Communications(NFC) circuits for mobile handsetsMagnus Wiklund; Qualcomm CorporationIntegrating multiple standards in mobile handsets presentsnumerous difficulties with respect to interference. Typicalconnectivity systems feature WLAN, BT, FM, GPS, and NFC invarious combinations; in most applications connectivity mustcoexist with WAN. Despite challenges with coexistence ofmultiple radio standards a user expect their simultaneousoperation to be seamless. This paper focuses on the NFCtechnology with special emphasis to the transmitter andfundamental characteristics of the NFC system.

WSA8 Strategies for Transmitter SelfInterferenceManagement & MitigationChris Rudell; University of WashingtonManagement of selfinterference using numerous discrete duplexfilters has become a major barrier for current and future multiband highlyprogrammable full duplex radios. This presentationexplores some of the potential alternative integratedarchitectures to address selfinterface without the need for costlyand area consuming discrete filters. A key challenge for any selfinterference cancellation systems is the potential injection ofnoise in the receiver frontend, the matching of phase andamplitude between the RX input and the canceller. These topicswill be explored and some results from a recent integrated selfinterference cancellation will be presented.

WSB

Session: WSB Digital and Analog Techniques for PowerEfficiency Enhancement in Wireless Transmitters

Chair: Oren Eliezer, EverSet Technologies / TallannQuestCoChair: Ayman Fayed, Iowa State UniversityAbstract: Transmitter powerefficiency has always represented

a significant challenge in wireless devices, whetherthese are for batteryoperated mobile devices orinfrastructure applications.As the targeted bandwidths become wider and thespectral efficiencies higher, it is becoming even morechallenging to develop powerefficient transmittersthat meet all the requirements of the wireless systemsthey serve.This workshop, involving experts from industry andacademia, will cover various architectures andtechniques for powerefficient transmitters, includingboth analog and digital approaches.

WSB1 The Three Operating Modes of DynamicPowerSupply TransmitterEarl McCune; RF Communications ConsultingAny amplifier operated with a varying power supply is actually a3port circuit. When an amplifier is characterized as a 3port fordynamic power supply operation, three separate operatingmodes (2 nonlinear, 1 linear) appear: Lmode, Cmode, and Pmode. Each of these modes, along with their relationships anddifferences, are presented and discussed.

WSB2 Integrated and nonintegrated EnvelopeTracking Solutions



Jerry Lopez; NoiseFigure Research / Texas Tech UniversityThe recent necessity for wide bandwidth and lower powercommunications systems have increased the need for highlyefficient highlylinear power amplifiers (PA). Currentcommunication protocols can reach up to 12dB peaktoaverageratio (PAR), which directly affects the linearity and efficiency ofthe PA. Techniques such as envelopetracking (ET) and envelopemodulation (EM) are being utilized to increase efficiency andenhance linearity of the amplifier even when operated atcompressed modes. In this tutorial, we will analyze ET and EMsystems from a basic level to its recent forms including currenttesting techniques. An overview of envelope modulators,including integrated and nonintegrated versions, will be offered.Future highpower and subwatt ET/EM systems will also bediscussed.

WSB3 Design Challenges of Envelope Tracking andPolar Architectures as SupplyModulation BasedTechniques for Enhancing Transmitter EfficiencyJennifer Kitchen and Bertan Bakkaloglu; Arizona State UniversityThis tutorial will provide an overview of design challenges andadvances in supplymodulation techniques for improvingtransmitter efficiency. A comparison of existing adaptive biasingarchitectures and their implications to the RF transmitter'selectrical efficiency and linearity will be presented. Emphasis willbe placed on practical limitations for implementing envelopetracking and polar transmitters; highlighting the supplymodulator's design challenges. The bestinclass publishedperformance for the most recent works in supplymodulationbased architectures, including the envelopetracking Doherty and'digital' bias modulation, will also be discussed.

WSB4 Outphasing Techniques for Achieving HighEfficiency in TransmittersTaylor Barton; University of Texas at DallasOutphasing amplifiers control their output power using relativephase control of efficient branch PAs, offering the potential forlinear amplification with high efficiency over a wide range ofoutput power levels. The advantage of this approach is the highefficiency of the constituent branch PAs, which can be highlysaturated or operate in switchedmode. Conventional outphasingtechniques, however, have several limitations in achievableefficiency, primarily relating to the power combining network.This talk will present an overview of classic outphasingtechniques, including systems based on isolating and losslesspower combining. It will then focus on more recent techniques toimprove efficiency under backoff, including integratedimplementations.

WSB5 Power Supply Noise Mitigation techniques for RFPAsAyman Fayed; Iowa State UniversityRF Power Amplifiers (PAs) are typically the most powerdemanding components in wireless transmitters. Therefore,converting power from the battery to these PAs as efficiently aspossible is very critical. Although switching power converters areknown to be highly efficient, adopting them to power RF PAsfaces many hurdles, particularly due to the switching noiseassociated with them, which tends to significantly degrade thesystem performance. This tutorial will discuss various techniquesto mitigate the impact of this switching noise, including activeripple cancellation, deltasigma control, and different spreadspectrum control techniques.

WSB6 A Fully Integrated HighEfficiency DigitalTransmitter Based on PWM and ClassD PALei Ding and Rahmi Hezar; Texas Instruments This tutorial presents a fully digital transmitter architecture thatcan be used to replace the entire analog/RF signal chain in atraditional transmitter. The new architecture utilizes sigmadeltamodulation and pulsewidth modulation to convert highresolution baseband I and Q signals into 3level switchingsignals, thereby allowing efficient ClassD PA stages to be used.In addition, cascaded sigmadelta stages and switchedcapacitorcombining are incorporated into the architecture to significantly



reduce the outofband quantization noise while maintainingexcellent efficiency. The digital transmitter architecture isdemonstrated through a 45 nm CMOS test chip, which achievesexcellent efficiency and linearity.

WSB7 Linearizing Power Amplifiers with ClassGAnalog VoltageSupply ModulatorsJeffery Walling; University of Utah With increasing energy demands for wireless PAs, improvementsin energy efficiency are vital. CMOS optimization for lowswitching resistance leads to the use of CMOS switchedmodepower amplifiers. These amplifiers rely on external linearizationcircuits to amplify nonconstant envelope modulated signals. Inthis talk, we will compare several techniques for linearization,with particular emphasis on analog supply modulationtechniques. Practical design considerations for RF switchedmodePAs will be given, along with design considerations for analogsupply modulators. Several techniques will be compared and acasestudy of a classG analog supply modulator will beexamined in detail.

WSB8 Digital Approaches for Power EfficiencyEnhancement in TransmittersOren Eliezer and Sankalp Modi ; EverSet Technologies /TallannQuest, University of Texas at Dallas This tutorial proposes a unique digital approach to realizingpowerefficient transmission, which is based on a lookaheadwindow that provides a prediction of a segment of the envelopeof the signal. Examples for implementations of this digitallyintensive approach will be given, including several differentenvelope tracking systems and a Doherty based architecture fora highpower transmitter.

WSC

Session: WSC Highly Efficient RF Frequency Generation inNanometer CMOS Technologies

Chair: Salvatore Levantino, Politecnico di MilanoCoChair: Stefano Pellerano, Intel Corp.Abstract: The energy efficiency of RF frequency synthesizers is

of paramount importance in highperformance mobileradios that pose stringent phasenoise requirements,as well as in emerging wireless applications thatfeature extremely low power budgets (sensors,wearables, internet of things). Unfortunately,improving spectral purity in conventional phaselockedloops is obtained at the price of higher powerconsumption. This workshop will discuss the mostrelevant directions that have been investigated inrecent years to break this tradeoff by both circuitdesign and architectural innovations. The workshopwill begin by reviewing the fundamental limitations ofthe phasenoiseversuspower tradeoff in oscillatorsand the recent advances in the design of highlyefficient oscillators operating in unconventionalclasses. Then, it will move to discuss the mainarchitectural innovations relaxing the noisepowertradeoff in fractionalN PLLs: (i) adaptive phasenoisecancellation, (ii) nestedandcascaded architecture,(iii) subsampling phase detection, (iv) injectionlocked PLLs. As CMOS technologies scale down andaccurate DSP is enabled at low power and small area,the traditional analog PLLs are also moving towardsmostly digital designs, which are demonstrating betterefficiency and scalability, and even towards fullydigital designs, achieved via automatic synthesisandlayout flow. In the second half of the workshop, themost recent realizations of analog, hybrid and digital

1 2 1 2



frequency synthesizers will be critically compared fromthe efficiency and the scalability points of view.

WSC1 Fundamental limitations in LC oscillators noisepower efficiencyDanilo Manstretta; University of Pavia, ItalyModern communication systems need clocks with very low phasenoise (or jitter). Another increasingly key requirement is lowpower consumption, leading to the prominence of the phasenoise vs power tradeoff. To minimize power dissipation for agiven phase noise integrated oscillators often use as load highQLCresonators. Through the years several topologies have beenproposed. However, it is not always easy to ascertain whetherthe dominant reason of improvements comes from topology orimproved resonator Q. The goal of this talk is to ascertain theultimate performance limit for some of the most used oscillators,including most types of classB (standard, ACcoupled and withtail filter), classC and classF LC oscillators as well as distributedoscillators (travelingwave and standingwave and hybrid). In thepast, many authors have analyzed oscillators generally preferringrigor to intuitiveness. An intuitive yet sufficiently accurateformulation of phase noise is presented. To compare differenttopologies an excess noise factor that represents the differencebetween the maximum achievable Figure of Merit and the actualone is also introduced. In addition, the theory is experimentallyverified in a rigorous and objective way comparing differenttopologies in the exact same operating conditions, i.e.technology, Q of the tank, dividers, etc. Measurements on severalchip prototypes allow to verify, in an unbiased way a very goodagreement between the model and both simulations andmeasurements.

WSC2 Fully Integrated Phase Noise Extraction andCancellation Techniques for Ring OscillatorBased FractionalN PLLsBertan Bakkaloglu; Arizona State University, Tempe, AZ, USARingoscillators (ROs) provide a lowcost digital VCO solution infully integrated PLLs. However due to their supply noisesensitivity and high noise floor, their applications have beenlimited to low performance applications. The proposedarchitecture introduces an analog feedforward adaptive phasenoise cancellation architecture that extracts and suppressesphase noise of ringoscillators outside the PLL bandwidth. Theproposed technique can improve the phase noise at an arbitraryoffset frequency and bandwidth, and after initial calibration forgain it is insensitive to process, voltage and temperaturevariations. An experimental fractional PLL, with a loop bandwidthof 200 kHz is utilized to demonstrate the active phase noisecancellation approach. The cancellation loop is designed tosuppress the phase noise at 1 MHz offset by 12.5 dB andreference spur by 13 dB with less than 17% increase in theoverall power consumption at 5.1 GHz frequency. The measuredphase noise at 1 MHz offset after cancellation is 105 dBc/Hz. Theproposed ROPLL is fabricated in 90nm CMOS process. With noisecancellation loop enabled, the PLL consumes 24.7 mA at 1.2Vsupply.

WSC3 Lownoise highOSR sigmadelta fractionalNfrequency synthesizerSeongHwan Cho; Korean Advanced Institute of Science andTechnology, KAIST, Daejon, KoreaIn this talk, reference multiplication techniques to achieve lownoise lowpower fractionalN frequency synthesizer is presentedby means of nested and cascaded PLL architecture. In thenestedPLL, intermediate output of the feedback divider is usedas the deltasigma modulator (DSM) clock so that the DSMachieves high oversampling ratio (OSR) and thus lowquantization noise. Noise aliasing due to the divider is suppressedby having an antialias filter implemented using a PLL. In thecascadedPLL, reference multiplied fractionalN synthesis isachieved by employing two PLLs in cascade: an integerN PLLfollowed by a fractionalN PLL. In order to reduce the spur andphase noise of the integerN PLL, reference injection scheme withdualpulse ring oscillator is used, which eliminates the need forinjection timing adjustment. Prototype results of these PLLs in130nm CMOS demonstrate stateoftheart noise and powerconsumption without requiring any complex calibration



WSC4 Highperformance fractionalN frequencysynthesizers with large divided ratiosTaiCheng Lee; National Taiwan University, Taipei, TaiwanFor conventional chargepumpbased PLLs, charge pump circuitsand phase detectors are the dominant sources of inband noise,especially for the one with a large divided ratio. Furthermore, ΣΔmodulators in fractionalN PLLs induce significant quantizationnoise to deteriorate the phase noise of the output clocks.Samplingbased PLLs are proposed to achieve betterperformance. In this talk, prior arts on fractionalN PLL designare reviewed first. Then, the detail design and an analysis of asub sampling PLL are introduced to achieve a low inband phasenoise of 112 dBc/Hz at a 2.3GHz output frequency.

WSC5 Synthesizable Digital PLL Using InjectionLockArchitectureKenichi Okada; Tokyo Institute of Technology, Tokyo, JapanIn this presentation, a synthesizable PLL using the injectionlocktechnique is introduced. Synthesizable PLLs using common digitalsynthesis tools can be portable and scalable for processtechnology, which is advantageous in nanometerscale CMOStechnology. An injectionlock PLL is one of the good candidates ofsynthesizable PLL because the feedforward phaselockmechanism can relax the fine timing design of TDC/DTCbasedPLL.

WSC6 RingBased RF Digital Frequency SynthesizersAmr Elshazly; Intel Corporation, Hillsboro, OR, USARingbased digital frequency synthesizers have recently becomepopular as they offer certain advantages over their analog andLCbased counterparts. Ringbased DPLLs offer great areasavings, immunity to PVT variations, simplify several aspects ofthe design, and easier portability to newer processes. Thispresentation describes DPLL implementations identifying thedesign bottlenecks, and discusses recent design techniquesproposed to achieve high performance with low power for bothintegerN and FractionalN ringoscillator based RF digitalfrequency synthesizers.

WSC7 Area efficient analog PLLsJingHong Conan Zhan; Mediatek, Hsinchu, TaiwanIt is generally believed that ADPLL will benefit directly fromprocess scaling in terms of power and area. In this workshop,what limits conventional analog PLL from scaling will be revisited.Recent techniques and design examples toward an areaefficientanalog PLL will be reviewed. Analog PLL area shrink with respectto process scaling will be discussed.

WSC8 The best of both worlds: combining digital andanalog techniques in high performance PLLsMark Ferriss; IBM T. J. Watson Research Center, YorktownHeights, NY, USAThe recent interest in digital PLLs is primarily motivated by asearch for circuits which are architecturally better aligned withmodern digitaloriented CMOS manufacturing processes.However, some of the best features of analog PLLs, for example,highly linear phase detection, are difficult to replicate in fullydigital PLLs. In this work, we demonstrate how digital and analogPLLs can be combined in a hybrid PLL such that the best featuresof both architectures can by utilized, while avoiding the worstfeatures of both. In addition, we will demonstrate how advancedΔΣ noise cancellation can be implemented in the context of ahybrid PLL. This will be demonstrated in the context of a 13 to26GHz highly flexible hybrid PLL with an embedded ΔΣ noisecancellation scheme.

WSC9 UltraHigh Speed Direct Digital FrequencySynthesisFa Foster Dai; Auburn University, Alabama, USAThe recent success of ultrahighspeed direct digital synthesizer(DDS) provides an excellent solution to wideband complexwaveform generation and digital modulation for applications suchas digital radar, telemetry, RF sensor, instrument and wireless



communication. This talk presents advanced highspeed DDSdesigns, focusing on techniques that can achieve high clockfrequency, low power, high dynamic range and improved spectralperformance. Techniques such as spur cancellation, predistortion, ΣΔ modulation, digital calibration and timeinterleaving are addressed. A number of design examples arepresented to illustrate the stateoftheart developments in thisfield. A SiGe DDS MMIC with 11bit phase and 10bit amplituderesolutions achieves clock frequency of 8.6 GHz and spuriousfreedynamicrange (SFDR) of 45 dBc at 4.3 GHz Nyquist output.

WSD

Session: WSD MulitGbps Wireline Transceivers: Inching Closerto RF/MMwave IC Domain

Chair: Hiva Hedaytai, XilinxCoChair: Mona Hella, Rensselaer Polytechnic InstituteCoChair: Burak Catli, BroadcomAbstract: High Performance Computing (HPC) installations and

exaFLOP supercomputing require high bandwidth chiptochip and systemtosystem communication links.One critical block in such systems is theSerializer/Deserializer (SerDes) which formats andtransfers data over either electrical or optical links.Moving data transfer rates beyond 32Gb/s and 64Gb/sclearly places some of the SerDes design challengesinto the RF/Microwave domain. The high data ratecoupled to the limits on the transfer medium, requirerelatively complex modulation techniques. The costand power consumption have also become morepronounceable, particularly with super data centersemploying several thousand of such transceivers. Thisworkshop presents an overview of recent advancesand ongoing research in MultiGbp/s serial links as itrelates to the world of RF/Microwaves. The workshopwill cover wideband microwave clock generationschemes, clock and data recovery circuits along withvarious equalization techniques. In addition 30+GS/sADC architectures for 60+Gb/s wireline receiverapplications will be discussed. We will also explorelowpower circuit implementations for 25G+ I/Os,where we discuss both analog and digitalimplementations.

WSD1 Design Techniques for Scalable, SubpJ/b SerialI/O TransceiversProf. Samuel Palermo; Texas A&M UniversityIn order to meet the interchip bandwidth demands of futuresystems and comply with limited IC power budgets, both chiptochip data rates and I/O energy efficiency must improve. This is asignificant challenge for electrical interconnect architectures,which currently offer the lowestcost solutions, as the frequencydependent loss of conventional electrical channels prohibitsignificant data rate scaling without efficient equalizer circuits.This tutorial will discuss key design techniques that enablescalable, subpJ/b serial I/O transceivers. The first part of thetutorial will discuss low power transmitter and receiver designscapable of lowvoltage operation and fast powerstatetransitioning. Next, lowcomplexity clocking architectures aredetails. The tutorial concludes with a discussion on lowpowerequalizer circuits that enable the support of higher data ratesover lossy channels.

WSD2 Design techniques for 25G+ analog & digital I/OimplementationsDr. Thomas Toifl; IBM, Zurich, SwitzerlandIn this talk we will explore lowpower circuit implementations for25G+ I/Os, where we discuss both analog and digitalimplementations. We start by giving a short introduction to



important wireline I/O standards, and describe the associatedequalization requirements. We then turn to the equalizationoptions in the data path using a feed forward equalizer (FFE) anda continuoustime linear equalizer (CTLE), followed by adiscussion of design options for decision feedback equalizers(DFE). In the second part of the talk we will turn to digital I/Oimplementations: Here, we will first discuss the design andrecent results of highspeed lowpower SAR ADCs. We thendescribe methods to reduce the latency in the CDR logic, which isrequired to compensate the latency of the ADC withoutpenalizing jitter tolerance. We will then discuss lowpowersolutions for digital equalizer implementations.

WSD3 Review of ADCBased CDRs and the Challengesfor Higher Data RatesProf. Ali Sheikholeslami; University of TorontoADCBased Clock and Data Recovery circuits are one of primarycandidates for the 60+Gb/s wireline receivers, as they canprovide significant channel equalization in digital domain. This isespecially important at higher data rates as the channelattenuation become more significant at the Nyquist rate and asthe attenuation profile shows a higher complexity that cannot beeasily compensated for by analog equalization. The mainchallenge in designing ADCbased CDRs is their high powerconsumption, especially the power consumed by the ADC's at thefront end. This talk will review the ADCbased CDRs and thetechniques proposed to address their challenges.

WSD4 Transceivers for 40Gbps and 100Gbps WirelineConnectionsDr. Jun Cao; BroadcomThe demand for wireline transceivers running at rates 25Gbpsand higher has been fueled by the exponential growth in 40Gband 100Gb Ethernet in recent years. This talk will first presentthe design of a transmitter/receiver chipset running at 44Gb/s in40nm CMOS with stateofart jitter and power performance.Various techniques are employed to overcome the speedlimitation of the technology, including bridgedshunt and Tcoilshuntseries peaking and a new pipelined CDR/DMX structure.The design of a low power 4x28Gb/s transceiver for 100GbE isthen discussed, particularly the reconfigurable, distributed andtuned clock structure, which saves 70% of power compared toconventional designs. At present, 100G coherent systems arebeing deployed rapidly but they also pose special challenges inthe circuit design. The talk will conclude with the discussion on aquadchannel 128Gb/s coherent DPQPSK transmitter whichachieves an RJ of 103fsrms and IQ data skew much less than1ps across the variation in temperature and supplies.

WSD5 A 40nm High Performance Analog MultiToneTransceiver for Multidrop ProcessorMemoryInterfacesProf. Yusuf Leblebici; École polytechnique fédérale de Lausanne,SwitzerlandA 7.5 Gb/s mixed NRZ/multitone transceiver for multidrop bus(MDB) memory interfaces is designed and fabricated in 40nmCMOS technology. Reducing the complexity of the equalizationcircuitry on the RX side, the proposed architecture achieves 1pJ/bit link efficiency for a MDB channel with 45 dB loss at 2.5GHz. The transmitted spectrum composed of BB and I/Q subbands with the capability to match the modulation frequency ofthe entire TRX with respect to the channel response over+/25% range. A switchcap mixer/filter is developed to downconvert and equalize the I/Q subbands in RX very efficiently.

WSE

Session: WSE MixedSignal Power Amplifiers and RFDACsChair: Hua Wang; Georgia Institute of TechnologyCoChair: Robert Staszewski; University College DublinCoChair: Renaldi Winoto; MarvellAbstract:



The growing demand for a higher datarate and longerbattery life poses stringent requirements on the poweramplifiers (PAs) in mobile handset transceivers.Siliconbased PAs, e.g., in CMOS or SiGe HBTprocesses, have recently emerged as competitivesolutions for many applications. Besides lowcost andhigh integration, siliconplatforms offer unparalleledsignal processing/computation capabilities, which canbe exploited for PA performance enhancement withlow overhead. RFDAC is one perfect example of thisnew PA paradigmshift. It merges digitaloperation/processing and analog/mixedsignaltechniques with PA architectures to achieveefficiency/linearity enhancement, performance selfhealing, and antenna load compensation, etc. As aresult, advanced silicon PA has expanded from astandalone RF building block to a complex mixedsignal/mixedmode system with orchestratedcollaboration among analog, digital, and largesignalRF operations. This workshop is to review this recentwave of innovations on "MixedSignal PAs and RFDACs" and bring the stateoftheart technologies tothe attendees.

WSE1 SwitchedMode PA for Broadband and RFDACsProf. Robert Staszewski, University College DublinThis talk will provide an overview of switchedmode poweramplifiers and RF DACs in CMOS wireless transmitters. At thecore of this trend is CMOS technology scaling. As the switchingspeed of CMOS transistors has been increasing, advantages ofswitchedmode classE, classD and classF operations have beenmore obvious not only from the power efficiency standpoint, butalso from performance and transfer function repeatability.Furthermore, technology scaling has allowed full integration ofmatching networks between the last stage of PA and an antennafeed, which further allowed to reduce the total solution cost. Thefinal benefit of the technology scaling is the partition of the PA“switch” into a large number of controllable switches for thepurpose of amplitude modulation.

WSE2 Leveraging RFDACs to Enhance the Doherty PAArchitectureProf. Hua Wang, Georgia Insititue of TechnologyThe everincreasing demand of a high data rate has led to a wideuse of spectrumefficient modulations in modern wirelesssystems. These schemes often present high peaktoaveragepower ratios (PAPR), which require the power amplifier (PA) towork at the power backoff (PBO) mode. Moreover, sophisticatedconstellations are often employed, posing additional linearityrequirements on the PA for high fidelity signal transmission. Bothaspects may lead to substantially degraded PA efficiency inpractice.We present a CMOS compatible digital Doherty polar poweramplifier architecture to address the PA tradeoff challengesamong power backoff, linearity, and efficiency. Leveraging thedigitalintensive architecture, the gain relationship of the Dohertymain/auxiliary amplifier paths can be precisely controlled, whichachieves optimized Doherty "active loadpulling" operation forenhanced PA backoff efficiency. Moreover, the architectureprovides the Doherty power amplifier with highlyreconfigurability, linearity improvement, and robust Dohertyperformance against antenna load mismatch. In addition, we willexplore the feasibility of combining this digital Doherty PAscheme with other PA techniques to achieve new RF PAarchitectures with hybridmode efficiency/linearity enhancement.

WSE3 SwitchedCapacitor and ClassG PAProf. Jell Walling, University of UtahWith increasing energy demands for wireless PAs, improvementsin energy efficiency are vital. Leveraging CMOS prowess as aswitch is critical and leads to the development of mixedsignal RFPAs. A switched mode PA modulated by an analog classG supplymodulator will be introduced. Following this, the switchedcapacitor PA concept will be introduced along with a classG



digitally supply modulated PA. Design considerations for both ofthese mixedsignal PAs will be discussed in detail, andcomparisons and contrasts for the designs will be offered.Specifically tradeoffs in linearity, efficiency and noise will beanalyzed and discussed. Detailed design examples will be offeredfor all of the presented mixedsignal PAs.

WSE4 Polar Antenna Impedance Detection in a CMOSPower Amplifier and Impedance Tuning with AnSOI Switch based Impedance TunerDr. Shouhei Koussai, Tobisha CorporationThe recent demand for wideband and smallsized antennaunfortunately leads to potentially larger antenna load mismatchesin practice. However, this is a critical issue for achieving a highlyefficient power amplifier in real use. In this talk, an antennaimpedance detection and tuning scheme, which takes advantageof the unparalleled CMOS signal processing capability, ispresented as a promising solution that could be directlyembedded with CMOS power amplifier (PA) designs. Unlike manyother reported antenna tuning techniques, we propose a polarimpedance scheme, which can detect and correct both real andimaginary antenna impedance mismatches. Our detection circuitis integrated on a CMOS PA chip, and the antenna impedance canbe tuned to accurately track non50Ohm optimum loadimpedance for the PA with wide frequency range and backoffoutput power. In addition, the tuning system can handlemodulated signals and can track the timevarying antenna loaddue to the proximity effect.

WSE5 SelfHealing for MmWave Power AmplifiersProf. Steven Bowers, University of VirginaAdvances in CMOS technology create opportunities andchallenges for power amplifiers (PAs) at mmwave frequencies.Process variation, modeling inaccuracies, load impedancemismatch as well as partial and total transistor failure cansignificantly degrade the performance of the PA at thesefrequencies, especially early in a process node¹s lifecycle. Theseuncertainties and variation can require either a less aggressivemmwave design, multiple design spins, a reduction in yield orsome combination of all three. Selfhealing uses the vast digitalcomputational power of CMOS through an integrated mixedsignal feedback loop to sense performance degradation of themmwave circuit, and correct for it by actuating the circuit. Thispresentation will explore various techniques and costs associatedwith producing a robust and effective selfhealing mmwave PAand will go through an example of such a system.

WSE6 Holistic Design Approach for MmWaveDigitallyAssisted Power Amplifiers (DAPA)on CMOS and GaN Dr. Tim LaRocca, Northrop Grumman A topdown design review of the system, circuit andmeasurements of digitallyassisted power amplifiers (DAPA) onboth CMOS and GaN will be provided. This is based on threepublished designs including a 45GHz and 94GHz 4b DAPA on IBM10LPe (65nm bulk) and 12SOI (45nm SOI), and 618GHz GaNDAPA for 64QAM modulation. This presentation will start with areview of highlevel modeling and simulation of the DAPA usingVerliogA and CMOS device models to predict efficiencyimprovements and define system requirements. This will befollowed by a brief review of the digital algorithm andimplementation including tradeoffs between ASIC and FPGAsolutions. Finally, a practical review of the design of the DAPAwith explanation of measurements and future work will concludethe talk.

WSE7 Next Generation Base station Transmitters/ RFDACSProf. Leo de Vreede, Delft University of TechnologyNext generation base station transmitters need to be efficient andwideband in nature in order to support multiple communicationstandards / bands in an energy and cost effective manner. Thetrend to smaller cell sizes, lower transmit powers and increasedbandwidths puts new constrains on the TXsystem concept,systemintegration and the power consumption of the total TX



lineup. With this trend in mind, new PA techniques and RFDACapproaches will be considered that can provide higher systemintegration, bandwidth and overall line upefficiency.

WSE8 Digital Transmitters and RFDACs for CMOSTransceiver SoCs with SelfCompensation/PredistortionDr. Oren Eliezer, EverSet Technologies/TallannQuestThis tutorial will present several extensivelydigital topologies forwideband transmitters/RFDACs, some of which wereimplemented at Texas Instruments in nanometer CMOStransceiver SoCs. Productization aspects, such as builtin testingand “selfhealing” (builtin calibration and predistortion), will behighlighted.

WSF

Session: WSF Next Generation 7781 GHz Automotive RadarsChair: Gabriel M. Rebeiz, UCSDCo:Chair: Juergen Hasch, Robert Bosch GmbHAbstract: Automotive radars at 77 GHz are being shipped at

more than 1 million units per year for longrangeradars (LRR) and medium range radars (MRR) withapplications in automatic cruise control (ACC), collisionavoidance, and in imaging/tracking radars forautonomous driving. Radar topologies include lensbased systems, digital beamforming and RFbeamforming systems. Millimeterwave radars areessential for autonomous driving, and new systemswith wider bandwidths, better tracking and imagingsoftware, and better scanning techniques are beingdeveloped to meet this need. This workshopassembles a mix of industry and universities topresent the latest techniques in automotive radars,both from the systems/application perspective andfrom the mmwave electronics and hardwareperspective (antennas, packaging, etc.). The workshopwill have a mix of users (Daimler Benz, Toyota),chip/electronic developers (Freescale, Infineon), andUniversities, and promises to be comprehensive with awide but indepth view of this area.

WSF1 Trends in Roadway Domain Active Sensing Stephen H. Bayless; ITS AmericaThe talk analyzes the merits and limits of active sensingtechnologies (Radar, LIDAR and Ultrasonic detectors) and howthe demands for such technologies is evolving. Of all the roadwaydomain active sensing technologies, vehicular radar is the best atdetecting typical driving conflicts representing the most commoncrash risks and thus likely will serve as a key component ofcollision avoidance systems in many next generation smartvehicles. The report examines how future VehicletoVehiclecommunications and Active Traffic Management techniques willimprove and complement active sensing in vehicle crashavoidance and driving automation.

WSF2 Present Research Activities and FutureRequirements on Radar from a carmanufacturer's point of viewJuergen Dickmann; Daimler Benz, Ulm, GermanyAUTOMOTIVE RADARS have been the backbone for active safetyand advanced driver assistance systems (ADAS) for decades.With the introduction of the collision prevention assist, Radarsensors have become standard equipment in MercedesBenzpassenger cars. The range of applications they enable coversdetection tasks like blind spot assist up to automated brakingsystems like the PreSafe Brake assist available in the SClass.For heavy trucks and vans they enable cruise control and braking



support. In recent years, radar has more and more alsoconsidered as enabler for agency driven safety applications likethe EURONCAP, which grant star ratings. In former days, singlesensor concepts have been applied to realize ADAS, nowadaysmultisensor networks with short,mid, and far range radars arebeing applied. Today, in state of the art cars four to six radarsare being used. In 2013, the first stride ahead towards higherautomated systems in real serial cars has been made with theBertha drive with the MercedesBenz SClass Intelligent drive.The higher degree in automation of ADAS, where the driver isgoing to be exculpated increasingly from the pure driving task,imposes much higher performance to the environmentalperception task and hence to the automotive radar. The paperwill provide an overview on present automotive radars at DaimlerAG, will give an outline on future requirements for highlyautomated driving and will present some related researchexamples on radar based environmental perception.

WSF3 HighResolution PhasedArray AutomotiveRadarsDr. Jae S. Lee; Paul Schamlenburg; Kyosuke Miyagi; ToyotaTechnical Center, Ann Arbor, MichiganAutomotive radar is a critical sensing unit for vehicle safety,automated driving assistance etc. along with lidar and camera.This talk will introduce superior properties of phased array beamscanning method, prototype system development with SiGe RFICand its performance verification.

WSF4 Automotive Radar Technology TrendsJuergen Hasch; Robert Bosch GmbH, Stuttgart, GermanyIn the last few years automotive radar has been transformedfrom being a niche sensor to becoming standard even in middleclass cars. With EuroNCAP ratings now requiring automatedbraking and pedestrian safety functionality, radar is oftenidentified as the best suited sensor for this purpose.Additionally, future automated driving will require detailed andhighly reliable information on the environment and surroundingstreet traffic. This requires radar sensors to provide more detailedinformation about the environment, foremost in the spatialdomain. Automotive radar has always benefited significantly fromtechnological advances, especially in semiconductor technology.and packaging, allowing a better performance and much morefunctionality in the radar frontend. A second key area is theantenna system, where new concepts to acquire moreinformation about signals reflected from the environment cansignificantly improve resolution and detection performance.

WSF5 Digitally Centric Modulation Schemes on aSoftware Defined Radar (SDR) PlatformAndreas Stelzer; Johannes Kepler University, LinzHighly integrated radar sensors are a tradeoff of availablesemiconductor technology, analog bandwidth used, as well asbaseband functionality and signal processing capabilities. Basedon a software defined radar demonstrator digitally enhancedFMCW systems in combination with various modulation schemesfor TDMA, CDMA, FDMAMIMO applications and multibeam TXphased arrays, are discussed. Alternatives, e.g. OFDM modulationor PRNbased radar sensors with different coding schemes areshown, and a novel PRNMIMO radar sensor is introduced.With CMOS technology nodes on one hand reaching the highradar frequencies, on the other hand fully digitalonly modulationschemes and signal processing approaches are feasible. In theworkshop some approaches towards digital centric approaches interms of RFhardware, modulation schemes, and evaluationprocedures are tackled, which means a paradigm shift in the RFdesign flow from the analog towards the digital domain.

WSF6 Packaging Technology and Production Testing:Key Differentiators for Automotive Radar FrontEnd ProductsDr. Sergio Palma Pacheco; Freescale Semiconductor,Tempe, AZEver since the advent of the seat belt, safety has become a keydifferentiator in the automotive industry. This trend continuedwith airbags, antilock braking systems, and now with stabilitycontrol. Although these systems have been pervasive for the



past 20 years, the number of accidents and fatalities in the UShas remained steady. The next step on the road towards greatersafety is the use of active sensing for collision avoidance. Thistalk will cover the development of mmwave packagingtechnology and automated production testing capability as keydifferentiators in the industry. The main key features,challenges, and future trends for each will be presented; and howthese enablers impact automotive radar applications from anoverall system and business perspective.

WSF7 How Can Semiconductor Technology and MMICPackaging Contribute to Future Success ofAutomotive Radar?Dr. Rudolph Lachner; Infineon AGToday’s market success of automotive radar systems is to a greatextend driven by technology. The development is characterizedby the transition from old school GaAs based, more or less ondiscrete millimeter wave design approaches and semiautomatedassembly to highly integrated Sibased SoC solutions andautomated PCB assembly with standard SMD components. TheSoC solutions have significant costdown potential and offer highlevels of manufacturing maturity, yield, automotive quality overthe full temperature range and highvolume productioncapabilities, enabling broad market penetration of radar even inthe low priced car segments. In this talk, I will present state ofSiGe radar technology and its related packaging. Examples ofproducts will be given and directions and challenges of futureprocess developments will be outlined.

WSF8 Antennas Concepts for Automotive RadarSensorsProf. Wolfgang Menzel; University of Ulm, GermanyThe choice automotive radar antennas is determined by therequirement for high gain and low loss combined with small sizeand depth, the challenges by the millimeterwave frequencyrange, and great cost pressures. Consequently, planar antennasare dominating in the lower frequency range, while lens andreflector antennas had been the original choice at 76.5 GHz,partly in folded configurations, but today planar antennas arebeing introduced for the mmwave range as well. With increasingrequirements towards a much more detailed observation of thescenery in front or around the vehicle, multibeam antennas orscanning antennas have been designed, and solutions based on(digital) beamforming with a number of integrated antennas arein use or under development. This contribution will give a generalintroduction into antenna solutions forn automotive radar andpresent a number of realized solutions.

WSF9 Millimeterwave beamforming chips with builtinselftest for lowcost radarsGabriel M. Rebeiz; University of California, San DiegoPhasedarray chips with 8 to 16 channels and with transmit andreceive capabilities have been developed for lowcost mmwaveautomotive radars. One of the cost drivers in these chips is the Sparameter testing at Wband frequencies, and therefore, a newbuiltinselftest solution has been implemented which canaccurately measure the amplitude and phase of each channel,and measure an entirechip phasedarray pattern. The design andpackaging of these chips will be presented together withmeasured patterns with +/50 scan angle and actual radarexamples.

WSG

Session: WSG Performance Metrics for mmWave Devices andCircuits from the Perspective of theInternational Technology Roadmap forSemiconductors (ITRS)

Chair: Dr. Herbert S. Bennett, NISTCoChair: Dr. Pete Zampardim RFMDAbstract:

o



This workshop will focus on demystifying the ITRS RFand Analog/MixedSignal Technologies WorkingGroup's mmwave device technology and circuitroadmapping activities. Device, circuit, andtechnology performance simulation, scaling, andexperimental characterization metrics and techniqueswill be addressed in detail for the most advancedCMOS, SiGe BiCMOS, IIIV HBT and IIIV HEMTtechnologies. Intrinsic device structure as well aslayout parasitics will be addressed as potential showstoppers to future scaling. The everincreasing gapbetween the intrinsic high frequency performancemetrics of CMOS transistors and that of fully wiredMOSFETs, not seen in other device types, will beexplained.The workshop will end with an open discussion amongthe presenters and audience on how differenttechnologies compare to each other. Whatapplications will drive the mmwave section of theITRS in the next 15 years? Will the Internet of Thingspose new technology performance requirements or isexisting technology more than adequate? Are FinFETsfaster than Ultrathin Body and BOX SOI MOSFETs atthe same gate length and technology node? What isthe real gate length of 22nm and 14nm CMOStechnology and why gate length matters? Are theITRS metric tables accurately reflecting how thetechnology is going to perform in mmwave circuits?Will all existing transistor technologies live and dietogether in the next ten years? Is there transistor lifebeyond 23nm physical dimensions? Which devicetype will scale to the highest fT and fMAX? Will mmwave and THz SoCs be desirable and, if yes, feasibleat all or will these corresponding

WSG1 Roadmaps and Standards for RF andAnalog/MixedSignalTechnologies: International Roadmap forSemiconductors PerspectivesHerbert S. Bennett; NIST, Gaithersburg, MD, USARoadmaps and standards with their associated measurementsare key to successful innovation and commercialization and jobcreation. Mobile devices such as today's smart phones andtablets are rapidly growing segments of the electronics industryand are creating more opportunities for increased growth. As aresponse to earlier market demands for RF dependent mobiledevices the ITRS established in 2001 its Working Group on RFand Analog/MixedSignal (RF and AMS) Technologies. Thispresentation includes: 1) a brief discussion on the history oftechnology roadmaps and a discussion on the roles thatinternational technology roadmaps and standards play inaccelerating the rates of innovation and commercialization ofselected technologies, 2) the ITRS process for establishing anindustrial consensus on priorities, technical requirements, anddifficult challenges, and 3) Why you should be interested in RFtechnology roadmaps and standards. The latter are invisiblecatalysts for efficient economies. Essential ingredients for qualitytechnology roadmaps and standards include sound science andengineering principles, reproducible measurements, manageablenumber of key processing characteristics and performancemetrics, and agreement among all stakeholders. Grandchallenges are sustaining effective communications, cooperation,and collaboration among stakeholders and understandinginterfaces well enough to control and reproduce performancefigures of merit in high volume manufacturing.

WSG2 Scaling, modelling, and exploration of physicallimitations of SiGe HBTsProf. Michael Schroter; Technical University Dresgen, Germanyand UCSD, La Jolla, Ca, USAThe latest ITRS predictions for SiGe HBT technology have beenbased on combining the results of various one, two and three



dimensional TCAD simulation tools with geometry scalablecompact modeling. This enables an accurate and consistentdetermination of all figures of merit for both devices and(benchmark) circuits. This presentation will discuss the overallprocedure and the assumptions made for generating thetransistor performance results found in the present ITRS tables.An extensive and consistent set of technology and electricalparameters is provided along with the obtained scaling rules.Finally, the expected fabrication related challenges and possiblesolutions for achieving the predicted performance data will bediscussed.

WSG3 IIIV HBT and (MOS) HEMT scalingProf. Mark Rodwell, University of California, CA, USAInP HBTs and HEMTs are today the widestbandwidth transistors.InP HEMTs provide the lowest noise and the highest (~1.4THz)cutoff frequencies; InP HBTs have ~1.1THz cutoff frequencies,support moderate (~1000 HBT) integration scales, and offersuperior RF output power densities (~0.4W/mm at 220GHz,2.1W/mm at 86GHz). IIIV LNAs and PAs are ubiquitous intoday's cellular telephones and WiFi transceivers; similarly InPHEMT LNAs and HBT PAs will provide the needed noise figure,output power, and PAE in emerging ~50500 GHz wirelesscommunications systems. We will present scaling laws androadmaps of these devices, and examine their scaling potentialto ~23 THz cutoff frequencies.

WSG4 Nanoscale CMOS – an RF/mmwave PerspectiveDr. Kenneth Yau; Broadcom, Irvine, CA, USAMoore's law has been dictating the scaling of the MOS transistorfor several decades. Stateoftheart CMOS technologiescurrently in production feature minimum gate lengths in tens ofnanometers and integration scales that can only be dreamt of nottoo long ago. With this aggressive scaling, the CMOS transistorhas attained current and power gain cutoff frequencies in excessof 300 GHz. RF and millimeterwave LNA's, PA's and even entiretransceivers, which were traditionally the domain of IIIVtechnologies, have been successfully implemented in CMOS. Thispresentation will focus on the performance metrics of the nanoscale MOS transistor for RF and millimeterwave applications.Extensive RF figuresofmerit such as Ft and Fmax and theirscaling from one technology node to another will be presented.Finally, technology related challenges will be surveyed andpossible solutions will be discussed.

WSG5 Stateoftheart MillimeterWave IIIV HEMTTechnologiesDr. Keisuke Shinohara; HRL Laboratories, Malibu, CA, USAMillimeterwave InP and GaNbased HEMT device and MMICtechnologies will be reviewed. InPHEMTs offer the lowest noisefigure and the highest maximum oscillation frequency exceeding1THz, demonstrating submillimeterwave amplifier MMICs andlownoise amplifiers with a low DC power consumption. Recentprogress of GaNHEMT scaling technologies boosted its cutofffrequencies up to 500 GHz range while maintaining Johnson'sfigureofmerit high breakdown performance. The emerging GaNtechnology enables highefficiency millimeterwave poweramplifiers, robust lownoise amplifiers with high input powersurvivability, and lowloss RF switches with high power handlingcapability.

WSG6 55nm SiGe BiCMOS technology and beyond. Howaggressively can the CMOS be scaled?Dr. Pascal Chevalier; STMicroelectronics, Crolles, France55nm SiGe BiCMOS technology developed in STMicroelectronics300 mm wafer line will be presented. The technology featuresLow Power and General Purpose CMOS devices (triple gate oxide)and 0.45 µm² 6TSRAM bit cell. 3 flavors of SiGe HBT with fTranging from 65 GHz to 320 GHz and fMAX from 270 GHz to 380GHz associated to BVCEO values between 1.5 V and 3.2 V areoffered. A 9 metal layers backend of line combining theadvantages of being fully compatible with the existing 55 nmCMOS libraries and to provide enhanced performance formillimeterwave passives (inductors, capacitors and transmissionlines) is available. Specific varactors dedicated to millimeterwave applications are also proposed. Perspectives to use more



advanced CMOS nodes (40nm and beyond) for next BiCMOSnodes will also be discussed.

WSG7 mmWave RFCMOS TechnologyDr. David Harame; Global Foundries, USAAdvanced node RFCMOS is well suited for mmWave applicationsbecause of the high fT of the transistors and the features in thetechnology. An RFCMOS technology is typically compatible withthe base CMOS process so that libraries and IP may be leveragedin designs. Added features include passives such as varactors,capacitors including metaloxidemetal fringe capacitors,inductors, and transmission lines using layers and processesfound in the base CMOS technology.Performance scaling of advanced node CMOS now requires theincorporation of local strain layers (usually nitride) and High KMetal Gate stack.The International Technology Roadmap for Semiconductorspredicts the trends in CMOS and other technologies. There is anRF subcommittee which has made predictions about the RFcharacteristics. This report summarizes some of thoseprojections. The methodology is to develop analytical expressionsfor RF figures of merit and predict RF performance trends basedon the base process characteristics. Comparing the ITRS and thefoundry data there are discrepancies. This is not surprising giventhe introduction of disruptive process innovations such as strain,layout variation, and computational lithographic design rules.This workshop talks about the trends and why there differencesbetween extending analytical expressions and actual foundrydata. The workshop concludes with a brief section on passives.

WSG8 Beyond the Transistor. FET, HBT and FETHBTmmWave Circuit Benchmarking and ScalingProf. Sorin P. Voinigescu; University of Toronto, CanadaThe presentation will first discuss the measurement, deembedding and extrapolation techniques used to generate the HFfigures of merit in the ITRS tables. Exampels of nanoscale CMOS,FDSOI and SiGe HBT transistors and cascode stages measuredup to 325 GHz will be provided. Next, the choice of mmwaveand highspeed benchmark circuits will be addressed along withtheir predicted performance scaling based on large signalcompact models.

WSH

Session: WSH Nanopackaging: Multifunctional nanomaterialsand devices towards 3D system miniaturization

Chair: Dominique Baillargeat, XLIM UMR 7252CNRS/Université de Limoges

CoChair: Fabio Coccetti, CNRSLAASAbstract: Future nanoelectronics technology will face many

challenges to match Moore and more than MoorePredictions. Going to nanometric dimensions needs toovercome limits due to physical phenomena,technological capabilities, packaging and assembly ofcircuits and system. (Nano)packaging is becoming amajor bottleneck and it will play a crucial role forenabling future nanoelectronics to be consistent withfuture components, system and circuit board (orglobal level) requirements. In this context, manychallenges have to be considered: development ofstateoftheart thermal and interconnect interfaces.development of new thermal and electrical nanocharacterization techniques. development of predictivemodeling tools based on multidisciplinary andadvanced multiscales approaches, fabricating andtesting of representative demonstrators withsignificant impactThis WS will considered all this aspects. It isinherently interdisciplinary, and contributors arecomprised of experts in complementary research



fields and will present intensive researchinvestigations focused on carbon nanotubes,graphen, 2D materials, nanowires, etc. dedicated to3D system integration and miniaturization.

WSH1 Carbon based 3D interconnect technologyJohan Liu ; Yifeng Fu ; Di Jiang ; Shuangxi Sun ; Jie Bao andNing Wang ; Department of Microtechnology and Nanoscience,Chalmers University of Technology, Sweden, SMIT Center,School of Automation and Mechacnical Engineering and KeyLaboratory of New Displays and System Integration, ShanghaiUniversity, 3SHT Smart High Tech AB, Gothenburg, SwedenCarbon Nanotubes (CNTs) have excellent electrical, thermal andmechanical properties. They are mechanically strong atnanoscale yet also flexible if made micro or millimeter long.They are synthesized from nanosized catalyst particles and canbe made up to millimeters. A lot of research studies have beenspent on various properties of the CNTs. They are regarded as analternative material in a lot of applications such as ICs, MEMS,sensors, biomedical and other composite materials, etc. Amongthem, the thermally grown CNTs using chemical vapor depositionmethod is of particular interested in electronics applications as a3D interconnect material. Within this talk, growth and postgrowth processing of CNTs are covered and tailoring of CNTsproperties, i.e. electrical resistivity, thermal conductivity andstrength, etc., is discussed. To make the electronics systemssmaller, faster and more power efficient, CNTs as a potential newmaterial are likely to provide the solution for these futurechallenges.

WSH2 MicroNano interposer for Molecular electronicsand 3D integrated circuitsP. Reynaud; A. Thuaire; X. Baillin; S. Cheramy; G. Poupon; CEALéti, Grenoble – FranceAs molecular electronics is getting more and more explored, itbecomes necessary to find appropriate nanopackaging solutions.A micronano interposer based on silicon nanotechnology is thusdeveloped to allow connection between a molecular circuit andmesoscopic electrodes. This interposer includes nanotomicroscale interconnections and high density "trough silicon via" (TSV)for 3D integrated circuits.

WSH3 High Frequency Models for Multilayer GrapheneInterconnectsV. Kumar ; Shaloo Rakheja ; and Azad Naeemi ; GeorgiaInstitute of Technology, MITIn this talk, a unified approach in capturing quantum mechanicaland electromagnetic phenomena will be used to model signaltransport in multilayer graphene interconnects. The models willbe used to quantify the potential performance of grapheneinterconnects as possible replacements for copper interconnectsin digital and RF applications.

WSH4 RF Nano Electromechanical Systems (RF NEMS)Based on Vertically Aligned Carbon NanotubesA.Ziaei, S. Xavier; Thales R&T, FranceWe demonstrate a reproducible carbon nanotubes basedtechnology for switching applications (RF NEMS). The finalobjective is to demonstrate a CNT based switching deviceworking in the range 180GHz and fulfilling very demandingrequirements: low losses, high isolation, a switching time below0.1μs, an operation voltage below 30V and high power handlingcapabilities.

WSH5 Carbon nanostructures based RF nanopackaging.Application to 3D interconnectD. Baillargeat1; S. Bila ; P. Coquet ; B.K. Tay ; XLIM UMR7252 CNRS/University of Limoges, CINTRA UMI 3288CNRS/NTU/Thales, Singapore, SEEE NTU, SingaporeAssembly approaches are moving toward the systemlevelintegration paradigm and new packaging technologies areproposed such as 3D system integration, waferlevel packaging,or electro/optical integration. During the last past years, newapproaches have been studied. They consist in the use of new

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nanomaterials in packaging such as carbon nanotubes (CNTs),nanowires, nanoparticules and graphene.In this work, we mainly focus on the use of CNTs applied to highfrequency interconnect. They are studied and revealed uniquephysical, electrical and thermal properties, which make themextremely attractive for many applications in the area ofnanoelectronics.In order to help component design, two modeling approaches areproposed: one is based on mesoscopic model for theelectromagnetic properties of arrays of nanotubes, the other oneon circuit simulation for RF applications. All of them areconsidering the quantum effects of the CNTs.Several test structures are considered such as flipchip reportbased on CNTs bumps and wireless interconnect based on CNTsmonopole. Experimental works are conducted with success. Theyvalidate theoretical approaches and specific processes.

WSH6 Advanced numerical tools for the multiscalemultiphyiscs modelling of carbonbasedinterconnectionsL. Pierantoni ; D. Mencarelli ; F. Coccetti ; Università Polietcnicadelle Marche, LAASCNRS FranceFullwave multiphysics techniques aimed at the investigation ofthe combined electromagneticcoherent transport phenomena incarbonbased nanostructures/devices have been recentlyintroduced. The quantum transport is modeled by i) discreteHamiltonians at atomistic scale, ii) Schrödinger equation, and/orDirac/Diraclike eqs. at continuous level. In this work, we willanalyze: i) electromagneticquantum transport modelling andsimulation of CNTs interconnections with TS , providing RFequivalent circuits, ii) manyterminal graphene nanoribbon(GNR) circuits, Y and T GNR junctions. Moroever, a newinterconnection concept is presented. This consists of aresonating wire antenna, radiating very closely to a graphenepatch, thus inducing plasmon propagation. In particular, weconsider a suspended graphene structure, in order to i)emphasize the intrinsic properties of the material, ii) the changesof propagation characteristics due to a dielectric substrate. Thenumerical computation is achieved by means of a dedicated MoMtechnique, and, for comparison, is tentatively addressed bystandard fullwave simulators. The proposed configuration is notmuch dissimilar to use an STM (Scanning Tunneling Microscopy)probe for near field microwave microscopy: in fact, the STM tipcan be modeled by a filiform antenna protruding, for instance,from a coaxial feed.

WSI

Session: WSI MmW to THz, which Applications with whichTechnology

Chair: Didier Belot, CEA LetiCoChair: Pierre Busson, ST MicroelectronicsAbstract: Millimeter Waves applications are becoming more and

more used for civil markets in the infrastructures,automotive, mobile devices connectivity, and imagingdomains while THz applications remain manly in themilitary domain, even if we can notice tentative forcivil security and health imaging domain. TheWorkshop is organized in three levels of complexity: ina first time in order to target applications mentionedabove, process technologies has to be defined, and wewill have presentations covering SiGe and IIIVprocesses; then we will address modeling issues formillimeter waves and THz frequencies, before havingan overview on different design techniques in SiGe andIIIV processes addressing mmW and THz applications.At the end of the day, we will have an open door onindustrial systems and applications opportunities inTelecommunications infrastructures, mobile devicesand connectivity.

WSI1 SiGe Technologies for mmW and THz applications

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SiGe Technologies for mmW and THz applicationsPascal Chevalier; ST MicroelectronicsSiGe BiCMOS technologies in production today addressapplications such as 77 GHz automotive radar or 100 Gb/s opticalcommunications. They exhibit ~200 GHz fT / ~300 GHz fMAXSiGe HBTs, highQ millimeterwave passives and 0.18µm to0.13µm CMOS. Next generations in development today offerSiGe HBTs featuring ~300 GHz fT and fMAX up to 500 GHz,embedded in 55nm CMOS for the most advanced one. They willimprove the performance of current applications but will also pavethe way for new lowcost applications above 100 GHz. The talkwill review the BiCMOS developments carried out inSTMicroelectronics. The vertical and the lateral scaling of the SiGeHBT will be discussed and the outcome of these studies, withrespect to the HF performances (fT, fMAX, noise, power), will bepresented. Last 0.13µm and 55nm BiCMOS platforms(respectively BiCMOS9MW and BiCMOS055) fromSTMicroelectronics will be presented.

WSI2 IIIV Technologies for mmW and THzapplicationsMohamed Zaknoune; IEMN Lille, FranceThe increasing demand in the market in terms of data rate,speed, mobile devices has created a competition between devicetechnologies. The demand in terms of low noise amplification,power amplification and power generation in the millimeter andsubmillimeter waves range i.e. 100 GHz−1THz is becoming moreand more crucial. For these very high frequency applications, IIIV transistors such as the Double Heterojunction Bipolar Transistor(DHBT) and the High Electron mobility Transistor (HEMT) or THzphotomixer such as UniTravelingCarrierPhotodiode (UTC) arethe inevitable devices. During this last decade, immense effortshave been undertaken to push their performances at the limit,and sometimes beyond, of the THz. It will be shown in whichways these performances have been obtained on IIIVsemiconductors. These different ways include epitaxial design,scaling, interfaces, ohmic contacts.

WSI3 RF frontends for mmWave and THz applicationin SiGe/CMOSUlrich Pfeiffer; University of WuppertalThis workshop will present an overview of siliconbased RF frontends for imaging, radar, and communication applicationsoperating close to and beyond the THzgap. The presentation willfocus on heterodyne and direct detection techniques including adiscussion about the available device technologies and theachievable bandwidth and sensitivity. Heterodyne examplesinclude wideband IQ transmitter and receiver frontends at 240GHz for data transmission towards 100 Gbit/s, a circular polarizedradar transceiver chip at 240 GHz with a range resolution of 3.65mm, and a THz multicolor imager up to 1 THz. Finally, incoherentSiGe sources with 0dBm up to 1/2 THz and THz video cameras inCMOS and SiGe process technologies operating up to 4THz arediscussed.

WSI4 Multifunctional Circuits and Modules Based onIII/V mHEMT Technology for (Sub)MillimeterWave Applications in Space, Communication andSensingMichael Schlechtweg; Fraunhofer InstituteThe transmission of electromagnetic waves in the atmospherefeatures local maxima in the distinguished frequency bandsaround 94, 140, 220, 340, 410, 480, 660, and 850 GHz, makingthem especially attractive for millimeterwave highspeed datalinks and longdistance highresolution radar and imagingsystems. High operating frequencies allow for precise geometricalresolution due to high absolute bandwidth and small wavelength.It also reduces the size of components and antennas,predestining them for lightweight airborne systems, e.g. inunmanned aerial vehicles (UAVs). In comparison to visible andinfrared radiation, a particular benefit of millimeterwaves forimaging and sensing applications is the penetration of dust, fog,rain, snow, and textiles.The workshop presentation covers a broad variety of MMICs andmodules developed at the Frau

9/26/2016 ims2015 | ieee international microwave symposium | … · 2016. 9. 27. · techniques for...

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