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ELEC 5970-003/6970-003 (Fall 2004)Advanced Topics in Electrical Engineering

Designing VLSI for Low-Power and Self-Test

Power Consumption in a CMOS Circuit

Vishwani D. AgrawalJames J. Danaher Professor

Department of Electrical and Computer EngineeringAuburn University

http://www.eng.auburn.edu/~vagrawalvagrawal@eng.auburn.edu

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Motivation• Low power applications

–Remote systems (e.g., satellite)

–Portable systems (e.g., mobile phone)

• Methods of low power design–Reduced supply voltage

–Adiabatic switching

–Clock suppression

–Logic design for reduced activity

–Reduce Hazards (40% in arithmetic logic)

–Software techniques

• Reference: Chandrakasan and Brodersen

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Low-Power Design

• Design practices that reduce power consumption at least by one order of magnitude; in practice 50% reduction is often acceptable.

• General topics– High-level and software techniques– Gate and circuit-level methods– Power estimation techniques– Test power

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VLSI Chip Power Density

40048008

80808085

8086

286386

486Pentium®

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010

Year

Po

wer

Den

sity

(W

/cm

2 )

Hot Plate

NuclearReactor

RocketNozzle

Sun’sSurface

Source: Intel

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Specific Topics on Low-Power

• Power dissipation in CMOS circuits

• Low-power CMOS technologies

• Dynamic reduction techniques

• Leakage power

• Power estimation

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Components of Power

• Dynamic– Signal transitions

• Logic activity• Glitches

– Short-circuit

• Static– Leakage

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Power of a Transition

VVDDDD

GroundGround

CL

R

R

Power

= CLVDD2/2

+ Psc

Vi

Vo

isc

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Short Circuit Current, isc(t)

Time (ns)0 1

Amp

Volt

VDD

isc(t)45μA

0

Vi(t)Vo(t)

VDD - VTp

VTn

tB tE

Iscmaxr

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Peak Short Circuit Current

• Increases with the size (or gain, β) of transistors

• Decreases with load capacitance, CL

• Largest when CL= 0

• Reference: M. A. Ortega and J. Figueras, “Short Circuit Power Modeling in Submicron CMOS,” PATMOS’96, Aug. 1996, pp. 147-166.

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Short-Circuit Energy per Transition

• Escr=∫tB

tE VDD isc(t)dt = (tE – tB) IscmaxrVDD/2

• Escr = tr (VDD+ VTp-VTn) Iscmaxr/2

• Escf = tf (VDD+ VTp-VTn) Iscmaxf/2

• Escf = 0, when VDD = |VTp| + VTn

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Short-Circuit Energy

• Increases with rise and fall times of input

• Decreases for larger output load capacitance

• Decreases and eventually becomes zero when VDD is scaled down but the threshold

voltages are not scaled down

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Short-Circuit Power Calculation

• Assume equal rise and fall times

• Model input-output capacitive coupling (Miller capacitance)

• Use a spice model for transistors– T. Sakurai and A. Newton, “Alpha-power Law

MOSFET model and Its Application to a CMOS Inverter,” IEEE J. Solid State Circuits, vol. 25, April 1990, pp. 584-594.

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Psc vs. C

C (fF)

Input rise time3ns

0%

45%

0.5ns

Psc

/Pto

tal

0.7μ CMOS

35 75

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Technology Scaling

• Scale down by factors of 2 and 4, i.e., model 0.7, 0.35 and 0.17 micron technologies

• Constant electric field assumed

• Capacitance scaled down by the technology scale down factor

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Technology Scaling Results

tr (ns)0%

70%

Psc

/Pto

tal

L=0.7μ, C=40fF

0.4 1.6

10%

L=0.35μ, C=20fF

L=0.17μ, C=10fF

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Effects of Scaling Down

• 1-16% short-circuit power at 0.7 micron

• 4-37% at 0.35 micron

• 12-60% at 0.17 micron

• Reference: S. R. Vemuru and N. Steinberg, “Short Circuit Power Dissipation Estimation for CMOS Logic Gates,” IEEE Trans. on Circuits and Systems I, vol. 41, Nov. 1994, pp. 762-765.

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Summary: Short-Circuit Power

• Short-circuit power is consumed by each transition (increases with input transition time).

• Reduction requires that gate output transition should not be slower than the input transition (faster gates can consume more short-circuit power).

• Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power.

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Components of Power

• Dynamic– Signal transitions

• Logic activity• Glitches

– Short-circuit

• Static– Leakage

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Leakage Power

IG

ID

Isub

IPT

IGIDL

n+ n+

GroundVDD

R

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Leakage Current Components

• Subthreshold conduction, Isub

• Reverse bias pn junction conduction, ID

• Gate induced drain leakage, IGIDL due to

tunneling at the gate-drain overlap

• Drain source punchthrough, IPT due to short

channel and high drain-source voltage

• Gate tunneling, IG through thin oxide

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Subthreshold Current

Isub = μ0 Cox (W/L) Vt2 exp{(VGS-VTH)/nVt}

μ0: carrier surface mobility

Cox: gate oxide capacitance per unit area

L: channel lengthW: gate widthVt = kT/q: thermal voltage

n: a technology parameter

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IDS for Short Channel Device

Isub = μ0 Cox (W/L) Vt2 exp{(VGS-VTH+ηVDS)/nVt}

VDS = drain to source voltage

η: a proportionality factor

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Increased Subthreshold Leakage

0 VTH’ VTH

Lo

g I

sub

Gate voltage

Scaled device

Ic

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Summary: Leakage Power

• Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power.

• For a gate it is a small fraction of the total power; it can be significant for very large circuits.

• Scaling down features requires lowering the threshold voltage, which increases leakage power; roughly doubles with each shrinking.

• Multiple-threshold devices are used to reduce leakage power.

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Components of Power

• Dynamic– Signal transitions

• Logic activity• Glitches

– Short-circuit

• Static– Leakage

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Power of a Transition

VVDDDD

GroundGround

CL

R

R

Power

= CLVDD2/2

+ Psc

Vi

Vo

isc

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Dynamic Power

• Each transition of a gate consumes CV2/2.

• Methods of power saving:– Minimize load capacitances

• Transistor sizing• Library-based gate selection

– Reduce transitions• Logic design• Glitch reduction

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Glitch Power Reduction

• Design a digital circuit for minimum transient energy consumption by eliminating hazards

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Theorem 1• For correct operation with minimum

energy consumption, a Boolean gate must produce no more than one event per transition

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• Given that events occur at the input of a gate (inertial delay = d ) at times t1

< . . . < tn , the number of events at the

gate output cannot exceed

Theorem 2

min ( min ( n n , 1 + ), 1 + )ttnn – t – t11

----------------dd

ttnn - t - t11

tt11 t t22 t t33 t tnn timetime

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Minimum Transient Design

• Minimum transient energy condition for a Boolean gate:

| t| tii - t - tjj | < d | < d

Where tWhere tii and t and tjj are arrival times of input are arrival times of input

events and d is the inertial delay of gateevents and d is the inertial delay of gate

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Balanced Delay Method

• All input events arrive simultaneously• Overall circuit delay not increased• Delay buffers may have to be inserted

11 111111 11

111111

33

11 11

4?4?

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Hazard Filter Method• Gate delay is made greater than maximum input path

delay difference• No delay buffers needed (least transient energy)• Overall circuit delay may increase

22 111111 11

22111111 11

1?1?3?3?

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Linear Program

• Variables: gate and buffer delays

• Objective: minimize number of buffers

• Subject to: overall circuit delay

• Subject to: minimum transient condition for multi-input gates

• AMPL, MINOS 5.5 (Fourer, Gay and Kernighan)

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Variables: Full Adder add1b

1111

11 11

1111

11

11

11

0000

00

0000

00

00 0000

0000

00

00

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Objective Function

• Ideal: minimize the number of non-zero delay buffers

• Actual: sum of buffer delays

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Specify Critical Path Delay

1111

11 11

1111

11

11

11

0000

00

0000

00

00 0000

0000

00

00

Sum of delays on critical path ≤ Sum of delays on critical path ≤ maxdelmaxdel

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Multi-Input Gate Condition

11

11 11

11

0000

00

0000

00

d1d1

d2d2

dd

d1 - d2 ≤ dd1 - d2 ≤ dd2 - d1 ≤ dd2 - d1 ≤ d

dd

dd

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AMPL Solution: maxdel = 6

2211

11 11

1111

22

11

22

22

11

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AMPL Solution: maxdel = 7

2222

11 11

1111

11

11

33

22

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AMPL Solution: maxdel ≥ 11

2233

11 11

1111

44

33

55

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Power Estimates for add1b

maxdelmaxdelNo.No.

ofofbuf.buf.

Power* with respect to Ref.Power* with respect to Ref.

Ref: model del.Ref: model del. Ref: unit del.Ref: unit del.

PeakPeak Ave.Ave. PeakPeak Ave.Ave.

66

77

≥≥1111

22

11

00

0.600.60

0.560.56

0.520.52

0.890.89

0.850.85

0.800.80

0.600.60

0.560.56

0.520.52

0.900.90

0.860.86

0.810.81

* Hsiao et al., ICCAD-97

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Power Calculation in Spice

VDDVDD

GroundGround

CircuitLarge C

Open at t = 0

Ref.: M. Shoji, CMOS Digital Circuit Technology, Prentice Hall, 1988, p. 172.

t

En

erg

y,

E(t

)E(t) = -- C VDD 2 - -- C V 2 ~ C VDD ( VDD - V )

1 1

2 2

V

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Power Dissipation of ALU4E

ner

gy

in n

an

ojo

ule

s

0

1

2

3

4

5

6

7

0.0 0.5 1.0 1.5 2.0microseconds

Original ALUdelay ~ 3.5ns

Minimum energy ALUdelay ~ 10ns

1 micron CMOS, 57 gates, 14 PI, 8 PO100 random vectors simulated in Spice

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F0 Output of ALU4S

ign

al A

mp

litu

de

, Vo

lts

0

5

0 40 80 120 160nanoseconds

Original ALU, delay = 7 units (~3.5ns)

Minimum energy ALU, delay = 21 units (~10ns)

5

0

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References• E. Jacobs and M. Berkelaar, “Using Gate Sizing to Reduce

Glitch Power,” Proc. ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing, Nov. 1996, pp. 183-188; also Int. Workshop on Logic Synthesis, May 1997.

• V. D. Agrawal, “Low-Power Design by Hazard Filtering,” Proc. 10th Int. Conf. VLSI Design, Jan. 1997, pp. 193-197.

• V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method,” Proc. 12th Int. Conf. VLSI Design, Jan. 1999, pp. 434-439.

• Last two papers are available at website http://www.eng.auburn.edu/~vagrawal

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A Limitation

• Constraints are written by path

enumeration.

• Since number of paths in a circuit can be

exponential in circuit size, the formulation

is infeasible for large circuits.

• Example: c880 has 6.96M constraints.

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Timing Window

• Define two timing window variables per gate

output:

– ti Earliest time of signal transition at gate i.

– Ti Latest time of signal transition at gate i.t1, T1

tn, Tn

.

.

.

ti, Ti

Ref: T. Raja, Master’s Thesis, Rutgers Univ., 2002

i

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Linear Program

• Gate variables d4 . . . d12

• Buffer Variables d15 . . . d29

• Corresponding window variables t4 . . . t29 and T4 . . . T29.

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Multiple-Input Gate Constraints

For Gate 7:

T7 > T5 + d7; t7 < t5 + d7; d7 > T7 - t7;

T7 > T6 + d7; t7 < t6 + d7;

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Single-Input Gate Constraints

T16 + d19 = T19 ;

t16 + d19 = t19 ;

Buffer 19:

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Overall Delay Constraints

T11 < maxdelay

T12 < maxdelay

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Advantage of Timing Window

• Path constraints (exponential in n):

2 × 2 × … 2 = 2n paths between I/O pair• A single variable specifies I/O delay. Total variables,

O(n).• LP constraint set is linear in the size of circuit.

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Comparison of Constraints

Number of gates in circuit

Nu

mb

er

of

con

str

ain

ts

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Results: 1-Bit Adder

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Estimation of Power• Circuit is simulated by an event-driven

simulator for both optimized and un-optimized gate delays.

• All transitions at a gate are counted as Events[gate].

• Power consumed Events[gate] x # of fanouts.

• Ref: “Effects of delay model on peak power estimation of VLSI circuits,” Hsiao, et al. (ICCAD`97).

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Original 1-Bit Adder

Colo

r co

des

for

num

ber

of

transi

tions

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Optimized 1-Bit Adder

Colo

r co

des

for

num

ber

of

transi

tions

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Results: 1-Bit AdderSimulated over all possible vector transitions

•Average power = optimized/unit delay

= 244 / 308 = 0.792

•Peak power = optimized/unit delay

= 6 / 10 = 0.60

Power Savings :

Peak = 40 %

Average = 21 %

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Results: 4-Bit ALU

maxdelay Buffers inserted

7 5

10 2

12 1

15 0

Power Savings :

Peak = 33 %, Average = 21 %

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Benchmark Circuits

Circuit

C432

C880

C6288

c7552

Maxdel.(gates)

1734

2448

4794

4386

No. ofBuffers

9566

6234

294120

366111

Average

0.720.62

0.680.68

0.400.36

0.380.36

Peak

0.670.60

0.540.52

0.360.34

0.340.32

Normalized Power

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Physical Design

Gatel/w Gate

l/w

Gatel/w

Gatel/w

Gate delay modeled as a linear function of gate size, total load capacitance, and fanout gate sizes (Berkelaar and Jacobs, 1996).

Layout circuit with some nominal gate sizes.

Enter extracted routing delays in LP as constants and solve for gate delays.

Change gate sizes as determined from a linear system of equations.

Iterate if routing delays change.

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Power Dissipation of ALU4

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References• R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling

Language for Mathematical Programming, South San Francisco: The Scientific Press, 1993.

• M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC Workshop, Mierlo, The Netherlands, Nov. 1996, pp. 183-188.

• V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc. 10th Int’l Conf. VLSI Design, Jan. 1997, pp. 193-197.

• V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and Linear Programming Method,” Proc. 12th Int’l Conf. VLSI Design, Jan. 1999, pp. 434-439.

• M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, pp. 45-51.

• T. Raja, A Reduced Constraint Set Linear Program for Low Power Design of Digital Circuits, Master’s Thesis, Rutgers Univ., New Jersey, 2002.

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Conclusion• Glitch-free design through LP: constraint-set is linear in the size of the circuit.

• LP solution:

– Eliminates glitches at all gate outputs,

– Holds I/O delay within specification, and

– Combines path-balancing and hazard-filtering to minimize the number of

delay buffers.

• Linear constraint set LP produces results exactly identical to the LP requiring

exponential constraint-set.

• Results show peak power savings up to 68% and average power savings up

to 64%.