80x96 family microcontrollers - devi ahilya · pdf file2011 microcontrollers-... 2nd ed. raj...
TRANSCRIPT
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Chapter 14
80x96 Family Microcontrollers80x96 Family Microcontrollers
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education2
Interrupt Handling System
Lesson 12
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education3
Interrupt mask bits (primary and
secondary level)
• PSW lower byte (SFR at 0x08) saves the mask
bits for multiple interrupt source groups and
peripheral server enable (PSE) bit to support
DMA operations
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education4
Interrupt Masks
Primary
Mask
Secondary
Masks
By setting I bit at PSW-Hi
INT_Mask PSW-Lo at 08H
write
INT_Mask1 at 13H write
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education5
Interrupt vectors
• Between 0x0100H and 0x207F there are P3
and P4 port registers, Interrupt vectors and
PTS vectors
• Lower table of interrupt vectors at 2000H to
2013H
• Upper Table at 2030H to 203FH
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education6
Address
Interrupt Vectors
203E-3F T1or T2 overflow lowest
2000-01H Timers 1 and 2
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education7
Interrupt-mask registers
and Interrupt-Pending Registers
• Nine Bytes of SFRs Common in all 4 Windows
• Zero register
• 08H and 13H Two bytes for interrupt-mask registers (one only in 8096)
• 09H, 12H Two bytes for interrupt-pending registers (one only in 8096)
• One byte for window select register
• Two bytes for SPL-SPH.
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education8
Interrupt Identification flag at SP_STAT, IOS1, IOS0
For Maskable interrupts
Pending
Register
INT_Pend read at 09H te
INT_Pend1 at 12H write
Interrupt Pending Identification
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education9
INT_MaskWhen write 08H
INT_Mask1 When read 13H
interrupt mask register1
interrupt mask register
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education10
Hardware interrupt pins
• EXINT (maskable) [P2.2 external interrupt,
EXINT]
• EXINT1 (maskable) [P0.7 EXINT1]
• NMI Interrupt (non-maskable)
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education11
Generating interrupt on HSO
• HSO_Command bit b4 [b20]= 1
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education12
Generating Timer overflow interrupts
• T1OVIE and T2OVIE interrupt on overflow
enable bits to unmask the interrupts on
timeouts of timers 1and 2 at IOC1 (Input-
Output Control 1 Register).
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education13
Software Interrupts
• A Software timer interrupt causes execution of
a service routing on successful comparison but
no change in an HSO output pin level
• Four software timers are programmable
• Command bits in HSO_CAM at 0x0006
(write)
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education14
Flags for interrupts of software timer
• IOS1.0, IOS1.1, ISO.2 and ISO.3,
respectively, Software timer 0, software timer
1, software timer 2, and software timer 3
interrupt occurrence flag bits
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education15
Seventenn Interrupts
• Interrupt at NMI pin (highest priority)
Interrupt at HSI unit
• EXINT1 P0.7 pin Interrupt
• T2 Overflow
• T2 Capture when internal clocking
• HSI FIFO half-full interrupt
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education16
Seventenn Interrupts
• Serial Receiver RI set
• Serial Transmitter Empty TI set
• Unimplemented opcode Instruction
• Trap on External Interrupt,
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education17
Seventenn Interrupts
• EXINT
• SI interface Interrupts
• Any or both TI (transmitter interrupt) and
RI(Receiver Interrupt)
• Software Timers Interrupts,
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education18
Seventeen Interrupts
• ADCstart at T2 resetHSI pin 0 input instance
Interrupt
• HSO Interrupts HSO.0 to HSO.5
• Interrupts from the HSI capture data ready and
FIFO full
• A/D conversion over interrupts
• Interrupts from Any or both T1 and T2(lowest
priority)
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education19
4th entry interrupt
HSI.x pin capture interrupts
High
T2OVFand then T2CAP
FIFO full
T2
RI and then TxEmpty
HSI-FIFO
RI and TxEI
WDT overflow intr..WDT
Maskable Interrupts Priority
Low
External pin intr..EXINT
Serial Devices interrupts
Synchronous
SI, SI UART
mode
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education20
HSO events interrupts
software timer interrupts, AD conversion start,T2 Reset
High
HSI.0 pin capture interrupt
SWTs/ADC
HSI.0
Capture Ready or FIFO full
HSO
HSI
conversion overADC
Maskable Interrupts Priority
Low
Overflow intr..T1 orT2
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Pearson Education21
• NMI pin interrupt Highest Priority
Non Maskable Interrupts
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Pearson Education22
• Maskable EXINT1 next highest priority
• Maskable T2Overflow next highest
• Maskable T2CAP next highest
Maskable Interrupts
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Pearson Education23
• HSI-FIFO Half full next highest
• RI serial next highest
• Tx empty next highest
• Unimplemented opcode WDT timeout-next highest
Maskable Interrupts
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Pearson Education24
• Software Interrupt
• Trap instruction-next to WDT Priority
Maskable Interrupts
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Pearson Education25
• P2.2 EXINT pin interrupt next highest
• Any TI or RI SI interrupt next highest
• 4 SWTs interrupts
• ADC start
• T2 reset next highest
Maskable Interrupts
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Pearson Education26
• HSI.0 pin time-capture interrupt next highest priority
• HSO.0-HSO.5 interrupt next highest
• HSI capture data ready
• FIFO full interrupt next highest
Maskable Interrupts
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• AD conversion over next priority
• Either T1 or T2 overflow lowest priority
Maskable Interrupts
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2011 Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education28
Steps in Interrupt ISR Start and Return
Push
Pre
emption
PCH, PCH on to stack
Yes in between preemption by
higher priority interrupt if not
defined as masked
Priority Default Assignments
Pop PCH, PCH from stack
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Summary
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Pearson Education30
• Interrupt Handling System
• Interrupt Vectors
• Interrupt masks
• Hardware interrupt pins
• Interrupt Priorities
We learnt
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Pearson Education31
End of Lesson 12 on
Interrupt Handling System