8086 intro

7/21/2019 8086 Intro

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7/21/2019 8086 Intro


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• 8086 is desi,ned to operate in to modes

Minimum and Maimum.

• It can preetches up to 6 instruction bytes

rom memory and &ueues them in order to

speed up instruction eecution.

• !ddress ran,es rom 00000/ to /

• Memory is byte addressable - ery byte has a

separate address.

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Intel 8086 Internal Architecture

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Internal architecture of 8086

• 8086 has two blocks BI an! E"• #he BI han!les all transactions of !ata an!

a!!resses on the buses for E"

• #he BI $erfor%s all bus o$erations such asinstruction fetchin&' rea!in& an! writin&o$eran!s for %e%or( an! calculatin& thea!!resses of the %e%or( o$eran!s" #he

instruction b(tes are transferre! to theinstruction )ueue"

• E e*ecutes instructions fro% the instructions(ste% b(te )ueue"

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• Both units o$erate as(nchronousl( to&i+e the 8086 an o+erla$$in& instruction

fetch an! e*ecution %echanis% which iscalle! as Pi$elinin&" #his results inefficient use of the s(ste% bus an!s(ste% $erfor%ance"

• BI contains Instruction )ueue' Se&%entre&isters' Instruction $ointer' A!!ressa!!er"

• E contains Control circuitr(' Instruction!eco!er' A,' Pointer an! In!e* re&ister'Fla& re&ister"

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BS I-#ERFACE -I# .BI/

Contains

• 6b(te Instruction 1ueue .1/• #he Se&%ent Re&isters .CS' 2S' ES' SS/"

• #he Instruction Pointer .IP/"

• #he A!!ress Su%%in& block .3/

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• These pe!"etchin+ instuctions ae hel# in its FIFO

)ueue$ %ith its 56 (it #ata (us' the BIU "etches two

instuction ()tes in a sin+le memo) c)cle$

• ."te a ()te is loa#e# at the input en# o" the queue'

it automaticall) shi"ts up thou+h the FIFO to the

empt) location neaest the output$

• The E accesses the )ueue fro% the out$ut

en!$ It ea#s one instuction ()te a"te the othe

"om the output o" the queue$

• The inte&als o" no (us acti&it)' which ma) occu

(etween (us c)cles ae known as Idle state.

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O$co!e

2ata

O$co!e )ueue

Fro%

%e%or(

Re$eat the sa%e $roce!ure

for successi+e contents of 1

E*ecute it with !ata b(tes

!eco!e! b( the !eco!er

#ake n! b(te fro% 1 as

o$co!e' !eco!e n! b(te

o$co!e

E*ecute it with !ata b(tes

!eco!e! b( the !eco!er

Is it

Sin&le

b(te7

#ake n! b(te fro% 1 as

o$co!e' !eco!e n! b(te

o$co!e

.2eco!e also !eci!es the no" of

!ata b(tes for the instructions/

$!ate

)ueue

O$co!e n! b(te

(es

-o

#he 1ueue O$eration

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Instruction Queue

• 8086 employs overlapped processing

• When EU is busy decoding or executing current

instruction, the system bus of 8086 may not be in

use.

• t that time, !"U can use buses to fetch up to six

instruction bytes of the instructions next in program

• !"U stores these pre#fetched bytes in a $"$% register

called Instruction Queue

• When EU is ready for its next instruction, it simply

reads the instruction from the &ueue in !"U11

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Instruction Pipeline

• EU of 8086 does not have to 'ait for

!"U to fetch next instruction byte

from memory

• (he presence of a &ueue in 8086

speeds up the processing

• $etching the next instruction 'hile

the current instruction executes is

called "nstruction loo) ahead

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Se&%ente! Me%or(

Co#e se+ment 064B

ata se+ment 064B

*,ta se+ment 064B

tack se+ment 064B

5

MB

The memo) in an 8/8688

(ase# s)stem is o+anie# asse+mente# memo)$

The CU 8/86 is a(le to

a##ess 1()te o" memo)$

The Complete ph)sicall)

a&aila(le memo) ma) (e

#i&i#e# into a num(e o" lo+ical

se+ments$

00000

FFFFF

Ph(sical Me%or(

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• The sie o" each se+ment is 64 B

• . se+ment is an aea that (e+ins at an) location which is

#i&isi(le () 16$

• . se+ment ma) (e locate# an) whee in the memo)

• *ach o" these se+ments can (e use# "o a speci"ic

"unction$

9 Co#e se+ment is use# "o stoin+ the instuctions$

9 The stack se+ment is use# as a stack an# it is use# to stoe the

etun a##esses$

9 The #ata an# e,ta se+ments ae use# "o stoin+ #ata ()te$

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• The 4 se+ments ae Co#e' ata' *,ta an# tack se+ments$• . e+ment is a 64k()te (lock o" memo)$

• The 16 (it contents o" the se+ment e+istes in the BIUactuall) point to the statin+ location o" a paticula se+ment$

• e+ments ma) (e o&elappe# o non!o&elappe#

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Se&%ent re&isters

• In 8/8688 the pocessos ha&e 4 se+ments

e+istes

• Co#e e+ment e+iste 0C' ata e+mente+iste 0' *,ta e+ment e+iste 0* an#

tack e+ment 0 e+iste$

• .ll ae 16 (it e+istes$

• *ach o" the e+ment e+istes stoe the uppe 16(it a##ess o" the statin+ a##ess o" thecoespon#in+ se+ments$

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Instruction $ointer su%%in& block

• #he instruction $ointer re&ister contains a 56bit offseta!!ress of instruction that is to be e*ecute! ne*t"

• #he IP alwa(s references the Co!e se&%ent re&ister.CS/"

• #he +alue containe! in the instruction $ointer is calle!

as an offset because this +alue %ust be a!!e! to thebase a!!ress of the co!e se&%ent' which is a+ailable inthe CS re&ister to fin! the 0bit $h(sical a!!ress"

• #he +alue of the instruction $ointer is incre%ente! aftere*ecutin& e+er( instruction"

• #o for% a 0bit a!!ress of the ne*t instruction' the 56 bita!!ress of the IP is a!!e! .b( the a!!ress su%%in&block/ to the a!!ress containe! in the CS ' which hasbeen shifte! four bits to the left"

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• #he followin& e*a%$les shows the CS9IP sche%e of

a!!ress for%ation9

Insertin& a he*a!eci%al 04 .0000B/

with the CSR or shiftin& the CSR

four binar( !i&its left

: ; B A 0 . C S / <

8 A B ; . I P /

: 2 6 = ; .ne*t a!!ress/

:;BA 8AB;CS IP

:;BA0

:26;=

;;B>F

Co!e se&%ent

8AB; .offset/

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• E*a%$le For A!!ress Calculation .se&%ent9 offset/

• I" the #ata se+ment stats at location 1///h an# a #ata

e"eence contains the a##ess 2-h whee is the actual#ata:

Re)uire! A!!ress

Offset

Se&%ent A!!ress

0000 0000 0050 5005

0000

0005 0000 0000 0050 5005

0005 0000 0000 0000

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E?EC#IO- -I#

• 2eco!es instructions fetche! b( the BI

• @enerate control si&nals'

• E*ecutes instructions"

#he %ain $arts are9

• Control Circuitr(

• Instruction !eco!er

• A,

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.; .<

B; B<

C; C<

; <

B

I

I

8 (its 8 (its

16 (its

Accu%ulator

Base

Count

2ata

Stack Pointer

Base Pointer

Source In!e*

2estination In!e*

A?

B?

C?

2?

Pointer

In!e*

8 (its 8 (its

16 (its

Accu%ulator

Base

Count

2ata

Stack Pointer

Base Pointer

Source In!e*

2estination In!e*

E?EC#IO- -I# @eneral Pur$ose Re&isters

E?EC#IO- -I# @ l P R i t

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E?EC#IO- -I# @eneral Pur$ose Re&isters

Register Purpose* Word multiply, 'ord divide, 'ord " +%

!yte multiply, byte divide, byte "+%, decimalarithmetic

- !yte multiply, byte divide

!* tore address information

/* tring operation, loops

/ ariable shift and rotate

= %o# multipl)' wo# #i&i#e' in#iect I>0Use# to hol# I> a##ess #uin+ I> instuctions$ I" the esult is moe than

16!(its' the lowe o#e 16!(its ae stoe# in accumulato an# hi+he o#e16!(its ae stoe# in = e+iste

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Pointer An! In!e* Re&isters

• use# to keep o""set a##esses$

• Use# in &aious "oms o" memo) a##essin+$• In the case o" an# B the #e"ault e"eence to "om a ph)sical

a##ess is the tack e+ment 0!will (e #iscusse# un#e theBIU

• The in#e, e+istes 0I ? I an# the B= +eneall) #e"ault to theata se+ment e+iste 0$

@ tack pointe

9 Use# with to access the stack se+ment

B@ Base ointe 9 imail) use# to access #ata on the stack

9 Can (e use# to access #ata in othe se+ments

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• I@ ouce In#e, e+iste

9 is equie# "o some stin+ opeations

9 %hen stin+ opeations ae pe"ome#' the I e+iste points

to memo) locations in the #ata se+ment which is a##esse#() the e+iste$ Thus' I is associate# with the instin+ opeations$

• I@ estination In#e, e+iste

9 is also equie# "o some stin+ opeations$

9 %hen stin+ opeations ae pe"ome#' the I e+iste pointsto memo) locations in the #ata se+ment which is a##esse#() the * e+iste$ Thus' I is associate# with the * in

stin+ opeations$

• The I an# the I e+istes ma) also (e use# to access #ata

stoe# in aa)s

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E?EC#IO- -I# Fla& Re&ister

• . "la+ is a "lip "lop which in#icates some con#itions po#uce# ()

the e,ecution o" an instuction o contols cetain opeations o"

the *U $

• In 8/86 The *U contains

a 16 (it "la+ e+iste

- o" the 16 ae acti&e "la+s an# emainin+ 7 ae un#e"ine#$

6 "la+s in#icates some con#itions! status "la+s

3 "la+s 9contol Ala+s

U U U U OF

DF

IF TF SF ZF U AF

U PF U CF

Carr(

O+er flow 2irectionInterru$t

#ra$

Si&n

eroAu*iliar(

Parit(

nuse!

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E?EC#IO- -I# Fla& Re&ister

Fla& Pur$oseCa) 0CA ;ol#s the ca) a"te a##ition o the (oow a"te su(taction$

.lso in#icates some eo con#itions' as #ictate# () some

po+ams an# poce#ues $

ait) 0A A/o## pait)' A1e&en pait)$

.u,ilia) 0.A ;ol#s the ca) 0hal" 9 ca) a"te a##ition o (oow a"te

su(taction (etween (it positions 3 an# 4 o" the esult

0"o e,ample' in BC a##ition o su(taction$

Deo 0DA hows the esult o" the aithmetic o lo+ic opeation$

D1 esult is eo$ D/ The esult is /

i+n 0A ;ol#s the si+n o" the esult a"te an aithmeticlo+icinstuction

e,ecution$ 1 ne+ati&e' /

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2-

Fla& Pur$ose

Tap 0TA . contol "la+$*na(les the tappin+ thou+h an on!chip #e(u++in+

"eatue$

Inteupt 0IA

. contol "la+$

Contols the opeation o" the IETF 0inteupt equestI/ IETF pin #isa(le#$ I1 IETF pin ena(le#$

iection 0A

. contol "la+$

It selects eithe the incement o #ecement mo#e "o I

an# o I e+istes #uin+ the stin+ instuctions$

>&e"low 0>A

>&e"low occus when si+ne# num(es ae a##e# o

su(tacte#$ .n o&e"low in#icates the esult has e,cee#e#

the capacit) o" the achine

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E*ecution unit Fla& Re&ister

• i, o" the "la+s ae status in#icatos e"lectin+

popeties o" the last aithmetic o lo+ical instuction$• Ao e,ample' i" e+iste .< 7Ah an# the instuction

. .<'1 is e,ecute# then the "ollowin+ happen

A, 80hCF 0 thee is no ca) out o" (it 7

PF 0 8/h has an o## num(e o" ones

AF 5 thee is a ca) out o" (it 3 into (it 4F 0 the esult is not eo

SF 5 (it se&en is one

OF 5 the si+n (it has chan+e#

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Min/Max Pin-out Moes

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!ogical Signals

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"#"" Details

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Min/Max Moes

• Mini%u% an! Ma*i%u% Mo!es

9 The minimum mo#e is selecte# () appl)in+

lo+ic 1 to the E =G input pin$ This is a

sin+le micopocesso con"i+uation$

• The ma,imum mo#e is selecte# ()

appl)in+ lo+ic / to the E =G input pin$

This is a multi mico pocessoscon"i+uation$

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Signal Description-$

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Signal Description-%

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Signal DescriptionMax Moe

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Me&or' Organi(ation

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Reser)e Me&or'!ocations

3-

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Min Moe !ogicalPin out

4/

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Min MoeInter*ace-$

• When the 1inimum mode operation isselected, the 8086 provides all controlsignals needed to implement the memoryand "+% interface

• (he minimum mode signal can be divided

into the follo'ing basic groups2address+data bus, status, control, interruptand 31.

• ddress+3ata !us 2 t+ese lines ser)et,o *unctions s an address bus is 40bits long and consists of signal lines 0

through 5. 5 represents the 1! and0 !. 40bit address gives the 8086 a51byte memory address space.

• "ndependent "+% address space 'hich 67bytes in length

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Min MoeInter*ace-%

• (he 56 data bus lines 30 through 359are actually multiplexed 'ith addresslines 0 through 59 respectively. (hebus 'or)s as an address bus during:rst machine cycle and as a data busduring next machine cycles. 359 isthe 1! and 30 !

• When acting as a data bus, they carry

read+'rite data for memory,input+output data for "+% devices, andinterrupt type codes from an interruptcontroller

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Min MoeInter*ace-.

• Status signal (he four most signi:cantaddress lines 5 through 56 are alsomultiplexed but in this case 'ith statussignals 6 through ;. (hese status bits areoutput on the bus at the same time that dataare transferred over the other bus lines.

• !it 7 and ; together form a 4 bit binarycode that identi:es 'hich of the 8086internal segment registers are used togenerate the physical address output on theaddress bus during the current bus cycle

• /ode 7,; < 00 identi:es a register )no'nas extra segment register as the source ofthe segment address

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Min MoeInter*ace-0

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Min MoeInter*ace-2

• E is a pulse to logic 5 that signalsexternal circuitry 'hen a valid address'ord is on the bus. (his address must belatched in external circuitry on the 5#to#0edge of the pulse at E.

• nother control signal that is producedduring the bus cycle is !-E ban) highenable. ogic 0 on this used as a memoryenable signal for the most signi:cant bytehalf of the data bus 38 through 35. (heseline also serves a second function, 'hich

is as the ? status line• Using the 1+"% and 3(+@ lines, the 8086signals 'hich type of bus cycle is inprogress and in 'hich direction data areto be transferred over the bus.

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i

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Min MoeInter*ace-3

• (he logic level of 1+"% tells external circuitry'hether a memory or "+% transfer is ta)ingplace over the bus. ogic 5 at this outputsignals a memory operation and logic 0 an "+%operation.

• (he direction of data transfer over the bus issignalled by the logic level output at 3([email protected] this line is logic 5 during the datatransfer part of a bus cycle, the bus is in thetransmit mode. (herefore, data are either'ritten into

• memory or output to an "+% device• %n the other hand, logic 0 at 3(+@ signals thatthe bus is in the receive mode. (hiscorresponds to reading data from memory orinput of data from an input port

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Min MoeInter*ace-"

• (he signal read @3 and 'rite W@ indicatesthat a read bus cycle or a 'rite bus cycle isin progress. (he 8086 s'itches W@ to logic0 to signal external device that valid 'riteor output data are on the bus

• %n the other hand, @3 indicates that the8086 is performing a read of data of thebus. 3uring read operations, one othercontrol signal is also supplied. (his is 3EAB data enableC and it signals externaldevices 'hen they should put data on thebus

• (here is one other control signal that isinvolved 'ith the memory and "+%interface. (his is the @E3D signal

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Min MoeInter*ace-4

• @E3D signal is used to insert 'ait statesinto the bus cycle such that it is extendedby a number of cloc) periods. (his signalis provided by an external cloc)generator device and can be supplied by

the memory or "+% subsystem to signalthe 8086 'hen they are ready to permitthe data transfer to be completed.

• "nterrupt signals 2 (he )ey interruptinterface signals are interrupt re&uest

B"A(@C and interrupt ac)no'ledgeB "A(C• "A(@ is an input to the 8086 that can be

used by an external device to signal thatit need to be serviced

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Min MoeInter*ace-$#

• ogic 5 at "A(@ represents an activeinterrupt re&uest. When an interruptre&uest has been recognied by the 8086,it indicates this fact to external circuit 'ithpulse to logic 0 at the "A( output

• (he (E( input is also related to theexternal interrupt interface. Execution of aW"( instruction causes the 8086 to chec)the logic level at the (E( input

• "f the logic 5 is found, the 1FU suspends

operation and goes into the idle state. (he8086 no longer executes instructions,instead it repeatedly chec)s the logic levelof the (E( input 'aiting for its transitionbac) to logic 0

5/

Mi M

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Min MoeInter*ace-$$

• s (E( s'itches to 0, execution resume'ith the next instruction in the program. (his feature can be used to synchronie theoperation of the 8086 to an event inexternal hard'are.

• (here are t'o more inputs in the interruptinterface2 the non#mas)able interrupt A1"and the reset interrupt @EE(

• %n the 0#to#5 transition of A1" control ispassed to a non#mas)able interrupt serviceroutine. (he @EE( input is used to provide

a hard'are reset for the 8086. 'itching@EE( to logic 0 initialies the internalregister of the 8086 and initiates a resetservice routine

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Min MoeInter*ace-$%

• 31 "nterface signals 2(he direct memoryaccess 31 interface of the 8086 minimummode consist of the -%3 and -3 signals

• When an external device 'ants to ta)econtrol of the system bus, it signals to the

8086 by s'itching -%3 to the logic 5 level.t the completion of the current bus cycle,the 8086 enters the hold state. "n the holdstate, signal lines 30 through 359, 56+;through 5+6, !-E, 1+"%, 3(+@, @3, W@,

3EA and "A(@ are all in the high G state. (he8086 signals external device that it is in thisstate by s'itching its -3 output to logic 5level

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Max Moe

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Max Moe5loc6 Diagra&

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Max MoeInter*ace-$

• When the 8086 is set for the maximum#mode con:guration, it provides signals forimplementing a multiprocessor +coprocessor system environment

• !y multiprocessor environment 'e meanthat one microprocessor exists in the

system and that each processor isexecuting its o'n program• Usually in this type of system

environment, there are some systemresources that are common to allprocessors

• (hey are called as global resources. (hereare also other resources that are assignedto speci:c processors. (hese are )no'n aslocal or private resources

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Max MoeInter*ace-%

• "n multiple processor situation asecond processor is in the system.!oth processors do not access thebus at the same time

• %ne passes the control of the systembus to the other and then maysuspend its operation

• "n the maximum#mode 8086 system,facilities are provided for

implementing allocation of globalresources and passing bus control toother microprocessor or coprocessor.

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Max Con7guration

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Max Con7gurationUsing "%"" 5us Controller

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"%"" Pin out

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M M

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Max MoeInter*ace-.

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M M

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Max MoeInter*ace-0

• (he 8488 produces one or t'o of these eightcommand signals for each bus cycles. $orinstance, 'hen the 8086 outputs the code450 e&uals 005, it indicates that an "+%read cycle is to be performed

• "f the code 555 is output by the 8086, it issignalling that no bus activity is to ta)e place

• (he control outputs produced by the 8488are 3EA, 3(+@ and E. (hese ; signalsprovide the same functions as thosedescribed for the minimum system mode.

(his set of bus commands and control signalsis compatible 'ith the 1ultibus Ban industrystandardC for interfacing microprocessorsystems.

5-

M M

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Max MoeInter*ace-1

• "%"4 5us Ar8iter 9 !us rbitration andoc) ignals 2 (his device permits processorsto reside on the system bus. "t does this byimplementing the 1ultibus arbitrationprotocol in an 8086#based system

• ddition of the 8488 bus controller and 848bus arbiter frees a number of the 8086 pinsfor use to produce control signals that areneeded to support multiple processors

• !us priority loc) B %/C is one of these

signals. "t is input to the bus arbiter together'ith status signals 0 through 4.

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"%"4 Pin Out

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Max Moe

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Max MoeInter*ace-2

• (he output of 848 are bus arbitrationsignals2 bus busy B!UDC, common busre&uest B/!@HC, bus priority out B!F@%C,bus priority in B!F@AC, bus re&uestB!@EHC and bus cloc) B!/C.

• (hey correspond to the bus exchangesignals of the 1ultibus and are used toloc) other processor oI the system busduring the execution of an instruction bythe 8086

• "n this 'ay the processor can be assuredof uninterrupted access to commonsystem resources such as globalmemory.

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M M

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Max MoeInter*ace-3

• 1ueue Status Si&nals 9 Two new si+nalsthat ae po#uce# () the 8/86 in the

ma,imum!mo#e s)stem ae queue status

outputs H/ an# H1$ To+ethe the) "om

a 2!(it queue status co#e' H1H/• Aollowin+ ta(le shows the "ou #i""eent

queue status

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Max Moe

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Max MoeInter*ace-"

• <ocal Bus Contol i+nal 9 Fequest

ant i+nals@ In a ma,imum mo#e

con"i+uation' the minimum mo#e ;><'

;<. inte"ace is also chan+e#$ These

two ae eplace# () equest+ant lines

FH T/ an# FH T1' especti&el)$ The)

po&i#e a pioitie# (us access

mechanism "o accessin+ the local (us$

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Instruction Set

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Instruction For&at

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Aressing Moes

• ddressing mode indicates a 'ay oflocating data or operands

• 3epending upon the data types used inthe instruction and the memoryaddressing modes, any instruction may

belong to one or more addressingmodes, or some instruction may notbelong to any of the addressing modes

• ddressing modes describe the types ofoperands and the 'ay they are accessed

for executing an instruction. "nstructionsmay be categoried asJ e&uential control =o' instructions and

J /ontrol transfer instructions

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Instruction T'pe Moes

• e&uential control =o' instructions arethe instructions, 'hich after execution,transfer control to the next instructionappearing immediately after it Binse&uenceC in the program

J $or example, the arithmetic, logical, datatransfer and processor control instructionsare se&uential control =o' instructions

• (he control transfer instructions, on theother hand, transfer control to someprede:ned address someho' speci:ed inthe instruction after their execution. $orexample, "A(, /, @E( and KU1Finstructions fall under this category

8086 intro

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