8085 instruction-set new

8085 Instruction Set 1

8085 Instruction Set

Instruction Format

Size of instruction Instruction : 2parts opcode – task to be performed

operand – 8/16 bit data/address, internal register 1 byte instruction : OPCODE

MOV C,A 2 byte instruction : OPCODE 8-bit data/address

MVI D,#F1 3 byte instruction : OPCODE low byte data/address high byte

data/address JMP 2084


Addressing Modes -Types Method of specifying data to be operated by the

instruction – ADDRESSING Intel 8085 uses the following addressing modes:

1. Direct Addressing Mode2. Register Addressing Mode3. Register Indirect Addressing Mode4. Immediate Addressing Mode5. Implied Addressing Mode


Direct Addressing Mode

The address of the operand (data) is given in the instruction itself.LDA 2500 H Load the contents of memory location 2500 H in accumulator.

LDA is the operation. 2500 H is the address of source. Accumulator is the destination.

Register Addressing Mode

Instruction specifies the register in which data is available.MOV A, B Move the contents of register B to A

MOV is the operation. B is the source of data. A is the destination

Register Indirect AddressingMode In this mode, the address of operand is specified by a

register pair.MOV A, M Move data from memory location specified by H-L

pair to accumulator. MOV is the operation. M is the memory location specified by H-L register pair. A is the destination.

Immediate Addressing Mode

In this mode, the operand is specified within the instruction itself.MVI A, 05 H Move 05 H in accumulator

MVI is the operation. 05 H is the immediate data (source). A is the destination.

Implied Addressing Mode

If address of source of data as well as address of destination of result is fixed, then there is no need to give any operand along with the instruction.CMA Complement accumulator

CMA is the operation. A is the source. A is the destination.


• No flags are affected• Register addressing mode•1 byte instruction• MOV B,M – Indirect addressing


• No flags are affected• 2 byte instruction• Immediate addressing mode• MOV M,57 – Indirect addressing or immediate addressing


• No flags are affected• 3 byte instruction• Direct addressing mode


• No flags are affected• one byte instruction • Register indirect addressing mode


• No flags are affected• 3 byte instruction• Immediate addressing mode


• No flags are affected• 3 byte instruction•Direct addressing mode


• No flags are affected• Register indirect addressing mode


• No flags are affected• 3 byte instruction•Direct addressing mode


• No flags are affected• 1 byte instruction• Implied addressing mode


• No flags are affected• 1 byte instruction• Register Indirect addressing mode


• All flags are affected• Register addressing mode• One byte Instruction• ADD M is Indirect addressing mode.


• All flags are affected• Register addressing mode• One byte Instruction• ADC M is Indirect addressing mode.


• All flags are affected• Two byte Instruction.• Immediate addressing mode


• All flags are affected• One byte Instruction.• Register addressing mode• SUB M is Indirect addressing mode.


• All flags are affected• One byte Instruction.• Register addressing mode• SBB M is Indirect addressing mode.


• All flags are affected except carry flag.• One byte Instruction.• Register addressing mode• INR M is Indirect addressing mode.


• No flags are affected• One byte Instruction.• Register addressing mode


• All flags are affected except carry flag.• One byte Instruction.• Register addressing mode• DCR M is Indirect addressing mode.


• No flags are affected• One byte Instruction.• Register addressing mode


PSW (Program Status word) - Flag unaffected * affected 0 reset 1 set S Sign (Bit 7) Z Zero (Bit 6) AC Auxiliary Carry (Bit 4) P Parity (Bit 2) CY Carry (Bit 0)


• All flags are affected.• One byte Instruction.• Register addressing mode• CMP M is Indirect addressing mode.


• All flags are affected.• Two byte Instruction.• Immediate addressing mode


• All other flags are affected.• One byte Instruction.• Register addressing mode• ANA M is Indirect addressing mode.


• All other flags are affected.• Two byte Instruction.• Immediate addressing mode


• All other flags are affected.• One byte Instruction.• Register addressing mode• ORA M is Indirect addressing mode.


• All flags are affected.• One byte Instruction.• Register addressing mode• XRA M is Indirect addressing mode.


• Only carry flag is affected.• One byte Instruction.• Implied addressing mode


PSW (Program Status word) - Flag unaffected * affected 0 reset 1 set S Sign (Bit 7) Z Zero (Bit 6) AC Auxiliary Carry (Bit 4) P Parity (Bit 2) CY Carry (Bit 0)


circular Left shift


circular right shift


Summary – Data transfer

MOV Move MVI Move Immediate LDA Load Accumulator Directly from Memory STA Store Accumulator Directly in Memory LHLD Load H & L Registers Directly from

Memory SHLD Store H & L Registers Directly in

Memory


Summary Data transfer An 'X' in the name of a data transfer instruction implies that it

deals with a register pair (16-bits);

LXI Load Register Pair with Immediate data LDAX Load Accumulator from Address in Register Pair STAX Store Accumulator in Address in Register Pair XCHG Exchange H & L with D & E XTHL Exchange Top of Stack with H & L


Summary - Arithmetic Group Add, Subtract, Increment / Decrement data in registers or memory. ADD Add to Accumulator ADI Add Immediate Data to Accumulator ADC Add to Accumulator Using Carry Flag ACI Add Immediate data to Accumulator Using Carry SUB Subtract from Accumulator SUI Subtract Immediate Data from Accumulator SBB Subtract from Accumulator Using Borrow (Carry) Flag SBI Subtract Immediate from Accumulator Using Borrow (Carry) Flag INR Increment Specified Byte by One DCR Decrement Specified Byte by One INX Increment Register Pair by One DCX Decrement Register Pair by One DAD Double Register Add; Add Content of Register Pair to H & L

Register Pair


Summary Logical Group This group performs logical (Boolean) operations on data in

registers and memory and on condition flags. These instructions enable you to set specific bits in the

accumulator ON or OFF. ANA Logical AND with Accumulator ANI Logical AND with Accumulator Using Immediate Data ORA Logical OR with Accumulator OR Logical OR with Accumulator Using Immediate Data XRA Exclusive Logical OR with Accumulator XRI Exclusive OR Using Immediate Data


The Compare instructions compare the content of an 8-bit value with the contents of the accumulator;

CMP Compare CPI Compare Using Immediate Data The rotate instructions shift the contents of the accumulator one bit position to the left or

right: RLC Rotate Accumulator Left RRC Rotate Accumulator Right RAL Rotate Left Through Carry RAR Rotate Right Through Carry Complement and carry flag instructions: CMA Complement Accumulator CMC Complement Carry Flag STC Set Carry Flag


Summary - Branch Group Unconditional branching

JMP Jump CALL Call RET Return

Conditions NZ Not Zero (Z = 0) Z Zero (Z = 1) NC No Carry (C = 0) C Carry (C = 1) PO Parity Odd (P = 0) PE Parity Even (P = 1) P Plus (S = 0) M Minus (S = 1)

Conditional branching


Summary - Stack

PUSH Push Two bytes of Data onto the Stack POP Pop Two Bytes of Data off the Stack XTHL Exchange Top of Stack with H & L SPHL Move content of H & L to Stack Pointer


I/0 instructions

IN Initiate Input Operation OUT Initiate Output Operation


Summary -Machine Control instructions EI Enable Interrupt System DI Disable Interrupt System HLT Halt NOP No Operation

8085 instruction-set new

Engineering