8051 chap6 interrupts

7/29/2019 8051 Chap6 Interrupts

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H Bch Khoa TP.HCM L Ch Thngwww.tinyurl.com/thongchile

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Chapter 6

Interrupts

The 8051 Microcontroller

L Ch Thng

Ref. I. Scott Mackenzie, The 8051 Microcontroller

Interrupts

When an interrupt occurs, the main program temporarily suspends execution

and branches to the interrupt service routine (ISR), perform the operation, and

terminates with a return from interrupt instruction (RETI).

Hardware

Event

Ref. I. Scott Mackenzie 2L Ch Thng


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Interrupts

An interrupt = Occurrence of a condition (an event)

Deal with the event while another program is executing

Do many things simultaneously

When an interrupt occurs, the main program temporarilysuspends execution and branches to the interrupt service

routine (ISR), perform the operation, and terminates with a

return from interrupt instruction (RETI).

ISR vs. subroutine:

Similarity: CPU executes another program and then returnsto the original program.

Difference: It is NOT known when the main programsuspends execution.


2 external interrupts (/INT0 and /INT1), 2 timer interrupts (TF0 and TF1), a

serial port interrupt (RI or TI), and Timer 2 interrupt (8052 only)

Interrupt Sources



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EA : Global enable/disable - : Undefined ET2: Enable Timer 2 interrupt ES: Enable Serial port interrupt ET1: Enable Timer 1 interrupt EX1: Enable External 1 interrupt

ET0: Enable Timer 0 interrupt EX0: Enable External 0 interrupt

1 = Enable; 0 = Disable

EA - ET2 ES ET1 EX1 ET0 EX0

Enabling and Disabling Interrupts

IE (Interrupt Enable) Register

Eg. Timer 1 interrupt is enabled asfollow:

SETB ET1

SETB EA

or

MOV IE,#10001000B

Eg. External 0 and serial interruptsare enabled as follow:

SETB EX0

SETB ES

SETB EA

or

MOV IE,#10010001BRef. I. Scott Mackenzie 5L Ch Thng

PT2 : Priority for Timer 2 interrupt

PS: Priority for Serial port interrupt

PT1: Priority for Timer 1 interruptPX1: Priority for External 1 interrupt

PT0: Priority for Timer 0 interrupt

PX0: Priority for External 0 interrupt

1 = Higher Level; 0 = Lower Level

- - PT2 PS PT1 PX1 PT0 PX0

Interrupt Priority

IP (Interrupt Priority) Register

If 2 interrupts occur simultaneously a high-priority ISR executes If a low-priority ISR is executing

when a high-priority interrupts the low-priority is interrupted A high-priority interrupt can

interrupt a low-priority ISR. A high-priority ISR cannot be

interrupted. If 2 interrupts of the same priority

occur simultaneously a fixed polling sequence

determines which is serviced first The polling sequence is external 0,

Timer 0, external 1, Timer 1, serialport, Timer 2.Ref. I. Scott Mackenzie 6L Ch Thng


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Processing Interrupts

When an interrupt (an event) occurs:

The corresponding interrupt flag is set

The current instruction completes execution.

The PC is saved on the stack.

The PC is loaded with the interrupt vector, which is the

address of the start of the ISR.

The interrupt flag is automatically cleared, except RI &TI

(and TF2 & EXF2 for 8052)

The ISR executes and takes action in response to theinterrupt.

The ISR finishes with a RETI (return from interrupt) instruction.

This retrieves the old value of the PC from the stack and

execution of the main program continues.Ref. I. Scott Mackenzie 7L Ch Thng

Interrupt Flags and Interrupt Vectors

When an interrupt (an event) occurs, the corresponding interrupt flag is set

Eg. - When a falling edge occur at /INT0 pin, the IE0 flag is set.

- When the Timer 0 is overflow, the TF0 flag is set.

- When the transmit buffer is empty, the TI flag is set.

When an interrupt is accepted, the value loaded into PC is called interruptvector. It is the address of the start of the ISR.

INTERRUPT FLAG VECTOR ADDRESS

System reset RST 0000H

External 0 IE0 0003H

Timer 0 TF0 000BH

External 1 IE1 0013H

Timer 1 TF1 001BH

Serial port RI or TI 0023H

Timer 2 TF 2 or EXF2 002BHRef. I. Scott Mackenzie 8L Ch Thng


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An Example

Assume that Timer 1 interrupt was enabled.

When Timer 1 is overflow TF1 is set (automatically by hardware)

The current PC is saved on the stack

PC 001BH (and the main program is interrupted)

The instruction at address 001BH (i.e. the first instruction of the ISR forTimer 1) executes.

When the ISR is done, the RETI instruction retrieves the old value of the PCfrom the stack and the main program continues.

Question: What will happen if the Timer 1 is NOT overflow (i.e. NO interruptsignal occur) but TF1 is set by software (i.e. by using SETB TF1)?


An Example of a Program Using Small ISR

ORG 0000H ;Reset

LJMP MAIN

ORG 000BH ;Interrupt vector of Timer 0

T0ISR:

RETI ;Return to main programMAIN:

END



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An Example of a Program Using Large ISR

ORG 0000H ;Reset

LJMP MAIN

ORG 0003H ;Interrupt vector of External 0

LJMP E0ISR


LJMP T0ISR

ORG 0013H ;Interrupt vector of External 1

LJMP E1ISR


LJMP T1ISR

ORG 0023H ;Interrupt vector of serial port

LJMP SPISR

ORG 0030H

MAIN:

SJMP $

E0ISR:

RETI

T0ISR:

RETI

ENDRef. I. Scott Mackenzie 11L Ch Thng

ISR Vector table

3-byte instruction

Memory Organization



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A Square Wave Using Timer Interrupt

Write a program using Timer 0 and interrupts to create a 10 kHz

square wave on P1.0

ORG 0000H ;Reset

LJMP MAIN


T0ISR: CPL P1.0

RETI

ORG 0030H

MAIN: MOV TMOD,#02H

MOV TH0,#-50

SETB TR0

MOV IE,#82HSJMP $

END


Two Square Waves Using Timer Interrupts

ORG 0000H

LJMP MAIN

ORG 000BH

LJMP T0ISR

ORG 001BH

LJMP T1ISRORG 0030H

MAIN: MOV TMOD,#12H

MOV IE,#8AH

MOV TH0,#-71

SETB TR0

MOV TH1,#HIGH(-1000)

MOV TL1,#LOW(-1000)

SETB TR1

SJMP $

Write a program using interrupts to create 7 kHz and 500 Hz square

waves on P1.7 and P1.6

T0ISR: CPL P1.7

RETI

T1ISR: CPL P1.6

CLR TR1


MOV TL1,#LOW(-1000)SETB TR1

RETI

END



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Two Square Waves Using Timer Interrupts

ORG 0000H

LJMP MAIN

ORG 000BH

LJMP T0ISR

ORG 001BH

LJMP T1ISR

ORG 0030H

MAIN: MOV TMOD,#12H

MOV IE,#8AH

MOV TH0,#-71

SETB TR0

SJMP $

Write a program using interrupts to create 7 kHz and 500 Hz square

waves on P1.7 and P1.6

T0ISR: CPL P1.7

RETI

T1ISR: CPL P1.6

CLR TR1


MOV TL1,#LOW(-1000)

SETB TR1

RETI

END

SETB TF1


Character Output Using Interrupts

ORG 0000H

LJMP MAIN

ORG 0023H

LJMP SPISRORG 0030H

MAIN: MOV TMOD,#20H

MOV TH1,#-26

SETB TR1

MOV SCON,#42H

MOV A,#20H

MOV IE,#90H

SJMP $

Write a program using interrupts to continually transmit the ASCII code set

(excluding control codes) to a terminal attached to the 8051s serial port (1200

baud, 12 MHz crystal). The ASCII codes consist of 95 graphic codes (20H to 7EH) and

33 control codes (00H to 1FH, and 7FH).

SPISR: CJNE A,#7FH,SKIP

MOV A,#20H

SKIP: MOV SBUF,A

INC ACLR TI

RETI

END



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Furnace ControllerUsing interrupts, design an 8051 furnace controller that keeps a building at 20oC

1oC.

Temperature sensors are connected to /INT0 and /INT1 and provide /HOT and /COLD

signals. The furnace ON/OFF solenoid is connected to P1.7.

/HOT = 0 if T > 21oC

/COLD = 0 if T < 19oC

P1.7 = 1 : Furnace ON

P1.7 = 0 : Furnace OFF

P3.2

P3.3


Furnace Controller

ORG 0000H

LJMP MAIN

ORG 0003H

E0ISR: CLR P1.7 ;turn furnace off

RETI

ORG 0013H

E1ISR: SETB P1.7 ;turn furnace onRETI

ORG 0030H

MAIN: MOV IE,#85H ;enable external 0 & 1 interrupts

SETB IT0 ;negative edge triggered for external 0

SETB IT1 ;negative edge triggered for external 1

SETB P1.7 ;turn furnace on

JB P3.2,SKIP ;if T > 21 degrees,

CLR P1.7 ; turn furnace off

SKIP: SJMP $ ;do nothing

END

Using interrupts, design an 8051 furnace controller that keeps a building at 20oC

1oC.



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Intrusion Warning System (1)Design an intrusion warning system using interrupts that sounds a 400 Hz tone using

loudspeaker connected to P1.7 whenever a door sensor connected /INT0 makes a

high-to-low transition.

P3.2


Intrusion Warning System (1)Design an intrusion warning system using interrupts that sounds a 400 Hz tone using

loudspeaker connected to P1.7 whenever a door sensor connected /INT0 makes a

high-to-low transition.

ORG 0000H

LJMP MAIN

ORG 0003H

LJMP E0ISR

ORG 001BH

LJMP T1ISR

ORG 0030H

MAIN: SETB IT0

MOV TMOD,#10H

MOV IE,#81H

SJMP $

E0ISR: SETB TF1

SETB ET1

RETI

T1ISR: CLR TR1


MOV TL1,#LOW(-1250)

CPL P1.7

SETB TR1

RETI

END



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Intrusion Warning System (2)

P3.2

50 ms

Design an intrusion warning system using interrupts that sounds a 400 Hz tone for

50 ms (using loudspeaker connected to P1.7) whenever a door sensor connected

/INT0 makes a high-to-low transition.


Intrusion Warning System (2)Design an intrusion warning system using interrupts that sounds a 400 Hz tone for

50 ms (using loudspeaker connected to P1.7) whenever a door sensor connected


ORG 0000H

LJMP MAIN

ORG 0003H

LJMP E0ISR

ORG 000BH

LJMP T0ISR

ORG 001BH

LJMP T1ISR

ORG 0030H

MAIN: SETB IT0

MOV TMOD,#11H

MOV IE,#81H

SJMP $

E0ISR: MOV TH0,#HIGH(-50000)

MOV TL0,#LOW(-50000)

SETB TR0

SETB TF1

SETB ET0

SETB ET1

RETI

T0ISR: CLR TR0

CLR ET0

CLR ET1

RETI

T1ISR: CLR TR1


MOV TL1,#LOW(-1250)

CPL P1.7

SETB TR1

RETI

END



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Intrusion Warning System (3)Design an intrusion warning system using interrupts that sounds a 400 Hz tone for

1 second (using loudspeaker connected to P1.7) whenever a door sensor connected


P3.2


Intrusion Warning System (3)

ORG 0000H

LJMP MAIN

ORG 0003H

LJMP E0ISR

ORG 000BH

LJMP T0ISR

ORG 001BH

LJMP T1ISR

ORG 0030H

MAIN: SETB IT0

MOV TMOD,#11H

MOV IE,#81H

SJMP $

E0ISR: MOV R7,#20

SETB TF0

SETB TF1

SETB ET0

SETB ET1

RETI

T0ISR: CLR TR0

DJNZ R7,SKIP

CLR ET0

CLR ET1

LJMP EXIT

SKIP: MOV TH0,#HIGH(-50000)

MOV TL0,#LOW(-50000)

SETB TR0

EXIT: RETI

T1ISR: CLR TR1


MOV TL1,#LOW(-1250)

CPL P1.7

SETB TR1

RETI

END

Design an intrusion warning system using interrupts that sounds a 400 Hz tone for

1 second (using loudspeaker connected to P1.7) whenever a door sensor connected




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References

L Ch Thng

I. Scott Mackenzie, The 8051 Microcontroller

Cc ti liu trn Internet khng trch dn hoc khng ghi tcgi

8051 chap6 interrupts

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