8-1 introduction chapter #8: finite state machine design

8-1

Introduction

Chapter #8: Finite State Machine Design

8-2

IntroductionMotivation

• Counters: Sequential Circuits where State = Output

• Generalizes to Finite State Machines: Outputs are Function of State (and Inputs) Next States are Functions of State and Inputs Used to implement circuits that control other circuits "Decision Making" logic

• Application of Sequential Logic Design Techniques Word Problems Mapping into formal representations of FSM behavior Case Studies

8-3

IntroductionChapter Overview

Concept of the State Machine

• Partitioning into Datapath and Control

• When Inputs are Sampled and Outputs Asserted

Basic Design Approach

• Six Step Design Process

Alternative State Machine Representations

• State Diagram, ASM Notation, VHDL, ABEL Description Language

Moore and Mealy Machines

• Definitions, Implementation Examples

Word Problems

• Case Studies

8-4

IntroductionConcept of the State Machine

Computer Hardware = Datapath + Control

RegistersCombinational Functional Units (e.g., ALU)Busses

FSM generating sequences of control signalsInstructs datapath what to do next

"Puppet"

"Puppeteer who pulls thestrings"

Qualifiers

Control

Control

Datapath

State

ControlSignalOutputs

QualifiersandInputs

8-5

IntroductionConcept of the State MachineExample: Odd Parity Checker

Even [0]

Odd [1]

Reset

0

0

1 1

Assert output whenever input bit stream has odd # of 1's

StateDiagram

Present State Even Even Odd Odd

Input 0 1 0 1

Next State Even Odd Odd Even

Output 0 0 1 1

Symbolic State Transition Table

Output 0 0 1 1

Next State 0 1 1 0

Input 0 1 0 1

Present State 0 0 1 1

Encoded State Transition Table

8-6

IntroductionConcept of the State MachineExample: Odd Parity Checker

Next State/Output Functions

NS = PS xor PI; OUT = PS

Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0

Clk

Output

Input 1 0 0 1 1 0 1 0 1 1 1 0

1 1 0 1 0 0 1 1 0 1 1 1

D

R

Q

Q

Input

CLK PS/Output

\Reset

NS

D FF Implementation

T

R

Q

Q

Input

CLK

Output

\Reset

T FF Implementation

8-7

IntroductionConcept of State MachineTiming: When are inputs sampled, next state computed, outputs asserted?

State Time: Time between clocking events

• Clocking event causes state/outputs to transition, based on inputs

• For set-up/hold time considerations:

Inputs should be stable before clocking event

• After propagation delay, Next State entered, Outputs are stable

NOTE: Asynchronous signals take effect immediately Synchronous signals take effect at the next clocking event

E.g., tri-state enable: effective immediately sync. counter clear: effective at next clock event

8-8

IntroductionConcept of State MachineExample: Positive Edge Triggered Synchronous System

On rising edge, inputs sampled outputs, next state computed

After propagation delay, outputs and next state are stable

Immediate Outputs: affect datapath immediately could cause inputs from datapath to change

Delayed Outputs: take effect on next clock edge propagation delays must exceed hold timesOutputs

State T ime

Clock

Inputs

8-9

IntroductionConcept of the State MachineCommunicating State Machines

Machines advance in lock step

Initial inputs/outputs: X = 0, Y = 0

One machine's output is another machine's input

CLK

FSM 1 X FSM 2

Y

A A B

C D D

FSM 1 FSM 2

X

Y

A [1]

B [0]

Y=0

Y=1

Y=0,1

Y=0

C [0]

D [1]

X=0

X=1

X=0

X=0

X=1

8-10

IntroductionBasic Design Approach

Six Step Process

1. Understand the statement of the Specification

2. Obtain an abstract specification of the FSM

3. Perform a state mininimization

4. Perform state assignment

5. Choose FF types to implement FSM state register

6. Implement the FSM

1, 2 covered now; 3, 4, 5 covered later;4, 5 generalized from the counter design procedure

8-11

IntroductionBasic Design Approach

Example: Vending Machine FSM

General Machine Concept:deliver package of gum after 15 cents deposited

single coin slot for dimes, nickels

no change

Block Diagram

Step 1. Understand the problem:

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

SensorGum

Release Mechanism

Draw a picture!

8-12

IntroductionVending Machine Example

Tabulate typical input sequences:three nickelsnickel, dimedime, nickeltwo dimestwo nickels, dime

Draw state diagram:

Inputs: N, D, reset

Output: open

Step 2. Map into more suitable abstract representation

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

8-13

IntroductionVending Machine ExampleStep 3: State Minimization

Reset

N

N

N, D

[open]

15¢

0¢

5¢

10¢

D

D

reuse stateswheneverpossible Symbolic State Table

Present State

0¢

5¢

10¢

15¢

D

0 0 1 1 0 0 1 1 0 0 1 1 X

N

0 1 0 1 0 1 0 1 0 1 0 1 X

Inputs Next State

0¢ 5¢ 10¢ X 5¢ 10¢ 15¢ X

10¢ 15¢ 15¢ X

15¢

Output Open

0 0 0 X 0 0 0 X 0 0 0 X 1

8-14

IntroductionVending Machine ExampleStep 4: State Encoding

Next State D 1 D 0

0 0 0 1 1 0 X X 0 1 1 0 1 1 X X 1 0 1 1 1 1 X X 1 1 1 1 1 1 X X

Present State Q 1 Q 0

0 0

0 1

1 0

1 1

D

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

N

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Inputs Output Open

0 0 0 X 0 0 0 X 0 0 0 X 1 1 1 X

8-15

IntroductionParity Checker Example

Step 5. Choose FFs for implementation

D FF easiest to use

D1 = Q1 + D + Q0 N

D0 = N Q0 + Q0 N + Q1 N + Q1 D

OPEN = Q1 Q0

8 GatesCLK

OPEN

CLK

Q 0

D

R

Q

Q

D

R

Q

Q

\ Q 1

\reset

\reset

\ Q 0

\ Q 0

Q 0

Q 0

Q 1

Q 1

Q 1

Q 1

D

D

N

N

N

\ N

D 1

D 0

D

Q0Q1

N00 01 11 10

0001

11

10

00 1 1

11 1

11 11

0

X X X X

Q0

N

K-map for D1

Q1

D

D

Q0Q1

N00 01 11 10

0001

11

10

10 1 0

10 1

0 1

1

X X X X

Q0

N

K-map for D0

1 1

Q1

D

D

Q0Q1

N00 01 11 10

0001

11

10

00 1 0

10 0

00 01

0

X X X X

Q0

N

K-map for Open

Q1

D

8-16

IntroductionParity Checker Example

Step 5. Choosing FF for Implementation

J-K FF

Remapped encoded state transition table

Next State D 1 D 0

0 0 0 1 1 0 X X 0 1 1 0 1 1 X X 1 0 1 1 1 1 X X 1 1 1 1 1 1 X X

Present State Q 1 Q 0

0 0

0 1

1 0

1 1

D

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

N

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Inputs K 1

X X X X X X X X 0 0 0 X 0 0 0 X

K 0

X X X X 0 1 0 X X X X X 0 0 0 X

J 1

0 0 1 X 0 1 1 X X X X X X X X X

J 0

0 1 0 X X X X X 0 1 1 X X X X X

8-17

IntroductionVending Machine ExampleImplementation:

J1 = D + Q0 N

K1 = 0

J0 = Q0 N + Q1 D

K0 = Q1 N

7 Gates

OPEN Q 1

\ Q 0

N

Q 0 J

K R

Q

Q

J

K R

Q

Q

Q 0

\ Q 1

\ Q 1

\ Q 0

Q 1

\reset

D

D

N

N

CLK

CLK

D

Q0Q1

N00 01 11 10

0001

11

10

00 1 1

11 1

11 11

0

X X X X

Q0

N

K-map for D1

Q1

D

D

Q0Q1

N00 01 11 10

0001

11

10

00 1 1

11 1

11 11

0

X X X X

Q0

N

K-map for D1

Q1

D

D

Q0Q1

N00 01 11 10

0001

11

10

00 1 1

11 1

11 11

0

X X X X

Q0

N

K-map for D1

Q1

D

D

Q0Q1

N00 01 11 10

0001

11

10

00 1 1

11 1

11 11

0

X X X X

Q0

N

K-map for D1

Q1

D

8-18

IntroductionAlternative State Machine Representations

Why State Diagrams Are Not Enough

Not flexible enough for describing very complex finite state machines

Not suitable for gradual refinement of finite state machine

Do not obviously describe an algorithm: that is, well specified sequence of actions based on input data

algorithm = sequencing + data manipulation separation of control and data

Gradual shift towards program-like representations:

• Algorithmic State Machine (ASM) Notation

• Hardware Description Languages (e.g., VHDL)

8-19


Algorithmic State Machine (ASM) Notation

Three Primitive Elements:

• State Box

• Decision Box

• Output Box

State Machine in one state block per state time

Single Entry Point

Unambiguous Exit Path for each combination of inputs

Outputs asserted high (.H) or low (.L); Immediate (I) or delayed til next clock

State Entry Path

State Name

State Code

State Box

ASM Block

State Output List

Condition Box

Conditional Output List

Output Box

Exits to other ASM Blocks

Condition

* ***

T F

8-20


ASM Notation

Condition Boxes:Ordering has no effect on final outcome

Equivalent ASM charts: A exits to B on (I0=1 & I1=1) else exit to C

A 010

I0

I1

T

T

F

F

B C

A 010

I0

T

T

F

F

B C

I1

8-21


Example: Parity Checker

Nothing in output list implies Z not asserted

Z asserted in State Odd

Input X, Output Z

InputFTFT

PresentStateEvenEvenOddOdd

NextStateEvenOddOddEven

OutputNot ANot A

AA

Symbolic State Table:

Input0101

PresentState

0011

NextState

0110

Output0011

Encoded State Table:

Trace paths to derivestate transition tables

Trace paths to derivestate transition tables

Even

Odd

H. Z

X

X

0

1

F

T

T F

8-22


ASM Chart for Vending Machine

0¢

15¢

H.Open

D

Reset

00

1 1

T

T

F

N F

T

F

10¢

D

10

T

N F

T

F

5¢

D

01

T N

F T

F

0¢

8-23

IntroductionAlternative State Machine RepresentationsHardware Description Languages: VHDL

ENTITY parity_checker IS PORT ( x, clk: IN BIT; z: OUT BIT);END parity_checker;

ARCHITECTURE behavioral OF parity_checker IS BEGIN main: BLOCK (clk = ‘1’ and not clk’STABLE)

TYPE state IS (Even, Odd); SIGNAL state_register: state := Even;

BEGIN state_even: BLOCK ((state_register = Even) AND GUARD) BEGIN state_register <= Odd WHEN x = ‘1’ ELSE Even END BLOCK state_even;

BEGIN state_odd: BLOCK ((state_register = Odd) AND GUARD) BEGIN state_register <= Even WHEN x = ‘1’ ELSE Odd; END BLOCK state_odd;

z <= ‘0’ WHEN state_register = Even ELSE ‘1’ WHEN state_register = Odd; END BLOCK main;END behavioral;

Interface Description

Architectural Body

Guard Expressionthat evaluates to truewhenever the clock signalhas recently undergone0 to 1 transition

Determine New State

Determine Outputs

8-24

IntroductionAlternative State Machine RepresentationsABEL Hardware Description Language

module paritytitle 'odd parity checker state machine'u1 device 'p22v10';

"Input Pins clk, X, RESET pin 1, 2, 3;

"Output Pins Q, Z pin 21, 22;

Q, Z istype 'pos,reg';

"State registersSREG = [Q, Z];S0 = [0, 0]; " even number of 0'sS1 = [1, 1]; " odd number of 0's

equations [Q.ar, Z.ar] = RESET; "Reset to state S0

state_diagram SREGstate S0: if X then S1 else S0;state S1: if X then S0 else S1;

test_vectors ([clk, RESET, X] -> [SREG]) [0,1,.X.] -> [S0]; [.C.,0,1] -> [S1]; [.C.,0,1] -> [S0]; [.C.,0,1] -> [S1]; [.C.,0,0] -> [S1]; [.C.,0,1] -> [S0]; [.C.,0,1] -> [S1]; [.C.,0,0] -> [S1]; [.C.,0,0] -> [S1]; [.C.,0,0] -> [S1];end parity;

8-25

IntroductionMoore and Mealy Machine Design ProcedureDefinitions

Moore Machine

Outputs are functionsolely of the current

state

Outputs change synchronously with

state changes

Mealy Machine

Outputs depend onstate AND inputs

Input change causesan immediate output

change

Asynchronous signals

State Register Clock

State Feedback

Combinational Logic for

Outputs and Next State

X Inputs

i Z Outputs

k

Clock

state feedback


Next State (Flip-flop Inputs)

State Register

Comb. Logic for Outputs

Z Outputs

k

X Inputs

i

8-26

IntroductionMoore and Mealy MachinesState Diagram Equivalents

Outputs are associated with State

Outputs are associated with Transitions

Reset/0

N/0

N/0

N+D/1

15¢

0¢

5¢

10¢

D/0

D/1

(N D + Reset)/0

Reset/0

Reset/1

N D/0

N D/0

MooreMachine

Reset

N

N

N+D

[1]

15¢

0¢

5¢

10¢

D

[0]

[0]

[0]

D

N D + Reset

Reset

Reset

N D

N D

MealyMachine

8-27

IntroductionMoore and Mealy MachinesStates vs. Transitions

Mealy Machine typically has fewer states than Moore Machine for same output sequence

EquivalentASM Charts

Same I/O behavior

Different # of states

1

1

0

1

2

0

0

[0]

[0]

[1]

1/0

0

1

0/0

0/0

1/1

1

0

S0

S1

IN

IN

S2

IN

10

01

00

T

H.OUT

T

T

F

F

F

S0

S1

IN

IN

1

0

F

F

T

T

H.OUT

8-28

IntroductionMoore and Mealy MachinesTiming Behavior of Moore Machines

Reverse engineer the following:

Two Techniques for Reverse Engineering:

• Ad Hoc: Try input combinations to derive transition table

• Formal: Derive transition by analyzing the circuit

Input XOutput ZState A, B = Z

JCK R

Q

Q

FFa

JCK R

Q

Q

FFb

X

X

X

X

\Reset

\Reset

A

Z

\A

\A\B

\B

Clk

8-29

IntroductionMoore and Mealy MachinesAd Hoc Reverse Engineering

Behavior in response to input sequence 1 0 1 0 1 0:

Partially DerivedState Transition

Table

A 0

0

1

1

B 0 1 0 1

X 0 1 0 1 01 0 1

A+ ? 1 0 ? 1 0 1 1

B+ ? 1 0 ? 0 1 1 0

Z 0 0 1 1 0 0 1 1

X = 1 AB = 00

X = 0 AB = 1 1

X = 1 AB = 1 1

X = 0 AB = 10

X = 1 AB = 10

X = 0 AB = 01

X = 0 AB = 00

Reset AB = 00

100

X

Clk

A

Z

\Reset

8-30

IntroductionMoore and Mealy MachinesFormal Reverse Engineering

Derive transition table from next state and output combinational functions presented to the flipflops!

Ja = XJb = X

Ka = X • BKb = X xor A

Z = B

FF excitation equations for J-K flipflop:

A+ = Ja • A + Ka • A = X • A + (X + B) • AB+ = Jb • B + Kb • B = X • B + (X • A + X • A) • B

Next State K-Maps:

State 00, Input 0 -> State 00State 01, Input 1 -> State 01

A+

B+

AB00 01 11 10

0

1

0 0 1 1

1 1 1 0

AB00 01 11 10

0

1

0 0 1 0

1 1 O 1

X

X

8-31

IntroductionMoore and Mealy MachinesComplete ASM Chart for the Mystery Moore Machine

Note: All Outputs Associated With State BoxesNo Separate Output Boxes , Intrinsic in Moore Machines

S 0 00

X

H. Z

S 1 01

X

S 3 1 1

S 2 10

H. Z

X

X

0 1

1 0

0

1

0 1

8-32

IntroductionMoore and Mealy MachinesReverse Engineering a Mealy Machine

Input X, Output Z, State A, B

State register consists of D FF and J-K FF

D

C R

Q

Q

J C K R

Q

Q

X

X

X

Clk

A

A

A

B

B

B

Z

\Reset \Reset

\ A

\ A

\ X

\ X

\ X \ B

DA

DA

8-33

IntroductionMoore and Mealy MachineAd Hoc Method

Signal Trace of Input Sequence 101011:

Note glitchesin Z!

Outputs valid atfollowing falling

clock edge

Partially completedstate transition tablebased on the signal

trace

A 0

0

1

1

B 0 1 0 1

X 0 1 0 1 0 1 0 1

A+ 0 0 ? 1 ? 0 1 ?

B+ 1 0 ? 1 ? 1 0 ?

Z 0 0 ? 0 ? 1 1 ?

Reset AB =00

Z =0

X =1 AB =00

Z =0

X =0 AB =00

Z =0

X =1 AB =01

Z =0

X =1 AB =10

Z =1

X =0 AB =1 1

Z =1

X =1 AB =01

Z =0

X

Clk

A

B

Z

\Reset

100

8-34

IntroductionMoore and Mealy MachinesFormal Method

A+ = B • (A + X) = A • B + B • X

B+ = Jb • B + Kb • B = (A xor X) • B + X • B

= A • B • X + A • B • X + B • X

Z = A • X + B • XMissing Transitions and Outputs:

State 01, Input 0 -> State 01, Output 1State 10, Input 0 -> State 00, Output 0State 11, Input 1 -> State 11, Output 1

00 01 11 10

0

1

0 0 1 0

0 1 1 0

AB00 01 11 10

0

1

1 0 0 0

0 1 1 1

AB00 01 11 10

0

1

0 1 1 0

0 0 1 1

ABX

X

X

A+

A+

Z

8-35

IntroductionMoore and Mealy MachinesASM Chart for Mystery Mealy Machine

S0 = 00, S1 = 01, S2 = 10, S3 = 11

NOTE: Some Outputs in Output Boxes as well as State BoxesThis is intrinsic in Mealy Machine implementation

S 0 00

X

H. Z S 1 01

S 2 10

X

H. Z

H. Z

S 3 1 1

X X

0

1

0

0 1

1

0 1

8-36

IntroductionMoore and Mealy Machines

States, Transitions, and Outputs in Mealy and Moore Machines

M inputs and N outputs with L flip-flops- 1 to 2L valid states

max and min state transitions that can an begin in a given state if we include exit transition- both 2M states

max or min state transitions that can end in a given state- min : 0 (start up states reachable only on reset)- max : 2L x 2M states (# of possible input comb. multiplied by # of states)

min and max # of patterns that can be observed on the machine’s outputs- min : L (every state and every transition can be associated with the

same pattern)- max depends on the kinds of machine

Mealy : smaller of (2M x 2L, 2N)Moore : smaller of (2L, 2N)

8-37

IntroductionMoore and Mealy MachinesSynchronous Mealy Machine

latched state AND outputs

avoids glitchy outputs! (less hardware)

Use output flip-flops

State Register Clock

Clock


Outputs and Next State

state feedback

X Inputs

i Z Outputs

k

8-38

IntroductionFinite State Machine Word ProblemsMapping English Language Description to Formal Specifications

Four Case Studies:

• Finite String Pattern Recognizer

• Complex Counter with Decision Making

• Traffic Light Controller

• Digital Combination Lock

We will use state diagrams and ASM Charts

8-39

IntroductionFinite State Machine Word ProblemsFinite String Pattern Recognizer

A finite string recognizer has one input (X) and one output (Z).The output is asserted whenever the input sequence …010…has been observed, as long as the sequence 100 has never beenseen.

Step 1. Understanding the problem statement

Sample input/output behavior:

X: 00101010010…Z: 00010101000…

X: 11011010010…Z: 00000001000…

8-40

IntroductionFinite State Machine Word Problems

Finite String Recognizer

Step 2. Draw State Diagrams/ASM Charts for the strings that must be recognized. I.e., 010 and 100.

Moore State DiagramReset signal places FSM in S0

Outputs 1

Loops in State

S0 [0]

S1 [0]

S2 [0]

S3 [1]

S4 [0]

S5 [0]

S6 [0]

Reset

0

0

00

0,1

1

1

8-41

IntroductionFinite State Machine Word ProblemsFinite String Recognizer

Exit conditions from state S3: have recognized …010 if next input is 0 then have …0100! if next input is 1 then have …0101 = …01 (state S2)

S0 [0]

S1 [0]

S2 [0]

S3 [1]

S4 [0]

S5 [0]

S6 [0]

Reset

0

0

0

0,10

...010

0

...01

1

...100

1

1

8-42


Exit conditions from S1: recognizes strings of form …0 (no 1 seen) loop back to S1 if input is 0

Exit conditions from S4: recognizes strings of form …1 (no 0 seen) loop back to S4 if input is 1

S0 [0]

S1 [0]

S2 [0]

S3 [1]

S4 [0]

S5 [0]

S6 [0]

Reset

0

0

0...0

0

0

...01

1

1

1

1

...100

0

...010

0,1

8-43


S2, S5 with incomplete transitions

S2 = …01; If next input is 1, then string could be prefix of (01)1(00) S4 handles just this case!

S5 = …10; If next input is 1, then string could be prefix of (10)1(0) S2 handles just this case!

Final State Diagram

S0 [0]

S1 [0]

S2 [0]

S3 [1]

S4 [0]

S5 [0]

S6 [0]

Reset

0 1

0

0...0

0

0,1

1

1...11

1

...10

...100

1

0

0

...01

...010

8-44


module stringtitle '010/100 string recognizer state machine Josephine Engineer, Itty Bity Machines, Inc.'u1 device 'p22v10';

"Input Pins clk, X, RESET pin 1, 2, 3;

"Output Pins Q0, Q1, Q2, Z pin 19, 20, 21, 22;

Q0, Q1, Q2, Z istype 'pos,reg';

"State registersSREG = [Q0, Q1, Q2, Z];S0 = [0,0,0,0]; " Reset stateS1 = [0,0,1,0]; " strings of the form ...0S2 = [0,1,0,0]; " strings of the form ...01S3 = [0,1,1,1]; " strings of the form ...010S4 = [1,0,0,0]; " strings of the form ...1S5 = [1,0,1,0]; " strings of the form ...10S6 = [1,1,0,0]; " strings of the form ...100

equations [Q0.ar, Q1.ar, Q2.ar, Z.ar] = RESET; "Reset to S0

state_diagram SREGstate S0: if X then S4 else S1;state S1: if X then S2 else S1;state S2: if X then S4 else S3;state S3: if X then S2 else S6;state S4: if X then S4 else S5;state S5: if X then S2 else S6;state S6: goto S6; test_vectors ([clk, RESET, X]->[Z]) [0,1,.X.] -> [0]; [.C.,0,0] -> [0]; [.C.,0,0] -> [0]; [.C.,0,1] -> [0]; [.C.,0,0] -> [1]; [.C.,0,1] -> [0]; [.C.,0,0] -> [1]; [.C.,0,1] -> [0]; [.C.,0,0] -> [1]; [.C.,0,0] -> [0]; [.C.,0,1] -> [0]; [.C.,0,0] -> [0];end string;

ABEL Description

8-45


Review of Process:

• Write down sample inputs and outputs to understand specification

• Write down sequences of states and transitions for the sequences to be recognized

• Add missing transitions; reuse states as much as possible

• Verify I/O behavior of your state diagram to insure it functions like the specification

8-46

IntroductionFinite State Machine Word ProblemsComplex Counter

A sync. 3 bit counter has a mode control M. When M = 0, the countercounts up in the binary sequence. When M = 1, the counter advancesthrough the Gray code sequence.

Binary: 000, 001, 010, 011, 100, 101, 110, 111Gray: 000, 001, 011, 010, 110, 111, 101, 100

Valid I/O behavior:

Mode Input M0011100

Current State000001010110111101110

Next State (Z2 Z1 Z0)001010110111101110111

8-47


One state for each output combinationAdd appropriate arcs for the mode control

S 0 000

S 1 001 H. Z 0

M

S 3 01 1 H. Z 1 H. Z 0

H. Z 1

S 2 010

M M

S 6 1 10 H. Z 2 H. Z 1

H. Z 2 H. Z 1 H. Z 0

S 4 100

M

H. Z 2

H. Z 2 H. Z 0

M

S 5 101

M

S 7 1 1 1

0 1

0 1

0

1

0

1 0

1

0 1

ResetS0

[000]

S1 [001]

S2 [010]

S3 [011]

S4 [100]

S5 [101]

S6 [110]

S7 [111]

01

1 0

0

0

0

0

0

0

1

1

1

1

1

1

8-48


module countertitle 'combination binary/gray code upcounter Josephine Engineer, Itty Bity Machines, Inc.'u1 device 'p22v10';

"Input Pins clk, M, RESET pin 1, 2, 3;

"Output Pins Z0, Z1, Z2 pin 19, 20, 21;

Z0, Z1, Z2 istype 'pos,reg';

"State registersSREG = [Z0, Z1, Z2];S0 = [0,0,0];S1 = [0,0,1];S2 = [0,1,0];S3 = [0,1,1];S4 = [1,0,0];S5 = [1,0,1];S6 = [1,1,0];S7 = [1,1,1];

equations [Z0.ar, Z1.ar, Z2.ar] = RESET; "Reset to state S0

state_diagram SREGstate S0: goto S1;state S1: if M then S3 else S2;state S2: if M then S6 else S3;state S3: if M then S2 else S4;state S4: if M then S0 else S5;state S5: if M then S4 else S6;state S6: goto S7;state S7: if M then S5 else S0; test_vectors ([clk, RESET, M] -> [Z0, Z1, Z2]) [0,1,.X.] -> [0,0,0]; [.C.,0,0] -> [0,0,1]; [.C.,0,0] -> [0,1,0]; [.C.,0,1] -> [1,1,0]; [.C.,0,1] -> [1,1,1]; [.C.,0,1] -> [1,0,1]; [.C.,0,0] -> [1,1,0]; [.C.,0,0] -> [1,1,1];end counter;

ABEL Description

8-49

IntroductionFinite State Machine Word ProblemsTraffic Light Controller

A busy highway is intersected by a little used farmroad. DetectorsC sense the presence of cars waiting on the farmroad. With no caron farmroad, light remain green in highway direction. If vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing the farmroad lights to become green. These stay green only as long as a farmroad car is detected but never longer than a set interval. When these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to green. Even if farmroad vehicles are waiting, highway gets at least a set interval as green.

Assume you have an interval timer that generates a short time pulse(TS) and a long time pulse (TL) in response to a set (ST) signal. TSis to be used for timing yellow lights and TL for green lights.

8-50


Picture of Highway/Farmroad Intersection:

Highway

Highway

Farmroad

Farmroad

HL

HL

FL

FL

C

C

8-51


• Tabulation of Inputs and Outputs:

Input SignalresetCTSTL

Output SignalHG, HY, HRFG, FY, FRST

Descriptionplace FSM in initial statedetect vehicle on farmroadshort time interval expiredlong time interval expired

Descriptionassert green/yellow/red highway lightsassert green/yellow/red farmroad lightsstart timing a short or long interval

• Tabulation of Unique States: Some light configuration imply others

StateS0S1S2S3

DescriptionHighway green (farmroad red)Highway yellow (farmroad red)Farmroad green (highway red)Farmroad yellow (highway red)

8-52


Refinement of ASM Chart:

Start with basic sequencing and outputs:

S 0 S 3

S 1 S 2

H.HG H.FR

H.HR H.FY

H.HR H.FG

H.HY H.FR

8-53


Determine Exit Conditions for S0: Car waiting and Long Time Interval Expired- C • TL

Equivalent ASM Chart Fragments

S 0 S 0

H.HG H.FR

H.HG H.FR

TL TL • C

H.ST C

H.ST S 1

H.HY H.FR

S 1

H.HY H.FR

0

0

1

1

0

1

8-54


S1 to S2 Transition: Set ST on exit from S0 Stay in S1 until TS asserted Similar situation for S3 to S4 transition

S 1

H.HY H.FR

TS

H.ST

S 2

H.HR H.FG

0 1

8-55


S2 Exit Condition: no car waiting OR long time interval expired

Complete ASM Chart for Traffic Light Controller

S 0 S 3

H.HG H.FR H.ST

H.HR H.FY

TS TL • C

H.ST H.ST

S 1 S 2

H.HY H.FR

H.ST H.HR H.FG

TS TL + C

0 0 1

1

1 0

1

0

8-56


Compare with state diagram:

Advantages of State Charts:

• Concentrates on paths and conditions for exiting a state

• Exit conditions built up incrementally, later combined into single Boolean condition for exit

• Easier to understand the design as an algorithm

S0: HG

S1: HY

S2: FG

S3: FY

Reset

TL + C

S0TL•C/ST

TS

S1 S3

S2

TS/ST

TS/ST

TL + C/ST

TS

TL • C

8-57


module traffictitle 'traffic light FSM'u1 device 'p22v10';

"Input Pins clk, C, RESET, TS, TL pin 1, 2, 3, 4, 5;

"Output Pins Q0, Q1, HG, HY, HR, FG, FY, FR, ST pin 14, 15, 16, 17, 18, 19, 20, 21, 22;

Q0, Q1 istype 'pos,reg'; ST, HG, HY, HR, FG, FY, FR istype 'pos,com'; "State registersSREG = [Q0, Q1];S0 = [ 0, 0];S1 = [ 0, 1];S2 = [ 1, 0];S3 = [ 1, 1];

equations [Q0.ar, Q1.ar] = RESET; HG = !Q0 & !Q1;

HY = !Q0 & Q1; HR = (Q0 & !Q1) # (Q0 & Q1); FG = Q0 & !Q1; FY = Q0 & Q1; FR = (!Q0 & !Q1) # (!Q0 & Q1); state_diagram SREGstate S0: if (TL & C) then S1 with ST = 1 else S0 with ST = 0state S1: if TS then S2 with ST = 1 else S1 with ST = 0state S2: if (TL # !C) then S3 with ST = 1 else S2 with ST = 0state S3: if TS then S0 with ST = 1 else S3 with ST = 0 test_vectors ([clk,RESET, C, TS, TL]->[SREG,HG,HY,HR,FG,FY,FR,ST]) [.X., 1,.X.,.X.,.X.]->[ S0, 1, 0, 0, 0, 0, 1, 0]; [.C., 0, 0, 0, 0]->[ S0, 1, 0, 0, 0, 0, 1, 0]; [.C., 0, 1, 0, 1]->[ S1, 0, 1, 0, 0, 0, 1, 0]; [.C., 0, 1, 0, 0]->[ S1, 0, 1, 0, 0, 0, 1, 0]; [.C., 0, 1, 1, 0]->[ S2, 0, 0, 1, 1, 0, 0, 0]; [.C., 0, 1, 0, 0]->[ S2, 0, 0, 1, 1, 0, 0, 0]; [.C., 0, 1, 0, 1]->[ S3, 0, 0, 1, 0, 1, 0, 0]; [.C., 0, 1, 1, 0]->[ S0, 1, 0, 0, 0, 0, 1, 0];end traffic;

ABEL Description

8-58

IntroductionFinite State Machine Word ProblemsDigital Combination Lock

"3 bit serial lock controls entry to locked room. Inputs are RESET,ENTER, 2 position switch for bit of key data. Locks generates anUNLOCK signal when key matches internal combination. ERRORlight illuminated if key does not match combination. Sequence is:(1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) &(3) two more times."

Problem specification is incomplete:

• how do you set the internal combination?

• exactly when is the ERROR light asserted?

Make reasonable assumptions:

• hardwired into next state logic vs. stored in internal register

• assert as soon as error is detected vs. wait until full combination has been entered

Our design: registered combination plus error after full combination

8-59


Understanding the problem: draw a block diagram …

InternalCombination

Operator Data

Inputs:ResetEnterKey-InL0, L1, L2

Outputs:UnlockError

UNLOCK

ERROR

RESET

ENTER

KEY -IN

L 0

L 1

L 2

Combination Lock FSM

8-60


Enumeration of states:

what sequences lead to opening the door? error conditions on a second pass …

START state plus three key COMParison states

START entered on RESET

Exit START when ENTER is pressed

Continue on if Key-In matches L0

ST ART

Reset

Enter

COMP0

KI = L 0

N

Y

1

0

0

1

8-61


Path to unlock:

Wait for Enter Key press

Compare Key-IN

COMP0

N KI = L 0

Y IDLE0

Enter

COMP1

N

Y

KI = L 1

IDLE1

COMP2

Enter

N KI = L 2

Y DONE

H.Unlock

Reset

ST ART

1

0

0

1

0

1

8-62


Now consider error paths

Should follow a similar sequence as UNLOCK path, except asserting ERROR at the end:

COMP0 error exits to IDLE0'

COMP1 error exits to IDLE1'

COMP2 error exits to ERROR3

IDLE0'

Enter

ERROR1

IDLE1'

Enter

ERROR2

ERROR3

H.Error

Reset

ST ART

0 0 0

1 1 1

8-63


Equivalent State Diagram

Reset

Reset + Enter

Reset • Enter

Start

Comp0

KI = L0 KI ° L0

Enter

Enter

Enter

Enter

Idle0 Idle0'

Comp1 Error1

KI ° L1KI = L1Enter

Enter

EnterEnter

Idle1 Idle1'

Comp2 Error2

KI ° L2KI = L2

Done [Unlock]

Error3 [Error]

Reset

Reset Reset

Reset

StartStart

8-64

IntroductionFinite State Machine Word ProblemsCombination Lock

module locktitle 'comb. lock FSM'u1 device 'p22v10';

"Input Pinsclk, RESET, ENTER, L0, L1, L2, KI pin 1, 2, 3, 4, 5, 6, 7;

"Output PinsQ0, Q1, Q2, Q3, UNLOCK, ERROR pin 16, 17, 18, 19, 14, 15;

Q0, Q1, Q2, Q3 istype 'pos,reg';UNLOCK, ERROR istype 'pos,com'; "State registersSREG = [Q0, Q1, Q2, Q3];START = [ 0, 0, 0, 0];COMP0 = [ 0, 0, 0, 1];IDLE0 = [ 0, 0, 1, 0];COMP1 = [ 0, 0, 1, 1];IDLE1 = [ 0, 1, 0, 0];COMP2 = [ 0, 1, 0, 1];DONE = [ 0, 1, 1, 0];IDLE0p = [ 0, 1, 1, 1];ERROR1 = [ 1, 0, 0, 0];IDLE1p = [ 1, 0, 0, 1];ERROR2 = [ 1, 0, 1, 0];ERROR3 = [ 1, 0, 1, 1];

equations [Q0.ar, Q1.ar, Q2.ar, Q3.ar] = RESET; UNLOCK = !Q0 & Q1 & Q2 & !Q3;"asserted in DONE ERROR = Q0 & !Q1 & Q2 & Q3; "asserted in ERROR3 state_diagram SREGstate START: if (RESET # !ENTER) then START else COMP0; state COMP0: if (KI == L0) then IDLE0 else IDLE0p;state IDLE0: if (!ENTER) then IDLE0 else COMP1;state COMP1: if (KI == L1) then IDLE1 else IDLE1p;state IDLE1: if (!ENTER) then IDLE1 else COMP2;state COMP2: if (KI == L2) then DONE else ERROR3;state DONE: if (!RESET) then DONE else START;state IDLE0p:if (!ENTER) then IDLE0p else ERROR1;state ERROR1:goto IDLE1p;state IDLE1p:if (!ENTER) then IDLE1p else ERROR2;state ERROR2:goto ERROR3;state ERROR3:if (!RESET) then ERROR3 else START; test_vectors end lock;

8-65

IntroductionFinite State Machine Word ProblemsDesign Steps

1. Understand the problem

2. Make reasonable assumptions when specifications are not complete

3. Start by deriving the states and state transitions that lead to the goal of FSM

4. Consider the error conditions and the transitions that lead to error states

8-66

IntroductionChapter Review

Basic Timing Behavior an FSM

• when are inputs sampled, next state/outputs transition and stabilize

• Moore and Mealy (Async and Sync) machine organizations outputs = F(state) vs. outputs = F(state, inputs)

First Two Steps of the Six Step Procedure for FSM Design

• understanding the problem

• abstract representation of the FSM

Abstract Representations of an FSM

• ASM Charts, Hardware Description Languages

Word Problems

• understand I/O behavior; draw diagrams

• enumerate states for the "goal"; expand with error conditions

• reuse states whenever possible

8-1 introduction chapter #8: finite state machine design

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