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Chapter 7EEC 170Professor Wilken

Virtual Memory EEC 170 1

Virtual Memory

Kent Wilken

EEC170 Fall 2008


Virtual Addresses

Each executing program (each process) is givenits own virtual address space

A set of 232 addresses that do not directly correspond tophysical memory locations

Virtual Addresses

0

232-1


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Virtual Pages

Each virtual address space is divided intoblocks called pages

Page size is typically 4-16 Kbytes

Virtual Addresses

page


Physical Pages

The main-memory physical address space is alsodivided into same-size physical pages

The size of the physical address space is the amount ofRAM in the computer

Physical Addresses

page


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Virtual to Physical Mapping

The operating system assigns (mapsmaps) a virtualpage to a physical page

Unused virtual pages are not mapped

Virtual Addresses Physical Addresses


Address Translation

The processor uses virtual addresses to accessinstructions and data

Virtual addresses are translated by memory-systemhardware into physical addresses using table lookup

Virtual Address

Translation

Physical Address


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Address Translation

Addresses have into two parts:

Page number: mapping is assigned by OS

Page offset: not mapped


Address Translation

Doesnt address translation slow down the memoryaccess?!!

Yes!!

Then why do we want it?!!

1. Virtual memory isolates multiple processes from each other

Better reliability

Better security

2. Virtual memory allows total size of all processes (code +data) to be larger than the computers total RAM

Excess code/data is swapped from RAM to disk


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Process Isolation

Each process has its own virtual address space and own

virtual-page to physical-page translation table

OS can isolate a processs code/data from other processes

P1 Virtual Addresses Physical Addresses

P2 Virtual Addrs.


Data/Code Sharing

Or the OS can allow processes to share certaindata/code by mapping multiple virtual pages tothe same physical page

P1 Virtual Addresses Physical Addresses

P2 Virtual Addrs.


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Disk Swap Space

Virtual pages that dont fit in main memory aremapped to swap space on the disk


Page Table

A page table for each process stores the virtual page tophysical page mappings assigned by the OS

Page tables are stored in a main memory area thats onlywriteable by the OS

If a user process could write page tables, reliability and securitywould be lost

Page tables can be cached just like other data

Physical Memory

Page Tables


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Page Table Register

A special register (page table register) holds the starting

address of a processs page table

Page table register is written by OS when OS activates the process


Page Table Address

Dedicated translation adder (not shown) computes:

[page table register] + (VPN


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+

Memory Accesses

With virtual memory, a logical memory accessrequires two physical memory accesses

1. Access physical page number

PhysicalMemory

MUX

PT AddressVPN


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Mapping to Swap Space

Valid = 1: virtual page maps to main memory

Valid = 0: virtual page maps to disk,page table entry contains disk address


Page Fault

An access to a virtual page on disk is called apage fault

At a page fault the OS blocks the process fromrunning until the disk access completes

OS can activate another process while waiting for disk

Disk is slow: ~10ms access = ~107 CPU cycles

Page fault is a huge performance hit!

Want to avoid page faults if possible:

increase RAM so all processes fit in main memory


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Page Assignment

When a page fault occurs, OS must assign aphysical page to the faulting virtual page

OS maintains a list of unassigned (free) physicalpages and assigns the first page from the list

If free-page list is empty, OS must replace analready-assigned page

Which page to replace? How about least recently usedlike we did for cache?

Too complicated to maintain LRU for so many pages:

Example: 4Gbyte/4Kbytes per page = 106

pages

What if the replaced page has new data?


Page Replacement

Replacement requires two more page-table fields:

1. Hardware sets the Dirty bit when the virtual page is written

a replaced dirty page must be written to disk

2. Hardware sets the Reference bit when the page is written orread. Ref is used to approximate LRU

Valid Dirty RefPhysical page/Disk address

Page Table


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Clock Algorithm

When OS needs a replacement page, it can use theclock algorithm to scan through all page tableentries, with wrap around after last entry

If a table entry has Ref=1, Ref is set to 0 and thescan continues

This page was accessed in the not-too-distant past, dontreplace it

If Ref=0 and Valid=1, this page is replaced

Page was last accessed in the distant past: not for onecomplete clock-algorithm cycle through page tableentries


Fast Address Translation

Two physical memory accesses per logicalmemory access kills memory performance

Need to reduce time to translate virtual pagenumber to a physical page number

Can use a very small address translation cache,called a translation look-aside buffer (TLB)

A translation done by page table lookup is

cached in the TLB for later fast access


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TLB Structure

The TLB contains cached pairs of virtual pagenumbers and corresponding physical pagenumbers

TLB is very small (e.g., 32-256 entries) so that itsvery fast

VPN PPN

VPN PPN

VPN PPN

VPN PPN

VPN PPN

VPN PPN

VPN PPN

VPN PPN

TLB


TLB Organization

VPN

VPN PPN

=Hit

VPN PPN

=Hit

VPN PPN

=Hit

mux

PPN

TLB is fully associative to increase hit rate


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Physical

Page #

Page Offset+

Normal Memory Access

Address translation is now normally done bythe TLB

MUX

dataVirtualAddress

FromP

rocessor

PhysicalMemory

Virtual Page # TLB

+VPN


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Page Offset+

VPN


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Fast L1 Cache Access

If L1 cache index fits inside page offset, can

access TLB and cache in parallel1. Access physical page #, Tag and Data

Virtual address

virtual page number page offset

valid physical page #

valid tag data

data=

cache hit

index

TLB.

=

=

=

=

Cache



2. Compare cache tag and physical page number for cache hit

Virtual address

virtual page number page offset

valid physical page number

valid tag data

data=

cache hit

index

TLB.

=

=

=

=


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Maximum size for fast-access L1 cache is:

(Page size) x (cache associativity)

Most modern processors use fast-access L1caches. For example:

X86 architecture uses 4KByte pages

Intel Core processors have 32Kbyte, 8-way L1 caches

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