6/8/03 J. Lajoie - PHENIX Silicon Workshop 1

Pixel Ladder, PILOT Issues

• Physical structure of first pixel layer– FPGA-based PILOT chip readout

• Show some results from simulation model

– Kapton cable bus for parallel pixel chip readout

• Is a parallel readout structure possible?

J. Crandall, J. Hill, J. Lajoie, C. Ogilvie, G.Tuttle, S. Skutnik

6/8/03 J. Lajoie - PHENIX Silicon Workshop 2

Implementation in PHENIX

Laser + 2 pin diodes

Dig

PILOTGOL

Ana

PILOT

Flash

ADC

Pilot/control board, one per ladder• supplies voltage to readout• reads data from each readout• sends data out on fiber-optic• sets thresholds, masks etc.

start with ALICE design, modify to meet PHENIX needs

6/8/03 J. Lajoie - PHENIX Silicon Workshop 3

FPGA-based PILOT Module:Problem Statement and Goal

• Read 8 ALICE1 Pixel Chips in Parallel– Keep readout time within PHENIX specification– Minimize readout electronics

• Transmit Zero-Word Suppressed Data to Optical Chip (GOL)

• First look at design– Basic functionality only– Does it match to possible rad-hard FPGA?

6/8/03 J. Lajoie - PHENIX Silicon Workshop 4

PILOT Module Block Diagram

8 ALICE1 PIXEL CHIPS

32-bit Pixel Output @ 10MHz

8 chips in parallel

PILOT Module

GOL

16-bit PILOT Output @ 40MHz

LVL1 Strobe

. . . . .

. . . . .

. . . . . NEVR (Next Event Read) CE (Chip Enable)

6/8/03 J. Lajoie - PHENIX Silicon Workshop 5

PILOT Module Functional Operations

• READ– Read 32bit-word ALICE1 Pixel Data x 256 cycles @10 MHz– Reject zero words– Append word/cycle Address to 32-bit data word

• (0-255)– Store into FIFO

• WRITE– Append Pixel Chip Address (0-7)– Write to GOL 16-bit bus @ 40MHz

Full PHENIX functionality would require these two operations to be asynchronous!

6/8/03 J. Lajoie - PHENIX Silicon Workshop 6

Readout Timing

• ALICE1 Read Time:

• Store 32b Pixel data + 32b Address (overkill!) in FIFO

• Total Estimated Pixel-Chip Readout w/10% (word) Occupancy & Zero-word Suppression

(Note: design occupancy is <1% per channel)

t TMHz

sread pixel * * .2561

10256 25 6

t t t sMHz

sTOTAL read write 25 6256 8 4

4010% 461.

* ** .

6/8/03 J. Lajoie - PHENIX Silicon Workshop 7

FPGA Coding

• Written in VHDL for basic functionality– Read, Zero-suppress, Write to GOL

• Implement in FPGA Logic– Synthesize VHDL to FPGA architecture (Xilinx)– Implement Triple Modular Redundancy (TMR)

• TMR for state and critical logic • Check match for size, gates, timing etc. of FPGA

6/8/03 J. Lajoie - PHENIX Silicon Workshop 8

Xilinx FPGA SynthesisExceeded (BRAM capacity) of XCV600E (~23mm X 23mm, ~660k system gates)

Easily fit XCV2000E (~40mm X 40mm, ~2M system gates)

Does not currently meet ladder-physical size constraint, BUT

Use a smaller die and put FIFOs in system logic.

• Device Xilinx v2000efg680-6 (~40mm X 40mm)

• Number of Slices: 576 out of 19200 3%

• Number of Slice Flip Flops: 633 out of 38400 1%

• Number of 4 input LUTs: 1001 out of 38400 2%

• Number of bonded IOBs: 276 out of 516 53%

• Number of TBUFs: 512 out of 19200 2%

• Number of BRAMs: 32 out of 160 20%

• Number of GCLKs: 2 out of 4 50%

6/8/03 J. Lajoie - PHENIX Silicon Workshop 9

Functionality and Timing Tests

Simulation of read cycle and zero suppression:

6/8/03 J. Lajoie - PHENIX Silicon Workshop 10

Radiation Tolerance of FPGA’s• Development driven by satellite applications

• Xilinx QPro Series– Guaranteed for 100kRad operation (~9.0 rad/s rate)– SEL Immunity up to LET ~ 125 MeV cm2/mg– SEFI Immunity up to LET ~6 MeV cm2/mg (with TMR!)– Configuration data can be “scrubbed”– >100kRad possible with “self-annealing”

• ACTEL Rad-Hard Antifuse (RTSX-S)– Extensive use in industry – SEFI LET Immunity up to ~37 MeV cm2/mg (TMR in hardware!)– Antifuse (program once!)– ProASCI (Flash) not fully tested for rad-hard applications

• Need to more fully absorb test data and match PHENIX requirements

6/8/03 J. Lajoie - PHENIX Silicon Workshop 11

FPGA-based PILOT Chip Future Work

• Continue with software simulation• Multi-event readout cycle (async. READ/WRITE)• Bit-level zero suppression, smaller headers• Include ALICE1 and GOL behavioral models into

simulation• Move on to FPGA hardware, late summer/fall ‘03• Implement Triple Modular Redundancy for state machine

logic• Radiation Dose Estimates, FPGA evaluation for rad-hard

performance• Evaluate failure modes, rates.

6/8/03 J. Lajoie - PHENIX Silicon Workshop 12

Pixel Readout Bus

• 8 readout chips per ladder, 2 ladders laid end-to-end

ladder

control

pixel chip

READOUT CHIP

PIXELS DETECTOR 150 to 200µm

290µm

150 to 200µm

carbon fiber support cooling

passive components

Multi-layered kaptonALICE bus 32 signal lineseach chip read-out sequentially 8*25.6 s = 200 s

6/8/03 J. Lajoie - PHENIX Silicon Workshop 13

Line Density• Bus width is ~ 15mm• Line pitch= 15mm/(8*32) = 58m

– each output is single-ended• Existing busses

– D0 (2001) pitch 50m “fanned” out to 100m,• trace width 7-8m

– D0 (2002) two // cables each with pitch 91m• avoided “fan”

– Both made by Dyconex (Swiss), other manufacturers identified

• Manufacturing problems scale with bus length!• Requirements are close to state-of-the-art for production

– Our length (~50cm), requirements not unreasonable

6/8/03 J. Lajoie - PHENIX Silicon Workshop 14

Bonding Chip to Bus

READOUT CHIP

PIXELS DETECTOR 150 to 200µm

290µm

150 to 200µm

carbon fiber support cooling

passive components

wire bond densitysame as ALICE ~ 12mm/32 ~ 375 m

6/8/03 J. Lajoie - PHENIX Silicon Workshop 15

Parallel Bus Summary

• Worthwhile considering what limits going to an 8*32 signal bus – allows us to read all eight chips in parallel– time = (15 s + time to write) ~ 40 s

• Structure of readout bus must match requirements and manufacturing capabilities– Power and ground planes or traces?– Two or four layer bus?

6/8/03 J. Lajoie - PHENIX Silicon Workshop 16

Backups

6/8/03 J. Lajoie - PHENIX Silicon Workshop 17

Pilot Internal Structure

READ Module

WRITE Module

8b-Counter

L1a

addr

NEVRCE

coutCount_ enable

From ALICE1

To

GOL

6/8/03 J. Lajoie - PHENIX Silicon Workshop 18

Read Module + FIFO (Parallel Operation, Replicated 8x)

Read Control LogicX

64b X 256 deep FIFOX

(Synchronous)

L1a

From ALICE1

NEVRCE

64b Data_in

addr

Rd_enable

coutCount_enable

64b Data_out

Wr_enable

6/8/03 J. Lajoie - PHENIX Silicon Workshop 19

FIFO + Write Module (Daisy-Chain Operation, Replicated 8x)

64b X 256 deep FIFOX

(Synchronous)

64b Data_out

Write Control LogicX

Donex

Wr_enable

L1a

Startx

Done x-1

Start x+1

16b to MUXempty

6/8/03 J. Lajoie - PHENIX Silicon Workshop 20

Write Daisy Chain

MUX

FIFO x-1

FIFO x

FIFO x+1

WRITE x-1

WRITE x

WRITE x+1

GOL

6/8/03 J. Lajoie - PHENIX Silicon Workshop 21

6/8/03 J. Lajoie - PHENIX Silicon Workshop 22

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