64-Channel UWB Wireless Neural Vector Analyzerand Phase Synchrony-Triggered Stimulator SoC

Karim Abdelhalim, Hamed Mazhab Jafari, Larysa Kokarovtseva†, Jose Luis Perez Velazquez†, Roman GenovDepartment of Electrical and Computer Engineering, University of Toronto, Canada; Email: roman@eecg.utoronto.ca

†Brain and Behavior Programme and Division of Neurology, Hospital for Sick Children, University of Toronto, Canada

Abstract— A UWB 64-channel responsive neural stimulator ispresented. It wirelessly monitors magnitude, phase and phasesynchronization of neural signals. Abnormal phase synchronytriggers programmable-waveform biphasic current-mode stim-ulation in a closed loop. To implement these functionalities,the SoC integrates 64 neural recording amplifiers with tunableswitched-capacitor (SC) bandpass filters, 64 multiplying 8-bitSAR ADCs, 64 programmable 16-tap FIR filters, a tri-coreCORDIC processor, 64 biphasic current stimulation channels,and a 3.1-10.4GHz UWB wireless transmitter onto a 4mm × 3mm0.13µm CMOS die. The SoC dissipates 1.4mW/1.5mW whenrecording/stimulating and has been validated in early detectionand abortion of epileptic seizures in freely moving rodents on-lineand in early seizure detection in humans off-line.

I. INTRODUCTION

Abnormal coordinated interactions in various regions of thebrain are widely recognized as key indicators of pathologicalbrain states in numerous neurological disorders such as thoselisted in Fig. 1. Quantifying phase synchronization amongneural oscillations is effective for diagnostics, monitoring ortreatment of such disorders. For example, in epilepsy largefluctuations of phase synchrony in narrow frequency bandswithin the neural signal spectrum are among the earliestprecursors of an upcoming seizure [1]. Detecting the seizurebefore it develops is critical in a closed-loop implantableneural stimulator. Chances of aborting a seizure are muchhigher if responsive electrical stimulation takes place beforeone fully develops [1]. Previously reported integrated neuralinterfaces [2]–[6] and commercial neural stimulators currentlylack this capability.

We present a wireless 0.13µm CMOS SoC with 64 neuralrecording channels that performs neural vector analysis andresponsive neural stimulation based on phase synchrony. It isthe first reported on-chip neural vector analyzer to processnot only the magnitude, but also the phase of neural signals.It is also the first SoC to demonstrate real-time on-chipcomputation of the phase synchrony among neural signalsand to demonstrate on-chip closed-loop stimulation based onbivarite signal processing. This approach has shown promiseto outperform other methods used in commercially availableneural stimulators for epilepsy treatment [1].

II. VLSI ARCHITECTURE

The functional diagram is depicted in Fig. 1. The loopconsists of the neural vector analyzer in the feed-forward pathand the phase synchrony-triggered neural stimulator in the

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feedback. Pairs of neural signals are amplified and filteredin a narrow pass-band in which abnormal synchrony is mon-itored. In-phase (I) and quadrature-phase (Q) components arecomputed by allpass and Hilbert filters, respectively. I and Qare used to compute magnitude, phase, and phase differenceof the signals which are then wirelessly monitored. Phaselocking value (PLV), a common metric of phase synchrony,is computed in the feedback. The current-mode stimulator istriggered when the PLV indicates abnormal phase synchronylevels. In epilepsy, seizure precursors are abnormally largefluctuations in PLV which can be detected by thresholding.

A detailed block diagram of the SoC is presented in Fig. 2.There are 64 ADCs organized in a scalable manner, one perneural input, for raw neural data monitoring (not shown).In the phase synchrony computation mode, the ADCs arere-configured as multiplying ADCs (MADCs) to performmultiplications, the most computationally intensive operationsin allpass and Hilbert FIR filters. A bank of eight MADCscombined with a 16-tap folded add-and-delay line yields a16-tap transposed symmetric mixed-signal FIR filter. MADCsare time-multiplexed among eight neural inputs and eight add-and-delay lines to comprise eight FIR filters [7]. The useof in-channel MADCs eliminates 64 8-bit digital multipliersclocked at 8× sampling rate. As opposed to [7], in thisdesign, two sets of filters, eight allpass and eight HilbertFIR filters, are implemented to compute I and Q components,respectively, in two sets of eight recording channels. Thesecircuits are repeated four times to accommodate 64 inputs. Thephase, magnitude and phase synchronization processor utilizesthree digital CORDIC cores [8]. The computed PLV value is

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compared with programmed stimulation criteria. When trig-gered, the 64-channel neural stimulator generates individuallyprogrammable biphasic currents. A UWB wireless transmittersends raw ADC data, neural vector parameters and PLV off-chip. All control signals are generated by an on-chip controller.

III. CIRCUIT IMPLEMENTATION

Fig. 3 depicts the circuit implementation of the analogfront-end. Two stages of AC-coupled capacitive feedbackamplifiers provide 54-60dB programmable gain. The first stageis chopper stabilized. The high linearity of the second stageis achieved by biasing subthreshold MOS transistors with aconstant voltage generated by source followers [7]. The 2nd-order bi-quad switched capacitor (SC) BPF with the qualityfactor of 3.2 selects a narrow neural band of interest. TheSC LPF removes aliasing components introduced by the BPF.A subsequent compact tuneable buffered RC LPF removesaliasing caused by the SC LPF.

Fig. 4(a) shows the circuit implementation of a set of 8-channel recording and stimulation signal paths. To extractthe real and imaginary components the RC LPF drives twosets of eight parallel successive approximation register (SAR)MADCs. Each MADC requires an MDAC that uses a binary-weighted split-capacitor DAC. It multiplies two digital valuesat the cost of a small overhead of three two-input logic gates

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per bit. One set of eight MADCs implements an FIR filterprogrammed for an all pass-filter (I-extraction). The other setof eight MADCs, implements an FIR filter programmed for theHilbert transform (Q-extraction). In this mode, 32 recordingchannels utilize 64 FIR filters (32 allpass and 32 Hilbert FIRfilters) as shown for 8 channels in Fig. 4(a). Both the I andQ signals are sent to the on-chip digital processor. The 10-bit processor utilizes three CORDIC cores to simultaneouslycompute the magnitude, phase, phase difference and the phase-locking value per sample. Expensive multiplication operationsare eliminated as only shift operations are performed bythe CORDIC processor. An all-digital delay line-based UWBtransmitter shown in Fig. 4(b) generates a double-differentiatedGaussian pulse. The delay cells in all the paths are imple-mented as current-starved inverters to allow for tuning of theUWB pulse width for two different FCC bands (0-1GHz or3.1-10.4GHz).

In the stimulation mode, the MDACs and SAR logic arereused in the neural stimulation channel for programmablewaveform generation as shown in Fig. 4(c). A V-I converterand a 3.3V biphasic current driver deliver the triggered stim-ulus. An in-channel 12-bit memory stores an 8-bit currentamplitude and a 4-bit duty cycle values. The reuse of MDACsand SAR logic eliminates 64 8-bit DACs and 64 digital dutycycle controllers.

IV. EXPERIMENTAL RESULTS

The micrograph of the 4mm × 3mm SoC implementedin a standard 1P8M 0.13µm CMOS technology is shown inFig. 5(a). There is a total of 1kB of on-chip memory andapproximately 1 million transistors. The layout of the channelincluding the neural recording amplifier, SC bandpass filter,biphasic current driver, SAR multiplying ADC/DAC and a 22-bit memory is depicted in Fig. 5(b). Each 300µm × 300µmchannel has a bondpad to be flip-chip bonded directly to amicroelectrode array.

The experimentally measured results for the analog frontend are depicted in Fig. 6(a)-(c). The experimentally measuredfrequency response of the amplifiers and the SC filters forseveral frequency bands is shown in Fig. 6(d). An FFT of theADC output yields ENOB of 7.6-bits at 28 kS/s as presented

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Fig. 5. (a) Micrograph of the 4mm × 3mm 0.13µm CMOS SoC. (b) Layoutof the 300µm × 300µm recording and stimulation channel.

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in Fig. 6 (e). Fig. 6(f) demonstrates experimentally computedI and Q components of the shown input fed through the fullsignal path.

The full signal path from the input of the neural recordingchannel to the output of the digital processor was also exper-imentally characterized. Fig. 7(a) depicts the phase differencebetween two 100µV sinusoidal signals computed on-chip withless than 1.5 percent deviation from the ideal case. Fig. 7(b)shows the magnitude of a 30Hz 300µVpk sinusoid modulatedwith a higher-frequency sinusoid computed on-chip. Fig. 7(c)shows the PLV between two signals with the frequency ofone signal held at three fixed values and the frequency of theother swept. Fig. 7(d) depicts experimentally measured neuralstimulator output current into a saline solution for various am-plitude and duty cycle settings. The experimentally measuredUWB pulse in the 0-1GHz band is shown in Fig. 8(a). The

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measured output spectrum and the corresponding FCC maskfor the UWB transmitter operating in the 0 to 1GHz frequencyband is depicted in Fig. 8(b). Fig. 8(c) shows transmitted10MB/s Manchester encoded-data and Fig. 8(d) displays thewirelessly received UWB modulated data utilizing the 3.1-10.4GHz frequency band over a 5cm distance.

The SoC was validated in on-line in vivo experiments ina population of 4 freely moving rats and in off-line humanECoG data. In animal studies, two types of rat models ofepilepsy were employed, non-convulsive epilepsy induced bygamma butyrolactone (GBL) and convulsive epilepsy inducedby kainic acid, both recorded and stimulated with 8 depthelectrodes. For rats, the SC BPF was set to either a 4Hz or 8Hzcenter frequency to capture the abnormal phase synchrony inthese frequency bands. An example of the experimental resultsfor non-convulsive seizures (4Hz) is shown in Fig. 9(a). GBLinjected at time t=0s induces a seizure at time t=222s. At timet=50s, 172s before the seizure starts, the PLV at 4Hz computedby the chip increases, resulting in an early seizure detection.

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Fig. 9. Results of in-vivo testing in freely moving rats demonstrating (a) early detection of a seizure triggered by a GBL injection, (b) early detection ofa seizure triggered by kainic acid injection, and (c) abortion of a seizure using the on-chip neural stimulator. (d) An example of a result of off-line humanseizure detection for a University of Toronto epilepsy patient.

TABLE I

STATE-OF-THE-ART NEURAL RECORDING AND/OR STIMULATION SOCS

Spec. [5] [2] [4] [3] [7] THISWORK

Pwr. Diss.(mW) 0.375 0.077 0.27 6.5 5.03 1.4/1.5Tech.(μm) 0.35 0.18 0.18 0.13 0.13 0.13Area(mm)2 10.9 6.25 2.7 25 12 12Supply(V) 1.5 1.0 1.8 1.2 1.2 1.2/3.3# Record Chan. 4 1 8 96 64 64Pwr/chan.(μW) 32.8 4 9 68 6.3 10Gain(dB) 52-66 72 - 56 54-60 54-60Noise(μVrms) 3.1 1.3 - 2.2 6.5 5.1fL3dB (Hz) 0.1 0.5 - 280 10 1fH3dB (Hz) 12k 100 - 10k 5k 5kCMRR(dB) 58 60 - - 75 78ADC SNDR 54.7 65 44 60.3 48.5 47.5SC Filter - BPF BPF BPF - BPFSignal Proc. Yes Yes Yes No Yes YesFIR Filters - 7x48T 1x22T - 64x16T 64x16TIIR Filters 1x1T - - - - -DSP - Feature - - - Tri-

Extract CORDICUnivariate 4x 1x - - 64x 64xMag

Operations Spike Mag Spike 64xφBivariate - - - - - 32xΔφ

Operations 32xPLVClosed-loop Yes No Yes No No Yes

Stimulation# Stim. Chan. 4 - 64 - - 64DAC Res.(bits) 6 - 7 - - 8Compliance(V) 3.2 - 1.8 - - 2Current(mA) 0-0.1 - 0-0.14 - - 0.01-1.2Duty Cycle Res. No - 6-bit - - 4-bitWireless TX Yes No No No Yes YesModulation FSK - - - FSK UWBDate-rate(Mb/s) - - - - 1.5 10TX Pwr.(mW) 0.2 - - - 3.7 0.1

In Fig. 9(b), a convulsive seizure (8Hz) in a rat is induced bya kainic acid injection at time t=-5min and detected before theseizure starts. In Fig. 9(c), a 5Hz 100µA biphasic current burstthat starts early in the seizure successfully aborts it. Overall,on-chip responsive electrical stimulation aborted 80 percent ofall rat seizures. For spontaneous seizures in humans the SCBPF center frequency was set to 16Hz to capture abnormalsynchrony at that frequency. Fig. 9(d) depicts an example ofon-chip off-line early seizure detection in ECoG data recordedfrom an epilepsy patient at the Hospital for Sick Children inToronto.

A comparitive analysis is given in Table I. This designdemonstrates advanced functionality among recently publishedstate-of-the-art neural recording and stimulation SoCs. It com-

bines 64 recording channels with SC bandpass filters, 64stimulation channels, 64 programmable 16-tap FIR filters,a tri-core CORDIC processor and an UWB transmitter. Itcomputes phase and phase synchronization which triggersclosed-loop current-mode neural stimulation.

V. CONCLUSION

A 0.13µm CMOS wireless closed-loop neural recording andstimulation SoC is presented. The SoC has 64 neural recordingand stimulation channels. The on-chip neural vector analyzercomputes phase synchrony among inputs to trigger a closed-loop biphasic current-mode neural stimulation. The total powerdissipation is 1.4mW from a 1.2V supply in the recordingmode and 1.5mW from a 3.3V supply in the stimulation mode.The system was characterized in vivo and demonstrates earlyseizure detection and abortion in freely moving rodents andoff-line seizure detection in humans.

REFERENCES

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[2] N. Verma, Ali Shoeb, J. Bohorquez, Joel Dawson, John Guttag, andAnantha P. Chandrakasan, “A micro-power EEG acquisition SoC withintegrated feature extraction processor for a chronic seizure detectionsystem,” IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 804–816,April 2010.

[3] Hua Gao, Ross M. Walker, Paul Nuyujukian, Kofi A. A. Makinwa,Krishna V. Shenoy, Boris Murmann, and Teresa H. Meng, “HermesE:A 96-channel full data rate direct neural interface in 0.13µm CMOS,”IEEE Journal of Solid-State Circuits, vol. 47, no. 4, pp. 1043–1055, April2012.

[4] J. Lee, H. Rhew, D. R. Kipke, and M. P. Flynn, “A 64 channel pro-grammable closed-loop neurostimulator with 8 channel neural amplifierand logarithmic ADC,” IEEE Journal of Solid-State Circuits, vol. 45, no.9, pp. 1935–1945, September 2010.

[5] M. Azin, D. J. Guggenmos, S. Barbay, R. J. Nudo, and P. Mohseni, “Abattery-powered activity-dependent intracortical microstimulation IC forbrain-machine-brain interface,” IEEE Journal of Solid-State Circuits, vol.46, no. 4, pp. 731–745, April 2011.

[6] M S Chae, W Liu, Z Yang, T Chen, J Kim, M Sivaprakasam, and M Yuce,“A 128-channel 6mW wireless neural recording IC with on-the-fly spikesorting and UWB transmitter,” IEEE International Solid-State CircuitsConference Digest of Technical Papers, pp. 146–603, February 2008.

[7] K. Abdelhalim and R. Genov, “915-MHz wireless 64-channel neuralrecording SoC with programmable mixed-signal FIR filters,” IEEEEuropean Solid-State Circuits Conference, pp. 223–226, September 2011.

[8] K. Abdelhalim, V. Smolyakov, and R. Genov, “Phase-synchronizationearly epileptic seizure detector VLSI architecture,” IEEE Transactionson Biomedical Circuits and Systems, vol. 5, no. 5, pp. 430–438, October2011.

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