5.nov.2008k.tanaka spw conf. at nara1 proposal of csp based network design and construction kazuto...

5.nov.2008 k.tanaka SpW Conf. at Nara 1

Proposal of CSP based Network Design and Construction

Kazuto Tanaka ,Satoshi Iwanami ,Takeshi Yamakawa,Chikara Fukunaga （ Tokyo Metropolitan University)

Kazuto Matsui （ Prominent Network inc. ）Takashi Yoshida （ Smart Scape inc. ）


SpaceWire Network as a parallel system

Parallel system with many processors and front-end devices

Extremely strict care to avoid resource conflicts and deadlocks for system design

sensor1processor1

processor2

sensor2

sensor3


CSP （ Communicating Sequential Processes ）

A formal design method for parallel processing systems

Parallel processing with channel communications Synchronization of processes Data sharing through channels between processes No shared memory between processes

Refinement with mathematical deduction Check possible failures (livelock, deadlock)

sensor1processor1

processor2

sensor2

sensor3

： channel communication ： process


IEEE1355

Router Network System(IEEE1355)

Network on an FPGA chip Components

TPCORE (processor) OD convertor (protocol

convertor) Router (link switch unit)

TPCORE0

TPCORE1

ODconvertor

RouterTPCORE

2OD

convertor

ODconvertor

* We regard SpW and IEEE1355 are almost identical for the moment

FPGA

・・・

・・・

・・・


TPCORE Processor (homemade 2003)

Clock frequency : 24MHz Instruction set compatible with transputer (Inmos ltd., UK) Parallel processing with Occam (language) without Operating

System Flexible networks (on a FPGA chip) with four external I/Fs (OS-Link)

OS-Link is a simple bit serial link No destination address in OS-Link

Host PC

TP3 TP2

Host PC

TP0

TP1

TP2

TP3

TP0

TP1

mesh tree

R

Host PC

TP0

:process OS-Link


OS-Link and IEEE1355 （ DS ） -Link

OS-Link Simple protocol No destination address

IEEE1355(DS)-Link Complex protocol, layered structure (packet , character (=

token )) Header contains destination address

data

OS-Link IEEE1355(DS)-Link

2 start-bit 1 end-bitdata

1parity-bit 1 control or data select bit

・・header end of packet

・・・・・・

end of message

・・・・・・・・・・

・・


OS to DS and DS to OS conversion Main components

FCC (Flow Control Character) –rx ,FCC-tx Flow control for communication character transmission of DS-Link

protocol DS selector

Selection of FCC or other character (both directional)

OD-convertor

character

OSrx

FCC-rx

FCC-tx

Paritycheck

OStxFCC

character

FCC

DSselectorDS

tx

DSrx

OS-Linkin

OD convertor（ DO convertor）

FIFO

FIFO OS-Linkout

DS-Linkout

DS-Linkin


Router

TPCORE0

TPCORE1

OD

DSanalyzer

OD

TPCORE2

OD

RouterXbar control

DSanalyzer

DSanalyzer

Xbar

Components DS-analyzer

Pick up the destination address from header of input packet FCC and character transmission and DS selector

Crossbar (Xbar) Connection to the destination channel (bidirectional)

: destination address


OS OS

Time Sequence of the Network Packet transmitted by TPCORE0 (OS-Link) Converted to DS-Link by OD convertor Router switch Reverted to OS-Link Data accepted by TPCORE2(OS-Link)

example of packet transfer ： address=2,data=FF

OD ODDS DSRouter

DSOS

OS

DS

TP0 TP2

3.32 μｓ


Summary

Network-Router and OD convertor (IEEE1355) have been designed based on CSP.

By refinement checking ,We find no deadlock , no livelock in these devices as a parallel system.

Detailed discussion of CSP will be found in our another presentation (Poster).

Correct data communication has been confirmed using TPCOREs.

We measured DS-Link transfer rate . It is 20.29Mbps. Theoretical value is 20.28Mbps .

The difference is less than a clock width (48MHz). The good agreement has been achieved.

From this study, we found CSP as a good design method for parallel systems.

Thank you for your attention !!

5.nov.2008k.tanaka spw conf. at nara1 proposal of csp based network design and construction kazuto...

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