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4.1 Accelerate Measurements Using Timing and Synchronization Architectures

Improving Test Throughput with Emerging Technologies

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Power Supply

Need for Advanced Timing and Synchronization

Oscilloscope

Logic Analyzer

Spectrum AnalyzerDMM

Communications Analyzer

LCR Meter

FunctionGenerator

Pattern Generator

Programmable Switch

Images courtesy of Fluke, Rohde & Schwarz, LeCroy, Ascor, Agilent, and Tektronix

This slide from the keynote reinforces the growing complexity of devices under test. With the increased functionality built into a device, the test complexity and test time required has grown. In order to meet these growing needs, your test application requires advanced timing and synchronization to accelerate test time or actually enable the complex measurements. Traditional methods use software to force delays to compensate for a lack of integrated timing and synchronization. In addition, cabling introduces issues of impedance matching, noise, and propagation delay. Meeting these advanced test needs requires superior timing and synchronization.

Listed above are a few of the key benefits of having superior timing and synchronization.

Reduce test time by using advanced timing and synchronization by removing built in delays to tightly correlate stimulus and measurements.

• Synchronization of a digitizer (or multiple digitizers) to a source for stimulus-response applications

• Synchronization of DMM to a switch to access multiple test nodes when the DUT has settled to a steady state

Enable complex measurements and applications

• Synchronization of a digitizer to a counter/timer for position-correlated measurements

• Synchronization of motion control with image acquisition

• Synchronization of data acquisition with CAN

Improve measurement accuracy by having better correlated measurements through minimal propagation delay and skew.

• Synchronization of multiple digitizers/scopes to simultaneously sample multiple channels

• Phase-locking an arbitrary waveform generator to a stable reference clock to improve timing accuracy by 500

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Timing and Synchronization Tools

� Methods� Start and Stop Triggers� Phase Lock Looping� Trigger Clock (TClk)

� Implementations� PXI Synchronization Backplane� IEEE 1588 Synchronization (over Ethernet)

There are many timing and synchronization tools available. Methods used to correlate events include start and stop triggers and clocks. Phase-lock looping adds additional accuracy by tying sampling clocks to reference clocks to prevent drift. Building on that technology, TClkincorporates both triggers and clocks to provide minimal skew between devices.

Implementation of these tools are provided by some bus technologies. Not all bus technologies provide the same level of synchronization. We will examine the better implementations, PXI and 1588.

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Start and Stop Triggers

� Devices communicate with each other for handshaking

Start

ClockStart Acquisition Stop Acquisition

Stop

1 2 3 4 5

Slaves

� Master initiates and terminates events on multiple devices

Master

Built into PXI, VXI, GPIB, LAN, USB, 1394 Built into PXI and VXI

Trigger

Start and stop triggers signal when to initiate or terminate events on instruments. For instance, you can use a trigger to signal when to start an acquisition and another trigger to tell the instrument to stop the acquisition. You can use these triggers in various ways.

For example, a master device can send out triggers to multiple slaves to synchronize events on those instruments. This type of trigger functionality is supported in PXI, GPIB, LAN, USB, and 1394. Or you could use triggers to communicate between devices for handshaking. For instance, device A sends a trigger to device B so that device B can begin an event. When device B is finished, it send a trigger back to device A. At this point device A performs an event and then so forth. This type of trigger functionality is provided in PXI.

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Phase-Locked Looping

Clock 2

100 MHz clocks not phase locked

PLL

Clock 1

Clock 2

Reference Clock

Clock 1

PLL

10 MHz Ref clock

100 MHz clocks synchronized from Ref 10 MHz clocks using PLL

Clocks provide a regular timing source for the instruments. They provide a timing reference for events. Clocks can come from a master or an external device. For lower frequency measurements, you can share clocks over trigger lines to synchronize timing on multiple instruments.

For better alignment of your clocks, you can phase-lock loop internal sample clocks to a reference clock. Notice in the top image both internal clocks have the same frequency, but they are not in phase. This means that the samples will be taken at slightly different times (since the rising edges are not lined up).

In the second image both internal sampling clocks have been phase-lock looped to a 10 MHz reference signal. Notice how the rising edges for each clock are now aligned.

By synchronizing the device’s oscillator to common reference clock, this eliminates the need to share a sample clock among devices, and reduces clock error due to phase delays.

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Trigger Clock (TClk) Synchronization

� Ensures that the master and slave devices start on the same sample clock cycle

� Enables synchronization of devices with different sample clocks

� Aligns signals within tens of picoseconds

TClk: a slower clock signal that triggers and events are passed relative to

TClk provides a high level of synchronization between instruments. It sends a slower clock signal relative to triggers and events. TClk, an additional signal in the SMC TClk technology, can align sample clocks and keep them aligned over time. The figure shows a timing diagram of two synchronized devices with and without TClk. You can see that without TClk, the master device starts at A, and the slave starts at B. With TClk, both the master and slave start together at A.

With TClk, the SMC generates a local copy of the TClk signal by dividing down the sample clock to a frequency low enough to reliably send and receive triggers. If the sample clocks on different modules are at different frequencies, TClk is the greatest common factor of those frequencies (up to a maximum of 5 MHz). The master device pulses a trigger line synchronous to the TClk falling edge to generate a start trigger. All receiving devices, including the master device itself, receive the trigger pulse and start on the next rising edge of the TClk. Because the TClk period is 200 ns or greater, there is sufficient time for the trigger pulse to propagate to all devices before the next rising edge. This ensures that multiple devices can react to the same trigger signal in the same sample clock period. This method results in a channel-to-channel skew of typically 400 to 500 ps. To achieve even less skew, you can calibrate out the skew between TClk signals by adjusting the SMC devices’ sample clock delays with 10 ps resolution and using a multichannel, high-bandwidth oscilloscope for alignment.

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Star Trigger� Propagation delay less than 5 ns

� Less than 1 ns intermodule skew

PXI Timing and Synchronization Backplane

NI Synchronization and Memory Core (SMC)� For suite of modular

instruments� Picosecond level rms

clock jitter� TClk synchronization

System Reference Clock (CLK10)�Less than 1 ns skew

Moving onto implementations of these timing and synchronization methods. The PXI backplane allows you to implement these timing and synchronization tools. The backplane provides a trigger bus, a STAR trigger bus, a system reference clock, and local buses. By integrating these timing and synchronization tools into the backplane, PXI provides a simplified method for integrating instruments into a system for high performance and accuracy.

System Reference Clock—A highly accurate 10 MHz clock that cards can use as a common time base for synchronization of events.

Trigger Bus—Eight bused trigger lines link all PXI slots in a bus segment so that multiple boards can interact and control each other’s events through hardware.

Star Trigger—A special star trigger slot is defined which provides an independent dedicated line for each of up to 13 peripheral slots on a single backplane. A star trigger controller can be used to control, monitor, or route triggers among peripheral slots with very low skew (within 1 nanosecond).

Local Bus—A right and left local bus composed of 13 lines is available to each peripheral slot for private communication between adjacent slots. Pairs of peripherals can pass analog or digital signals back and forth using the local bus.

In addition, National Instruments provides a common architecture, called the NI Synchronization and Memory Core (SMC), for a suite of high-speed modular instruments. NI SMC implements T-clock synchronization so that you can implement the highest level of timing and synchronization resources. NI SMC provides a precise timing and synchronization engine that synchronize devices to sub-nanosecond level. It also allows you to calibrate trigger propagation delay and skew. NI SMC supplies picosecond level rms clock jitter, and allows you to adjust sample clock skew with tens of picoseconds resolution.

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Demo � PXI DMM and Switch T & SHardware versus Software handshaking

StartNI PXI-4070 FlexDMMNI PXI-2529 Switch

Input Trigger MeasurementComplete

Output Trigger Input Trigger

MeasurementExecute Switch

PXI Hardware Handshaking Diagram

This demonstration shows the performance improvement in handshaking between a DMM and Switch by upgrading from software-timed handshaking to PXI hardware handshaking.

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IEEE 1588 Synchronization� Accuracy determined by

� Capabilities of individual clocks � Topology and implementation of network components

� Protocol selects best 1588 clock, the �grandmaster clock�� Each subnet selects its best clock to be �master clock�� Within a subnet, all 1588 clocks synchronize to master

clock which synchronizes to grandmaster clock� Synchronize clocks to sub-microsecond level

Synchronization accuracy is determined primarily by the capabilities of the individual clocks and, depending on the specific network technology, on the topology and implementation of network components.

Typically, the 1588 protocol will select the best 1588 clock in the system, termed the grandmaster clock as the root of this hierarchy. Within each sub-net (by definition has no switches), the protocol selects the best clock of the sub-net to serve as the master clock of the sub-net. Within a sub-net, all 1588 clocks synchronize to the sub-net master that in turn synchronizes with the grandmaster. In a single sub-net system, the master and grandmaster are one and the same. In a system containing multiple boundary clocks, there is a hierarchy of masters with the grandmaster at the root. In all cases, the best clock is determined by comparing inherent stability, accuracy, resolution, and other descriptors defined by IEEE 1588 along with network topology information.

If a switch is used, it adds random delay to the system. You can avoid this by using a 1588 enabled switch.

Synchronization is achieved by master clocks periodically sending timing messages to their slaves.

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Implementation Comparison

Widely distributed applications, low frequency monitoring over large area

Sub-microsecondIEEE 1588 Synchronization

Higher frequency measurements, consumer electronics test, communications test, avionics, A/D converter test and characterization, power measurement

Tens of picosecondsPXI Synchronization Backplane

Example ApplicationsSynchronization Capability

Implementation

Both timing and synchronizations implementations are useful for your test system. By taking advantage of these timing and synchronization implementations, you can reduce test time, enable complex measurements and applications, and increase the accuracy of your test. PXI provides tighter synchronization at tens of picoseconds and is thus ideal for higher frequency measurements, consumer electronics test and so on. It allows you to perform some complex applications as well as increase the test system throughput. 1588 provides a way to achieve sub-microsecond synchronization over Ethernet which is useful for widely distributed applications or low frequency monitoring over a large area.