4 multiplexer micro- controller x 3 - university of illinois at ...logos.cs.uic.edu/366/notes/mano...

© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e

13-1

Micro-controller

Multiplexer

Decoder

4

3

Y

X


13-2

Track

Sector

Head positioning


13-3

RGB electron gunsPixel

R GB

Scan line


13-4

Centralprocessing

unit(CPU)

Interface

Keyboard

Inputdevice

Interface

CRTdisplay

Outputdevice

Interface

Printer

Outputdevice

Interface

Magneticdisk

Input and outputdevice

Data bus

Address bus

Control


13-5

Busbuffers

Bidirectional

data bus

Chip select

Register select

I/O read

I/O write

Timingand

control

CS

RS 1

RS 0

RD

WR

Inte

rnal

bus

Port Aregister

I/O data

Port Bregister

I/O data

Controlregister

Control lines

Statusregister

Status lines

To CPU To I/O device

RS1 RS0 Register selected

None: data bus in high-impedance statePort A registerPort B registerControl registerStatus register

x0101

x0011

CS

01111


13-6

(b) Source-initiated transfer

Source unit

Data bus

Strobe

Destination unit

Data bus

Strobe

(a) Destination-initiated transfer

Destination unit Source unit

Data bus

Strobe

Data bus

Strobe


13-7

(a) Destination-initiated transfer

Destination unit Source unit

Databus

Request

Reply

Data bus

Request

Reply

(b) Source-initiated transfer

Source unit

Data bus

RequestDestination unit

Reply

Data bus

Request

Reply


13-8

1 0 1

Start�bit

StopbitsCharacter bits

1 00 0 1


13-9

PowerKeyboard clock

Keyboard serial data

Ground

Keyboard

Microcontroller

Microcontroller

Inputregister

Outputregister

Controlregister

Statusregister

Keyboard controllerand interfaceI/O write

I/O read

Address bus

Data bus

Interrupt request

CPU


13-10

Computer

Root Hub

Monitor Printer

Mouse Joystick

Scanner

Microphone Speaker Speaker

Keyboard

Hub Hub

HubHub


13-11

Data

NRZI

0 10 0 0 0 0 01 1 1 11 1


13-12

Packet Specific Data

(a) General packet format

EOPSYNC PID CRC

(b) Output packet

SYNC8 bits

Type4 bits1001

Check4 bits0110

EndpointAddress

4 bits

DeviceAddress

7 bitsCRC EOP

(c) Data packet (Data0 type)

SYNC8 bits

Type4 bits1100

Check4 bits0011

CRCData(Up to 1024 bytes) EOP

(d) Handshake packet (Acknowledge type)

SYNC8 bits

Type4 bits0100

Check4 bits1011

EOP


13-13

CPU

Interface

Data register

Statusregister

Flag

Data bus

Address bus

I/O read

I/O write

I/O bus

Ready

Acknowledge

I/O�device


13-14

Check flag bit

Flag

Read data register

Transfer data to memory

Continueprogram

0

No

Yes

Read status register

1

Operationcomplete?


13-15

PI PODevice 0

PI PODevice 1

PI PODevice 2

CPU data bus

VAD 0 VAD 1 VAD 2

To next�device

Interrupt request

Interrupt acknowledge

CPU


13-16

PI

00

11

RF

01

01

PO

00

10

Enable

00

01

PIPriority in

Enable Vector address

VAD

Priority outPO

Delay

Interrupt�request�from device

RFS

R

Interrupt request�to CPU


13-17

Interruptregister

3

2

1

0 0

0

0

0

0

0

3

2

1

0

Highestpriority

Lowestpriority

Mask�register

D3

D2

D1

D0

Priority�encoder

A0

A1

Interruptacknowledge

from CPU

VAD

Interrupt�to CPU

V

Figure 4-12


13-18

Bus request

Bus granted

BR

BG

AB

DB

RD

WR

Address bus

Data bus

Read

Write

CPUHigh impedance(disabled)if BG 5 1


13-19

Inte

rnal

bus

Data bus�buffers

Control�logic

DS

RS

RD

WR

BR

BG

DMA select

Register select

Read

Write

Bus request

Bus granted

InterruptDMA request

DMA acknowledge to I/O device

Address bus�buffers

Address register

Word-count register

Control register

Data bus

Address bus


13-20

Read control

Write control

Address bus

Interrupt

BG

BR

CPU

RD WR Address Data

Memory

RD WR Address Data

Address�decoder

I/Operipheral

device

DMA�controller

DMA request

DMA acknowledge

DS

RS

BR

BG

Interrupt

Data bus

RD WR Address Data


13-21

Memory unit

Central processingunit (CPU)

Input-output�processor (IOP)

Memory busPeripheral devices

PD PD PD PD

I/O bus


13-22

Continue

Transfer status wordto memory location

I/O transfer completed;interrupt CPU

Conduct I/O transfersusing DMA:

prepare status report

Access memory forIOP program

Transfer status wordto memory location

Send instructionto test IOP path

If status O.K.,send start I/O

instruction to IOP

CPU continues withanother program

Request IOP status

Check status wordfor correct transfer

CPU operations IOP operations

4 multiplexer micro- controller x 3 - university of illinois at ...logos.cs.uic.edu/366/notes/mano...

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