4-Bit Counter Design and Simulation using Microwind, Dsch3.0

and Spice

Mr. Nayyer Abbas Hira Shaukat 2010131

OBJECTIVE

“The purpose of this project is to design with Microwind a 4-bit asynchronous counter with a reset function.”

BLOCK DIAGRAM

• Transistor level

• Microwind

NOT Gate

• DSCH• Microwind

Complex Gate • DSCH• Microwind

D Latch

• By compiling earlier layouts

D-Register • Cascading D-Registers

Counter

Design Details

NOT Gate

• One NMOS and one PMOS is required• Gates are interconnected to do the input• Sources are interconnected to do the output

NOT Gate (Schematic Diagram)

NOT Gate (Microwind design)

Layout of the NOT Gate (Microwind)

Complex Gate

• Compressed and optimized design• Error in the design of paper• Design characteristics do not need to be

followed

Complex Gate

Complex Gate (Schematic Diagram)

Schematic diagram of a complex gate

Complex Gate (Microwind design)

Layout of a complex gate (Microwind)

D Latch

• D Latch is designed using two Complex Gates and one Inverter

D Latch (Schematic Diagram)

D Latch (Microwind Design)

Layout of a D Latch (Microwind)

D Register

• Master-Slave structure is chosen • 2 D Latches and a NOT Gate is used to get a

single design

D Register (Schematic Diagram)

D Register (Microwind Design)

COUNTER

• 4 D Registers are cascaded • Output of previous register is given to the

clock of next register

Counter (Schematic Diagram)

Counter (Microwind Design)

The End