UNIT -III

8086 Interrupts And Interrupt Responses:

An 8086 interrupt can come from any one of three sources. One source is an external signal applied to the non-maskable interrupt (INTR) input pin. An interrupt called by a signal applied to one of these inputs is referred to as hardware interrupt.

A second source of an interrupt is execution of the Interrupt instruction, INT. This is referred to as software interrupt.

The third source of an interrupt is some error condition produced in the 8086 by the execution of an instruction. An example of this is the divide – by – zero interrupt.

At the end of each instruction cycle the 8086 checks to see if any interrupts have been requested. If an interrupt has been requested, the 8086 responds to the interrupts by stepping through the following series of major actions.

It decrements the stack pointer by 2 and pushes the flag register on the stack.

It disables the 8086 INTR interrupt input by clearing the interrupt flag (IF) in the flag register.

It resets the trap flag (TF) in the flag register.

It decrements the stack pointer by 2 and pushes the current code segment contents on the stack.

It decrements the stack pointer again by 2 and pushes the current instruction pointer contents on the stack.

It does an indirect far jump to the start of the procedure (that is available or written by the programmer) to responds to the interrupt.

The 8086 pushes the flag register on to the stack, disables the INTR input and the single step function, and does essentially an indirect FAR CALL to an interrupt service procedure. An IRET instruction at the end of the interrupt service procedure returns execution to the main program.

For an indirect FAR CALL, the 8086 gets the new values for CS and IP from four memory addresses likewise, when the 8086 responds to an interrupt, if goes to four memory locations to get the CS and IP values for the start of the interrupt service procedure.

In an 8086 system, the first 1KB of memory, from 00000H to 003FFH, is set aside as a table for storing the starting addresses of interrupt service procedures. Since 4 bytes are required to store the CS and IP values for each interrupt service procedure, the table can hold the starting addresses for up to 256 interrupt procedures. The starting address of an interrupt service procedure is called the interrupt vector or the interrupt pointer, so the table is referred to as the interrupt vector table or the interrupt-pointer table.

Fig 3.1: 8086 interrupt pointer table

Each double word interrupt vector is identified by a number from 0 to 255 Intel calls this number the type of the interrupts.

The lowest five types are dedicated to specific interrupts, such as the divide-by-zero interrupt. Interrupt types 5 to 31 are reserved by Intel for use in more complex microprocessor such as 80286, 80386 and 80486. The upper 224 interrupt types, from 32 to 255, are available for hardware or software interrupt.

3.1 8086 Interrupt Types:

Divide-by-zero interrupts – Type 0:

The 8086 will automatically do a Type 0 interrupt if the result of a DIV or IDIV operation is too large to fit in the destination register.

Since the 8086 Type 0 response is automatic and cannot be disabled in any way. One way is, we first make sure the divisor is not zero.

Single – step interrupts – Type 1:

When in single – step mode, a system will stop after execution each instruction and wait for further direction from the programmer.

If the 8086 trap flag is set, the 8086 will automatically do a type1 interrupt after each instruction executes.

The trap flag is reset when the 8086 does a Type1 interrupt, so the single step mode will be disabled during the interrupt service procedure.

Non-Maskable interrupts – Type 2:

The 8086 will automatically do type 2 interrupt response when it receives a low- to-high transition on its NMI input pin.

The name non-maskable given to this input pin on the 8086 means that the Type 2 interrupt response can not be disabled (masked) by any program instructions.

Break-point interrupts – Type 3:

The Type 3 interrupt is produced by execution of the INT 3 instruction. The main use of the Type 3 interrupt is to implement a breakpoint function in a system.

Overflow interrupt – Type 4:

The 8086 overflow flag (OF) will be set if the signed result of an arithmetic operation on two signed numbers is too large to be represented in the destination register or memory location.

There are two major ways to detect and respond to an overflow error in a program. One way is to put the Jump if overflow instruction, JO immediately after the arithmetic instruction. The second way of detecting and responding to an overflow error is to put the “Interrupt on overflow instruction, INTO”, immediately after the arithmetic instruction in the program.

3.7.1 Software Interrupts:

The 8086 INT instruction can be used to cause the 8086 to do any one of the 256 possible interrupt types. The desired interrupt type is specified as a part of the instruction.

For example, INT 3 is used to insert breakpoints in programs for debugging an INT 0 instruction to send execution to divide–by–zero interrupt service procedure an INT 2 instruction to send execution to an NMI interrupt service procedure.

INTR interrupts:

The 8086 INTR input allows some external signal to interrupt execution of a program. Unlike the NMI input, however, INTR can be masked (disable) so that it can not cause an interrupt. If the interrupt flag (IF) is cleared, then the INTR input is disabled IF can be cleared at any time with the clear interrupt instruction (CLI). If the interrupt flag is set, the INTR input will be enabled, IF can be set at any time with the set interrupt instruction, STI.

When the 8086 is reset, the interrupt flag is automatically cleared. Before the 8086 can respond to an interrupt signal on its INTR input the IF has to be set with an STI instruction.

The interrupt flag (IF) is also automatically cleared as a part of the response of an 8086 to an interrupt. This is done for two reasons. First, it prevents a signal on the INTR input from

interrupting a higher-priority interrupt-service procedure in progress, but the INTR can be re-enabled with an STI instruction at any time.

The second reason for automatically disabling the INTR input at the start of an INTR interrupt-service procedure is to make use that a signal on the INTR input does not cause the 8086 to interrupt itself continuously.

When the 8086 responds to an INTR interrupt signal, its response is different from its response to other interrupts. The main difference is that for an INTR interrupt, the interrupt type is sent to the 8086 from an external hardware device such as the 8259A priority interrupt controller.

a)

b)

Fig 3.2: a) Block diagram showing an 8259 connected to an 8086

b) 8086 interrupt acknowledgement machine cycles.

When an 8259A receives an interrupt signal on one of its IR inputs, it sends an interrupt request signal to the INTR input of the 8086. If the INTR input of the 8086 has been enabled with an STI instruction, the 8086 will respond as shown by the waveform in figure.

The 8086 first does two interrupt-acknowledge machine cycles. The response of these two machine cycles is to get the interrupt type from the external device. At the start of the first interrupt-acknowledge machine cycles the 8086 floats the data bus lines, AD0 – AD15 and sends out an interrupt acknowledge pulse on its INTR output pin. This pulse (essentially) tells the 8259A to ‘get ready’. During second interrupt-acknowledge machine cycle the 8086 sends out another pulse on its INTA pulse, the 8259A puts the interrupt type (number) on the lower eight lines of the data bus, where it is read by the 8086.

Once the 8086 receives the interrupt type, if pushes the flag register on the stack, clears TF and IF, and pushes the CS and IP values of the next instruction on the stack. It then uses the type it read in from the external device to get the CS and IP values for the interrupt service procedure from the interrupt pointer table in memory. The IP value for the procedure will be put at an address equal to 4 times the type number, and the CS value will be put at an address equal to 4 times the type number plus 2 just as it done for the other interrupt.

The advantage of having an external device insert the desired interrupt type is that the external device can “funnel” interrupt signals from many sources into the INTR input pin on the 8086. When the 8086 responds with INTA pulses, the external device can send to the 8086 the interrupt type that corresponds to the source of the interrupt signal. The external device can also prevent an argument if two or more sources send interrupt signals at the same time.

3.3 8259a Priority Interrupt Controller:

In 8086 we have only two interrupt inputs, NMI and INTR. If NMI is saved for power failure interrupt then only INTR is left for all other applications. So, to handle interrupts from multiple sources, a priority interrupt controller (PCI) is used to funnel the interrupt signals into a single interrupt input on the micro processor.

3.3.1 8259a Overview And System Connections:

Working of INTR input:

If the 8086 interrupt flag is set and the INTR input receives a high signal, the 8086 will

Send out two interrupt acknowledge pulses on its INTA pin to the INTA pin of an 8259A PIC. The INTA pulses tell the 8259A to send the desired interrupt type to the 8086 on the data bus.

Multiply the interrupt type, it receives from the 8259A by 4 to produce an address in the interrupt vector table.

push the flags on the stack

clear CF and IF

push the return address on the stack

Get the starting address for the interrupt procedure from the interrupt vector table and load that address in CS and IP.

Execute the interrupt-service procedure.

Fig 3.2:8259A internal block diagram

The data bus allows the 8086 to send control words to the 8259A and read a status word from the 8259A. The RD and WR inputs control these transfers where the device is selected by asserting its chip select (CS) input low. The 8-bit data bus also allows the 8259A to send interrupt types to the 8286.

If the 8259A is properly enabled an interrupt signal applied to any one of inputs IR0 to IR7 will cause the 8259A to asserts its INT output pin high. If this pin is connected to the INTR pin of an 8086 and if the 8086 interrupt flag is set, then this high signal will cause the INTR response.

The INTA input of the 8259A is connected to the INTA output of the 8086. The 8259A uses the first INTA pulse from the 8086 to do some activities that depend on the mode in which it is programmed. When it receives the second INTA pulse from the 8086, the 8259A outputs an interrupt type on the 8-bit data bus. The interrupt type that it sends to the 8086 is determined by the IR input that received an interrupt signal. The 8259A funnels interrupt signals from up to 8 different sources into the 8086 INTR input, and it sends the 8086 a specified interrupt type for each of the 8 interrupt inputs.

In the fixed – priority mode, the IR0 input has the highest priority and IR7 has the lowest priority that is if two interrupt signals occur at the same time, the 8259A will service the one with the highest priority first.

Interrupt Mask Register (IMR): The interrupt mask register is used to disable (mask) or enable (unmask) individual interrupt inputs. Each bit in this register corresponds to the interrupt input with the same number.

Interrupt Request Register (IRR): The interrupt request register keeps track of which interrupt inputs are asking for service. If an interrupt input has an interrupt signal on it, then the corresponding bit in the interrupt request register will be set.

An interrupt signal must remain high on an IR input until after the falling edge of the first INTA pulse.

In-service Register (ISR): The in-service register keeps track of which interrupt inputs are currently being serviced. For each input that is currently being serviced, the corresponding bit will be set in the in-service register.

Priority Resolver: The priority resolver acts as a judge that determines if and when an interrupt request on one of the IR inputs gets serviced.

Suppose IR2 and IR4 are unmasked (enabled) and that an interrupt signal comes in on the IR4 input. The interrupt request register on the IR4 input will set bit 4 in the interrupt request register. The priority resolver will detect that this bit is set and check the bits in the in-service register (ISK) to see if a higher-priority input is being serviced. If a higher priority input is being serviced as indicated by a bit being set for that input in the ISR, then the priority resolver will take no action. If no higher-priority interrupt is being serviced, then the priority resolver will activate the circuitry which sends an interrupt signal to the 8086. When the 8086 responds with an INTA pulses, the 8259A will send the interrupt type that was specified for the IR4 input when the 8259A was initialized. The 8086 will use the type and execute the interrupt service procedure written for the IR4 interrupt.

Now, suppose that while the 8086 is executing IR4 service procedure, an interrupt signal arrives at the IR2 input of the 8259A. This will set bit 2 of the interrupt request register. Hence IR2 was unmasked (enabled), the priority resolver will detect that this bit in the IRR is set and make a division whether to send another interrupt signal to the 8086. To make the division, the priority resolver looks at the in-service register. If higher-priority bit in the IST is set, then a higher-priority interrupt is being serviced. The priority resolver will wait until the higher-priority bit in the IST is reset before sending an interrupt signal to the 8086 for the new interrupt input. If the priority resolver finds that the new interrupt has higher

priority than the highest priority interrupt currently being serviced, it will set the appropriate bit in the ISR and activate the circuitry which sends a new INT signal to the 8086. In this example, IR2 has a higher priority than IR4, so the priority resolver will set bit 2 of the ISR and activate the circuitry which sends a new INT signal to the 8086. If the 8086 INTR input was re-enabled with an STI instruction at the start of the IR4 service procedure as shown in fig (a) then this INT signal will interrupt the 8086 again.

At the end of the IR2 procedure, we send the 8259A a command word that resets bit 2 of the in-service register so that lower priority interrupts can be serviced. After that, an IRET instruction at the end of the IR2 procedure sends execution back to the interrupted IR4 procedure, we send the 8259A a command word which resets bit 4 of the in-service register so that lower priority interrupts can be serviced. An IRET instruction at the end of the IR4 procedure returns execution to the mainline program. This is a special case of nested procedure. Incidentally, if the IR4 procedure did not re-enable the 8086 INTR input with an STI instruction, the 8086 would not respond to the IR2 caused INT signal until it finished executing the IR4 procedure as shown in fig (b).

MAINLINE

Initialize 8259A IR4 IR2

Unmask IR2, IR4 procedure procedure

STI STI STI

EOI

EOI Command

Command IRET

IRET

(a)

MAIN LINE

Initialize 8259A IR4

Unmask IR2, IR4 procedure

STI STI

EOI Command IRET

IR2 Procedure

STI EOI Command

IRET

(b)

Fig 3.3: 8259A and 8086 program flow for IR4 interrupt followed by IR2 interrupt

(a) Response with INTR enabled in IR4 procedure (b) Response with INTR not enabled in IR4 procedure.

3.3.2 Cascading of 8259A:

Fig 3.4: Cascading of 8259As

More than one 8259A can be connected to 8086. If two 8259A are connected then we get a total of 15 interrupt inputs as shown in the above figure. Eight 8259A s can be connected like this to eight IR inputs of the first 8259A to give a total of 64 interrupt inputs. The 8259A which is connected to microprocessor is known as master and the others are known as slaves. The interrupt acknowledge signal from 8086 goes to both master and also slave. Each 8259A will have its own address. The cascade pins CAS2, CAS1, CAS0 of master are connected to the corresponding pins of slave. The cascade pins are output pins for master where as for the slaves they are input pins. Slaves are identified by SP/EN pin which is low.

If an interrupt signal is applied directly to IR inputs of the master, the master will send the interrupt type to 8086 when it receives the second INTA pulse from 8086 that the cascaded system behaves as a single 8259A system when the IR signal is placed on master.

Each slave will have a number ranging from 000 to 111 which are identified by the values of CAS0, CAS1, CAS2 lines of master depending upon the values of CAS0, CAS1, CAS2 the corresponding slave is enabled.

When slave receives an interrupt signal on one of its IR inputs then the slave will send an INT signal to IR input of master provided this interrupt input is unmasked and having the highest priority then any other inputs.

After receiving INT signal on IR from slave the master will send on INT signal to the 8086 INTR input provided IR input of master is non masked and the input is higher priority than any other IR inputs currently being serviced in the master.

8086 will go through INTR and send out two INTA pulses to both master and the slave. The master places a 3-bit slave identification number on the cascade lines to enable the slave when it receives the first INTA pulse. The slave ignores the first interrupt acknowledge pulse. When the slave receives the second INTA pulse from the 8086 the slave will send the interrupt number to 8086 on the lower eight data bus lines.

Programming the 8259A:

The 8259A is programmed by Initialization Command Words (ICW s) and Operation Command Words (OCWs). Initialization Command Words are programmed before the 8259A is able to function in the system and dictate the basic operation of the 8259A operation command words are programmed during the normal course of operation and allow the 8259A to function properly.

Fig 3.5: Sending order and requirements flow chart.

3.3.3 Initialization Command Words:

There are four ICW s for 8259A that are selected when the A0 pin is at logic 1 except for ICW1. When the 8259A is selected by using CS then ICW1, ICW2, and ICW4 are set to 8259A. If the 8259A is programmed in cascaded mode by ICW1 then ICW3 must also be programmed that is if there is a single 8259A then only ICW1, ICW2, ICW4 are programmed. If the system uses cascaded mode then all four ICW s, ICW1, ICW2, ICW3, ICW4 are to be programmed.

Initialization Command Word1 (ICW1):

ICW1 is used to program the basic operation of 8259A. D0=1 that is IC4=1 if ICW4 is required. If ICW4 is not required then it must be ‘0’. Generally, when programming is required with IC4 ‘D0’ must be 1.

Bit D1 is used to divide in which mode 8259A is to be operated. If it is ‘1’ then 8259A is operated in single mode, if D1=0 it is operated in cascaded mode. If cascade operation is selected then ICW3 must also be programmed.

D2, D5, D6, D7 bits are used when 8-bit processors are used like 8085. In 8086 these bits are don’t care bits.

A0 D7 D6 D5 D4 D3 D2 D1 D0

If D0=1, ICW4 needed

IfD0=0,NoICW4 needed

If D1=1, single

If D1=0, cascade mode

Call address interval

If D2=1, interval of 4

If D2=0, interval of 8

If D3=1, level triggered mode

If D3=0, edge triggered mode

A7 - A5 of interrupt vector address (MCS- 80/85 mode only)

Fig 3.6:ICW1 format of 8259A

D2 is call address interval (ADI) which is used for dividing the interval between two interrupt values in the interrupt table. If D2=1 then interval is 4. If D2=0 the interval is 8. This is used only with 8080/8085 microprocessors, for 8086 D2=X don’t care.

0 A7 A6 A5 1 LTIM ADI SNGL IC4

D3 bit is used to determine what type of triggering is used when interrupt request input is given. If LTIM=1 then level triggered mode is used and if LTIM=0 then edge triggered mode is used. D4 bit must be always 1.

D5, D6, D7 are A5, A6, A7 which are used for vectored interrupt address only. These are used along with 8086 or 8085. When 8086 is used D5, D6, D7 are don’t care.

Initialization Control Word2 (ICW2):

A0 D7 D6 D5 D4 D3 D2 D1 D0

A15 – A8 of interrupt vector address

(MCS 80/85 mode T7 – t3 of interrupt vector address 8086/8088).

Fig 3.7: ICW2 format of 8259A

In an 8086 system, ICW2 is used to tell the 8259A the type number to send in response to an interrupt signal on the IR0 input. In response to an interrupt signal on some other IR input, the 8259 will automatically add the number of the IR input to this base number and send the result to the 8086 as the type number for that input.

D0 – D7 that is A8 – A15 are vectored interrupt address and they are used when 8080/8085 connected to 8259A.

D3 – D7 that is T3 – T7 are used when 8086/8088 is used.

1 A15/t7 A14/T6 A13/T5 A12/T4 A11/T3 A10 A9 A8

Initialization Control Word3 (ICW3):

A0 D7 D6 D5 D4 D3 D2 D1 D0

If S7 – S0 =1 IR input has slave

If S7 – S0 =0 IR input does not have a slave

ICW3 (Slave device)

A0 D7 D6 D5 D4 D3 D2 D1 D0

Slave ID

ICW3 (Master device)

1 S7 S6 S5 S4 S3 S2 S1 S0

1 0 0 0 0 0 ID2 ID1 ID0

0 1 2 3 4 5 6 7

0 1 0 1 0 1 0 1

0 0 1 1 0 0 1 1

0 0 0 0 1 1 1 1

Fig3.8: ICW3 format of 8259A

ICW3 is used only when ICW1 indicates that the system is operated in cascaded mode (that is D1 bit of ICW1 must be 0). This Command Word indicates the position to which IR input the slave is connected. If the bits D0 – D7 are equal to zero then it indicates that the corresponding IR input does not have a slave. If the values of D7 – D0 are 00001000 then IR7 is having a slave.

The master and slave will have different ICW3 values. The master ICW3 indicates while interrupt input is having slave. The ICW3 of slave will have D3 – D7 as ‘0’. The first three bits D0 – D2 will indicate the slave identity. If D0 – D2 is 100 then the interrupt line IR1 is having a slave that is the slave number is send on CAS0, CAS1, CAS2 lines of master. The slave is recognized by its number based on CAS0, CAS1, CAS2 lines and sends the type of interrupt to the 8086 when it receives an INTA pulse.

Initialization Control Word4 (ICW4):

This Command Word is used to indicate which microprocessor associated with 8259A. The right most bit must be at logic1 to operate with 8086 microprocessor. If D0=0 then it indicates that the microprocessor associated is 8085. The remaining bits are programmed as follows.

D1=AEOI automatic or normal end of interrupt. If this is not used or not selected by ICW4 then the EOI command of OCW2 are used. If AEOI is selected, the interrupt automatically resets the interrupt request bit and does not modify priority. If D1=1 then it is auto EOI. If D1=0 then the system is in normal EOI mode. If D1=1, then 8259A is able to respond to an interrupt signal on a lower priority interrupt input.

M/S and buffer: Buffer and master slave are used together to select buffered operation or non-buffered operation for the 8259A as a master or slave. If D3=0 then the system is in non-buffered mode irrespective of the value of D2. If D3=1, then the master or slave mode is dependent upon the value of D2. If D2=0 then it is buffered slave mode. If D2=1 then it is buffered master mode. D3=1 indicates buffered mode.

SFNM (D4): This bit is used to indicate whether nested mode is fully selected or not. If D4=SFNM=1, then the special fully nested mode of operations selected. This allows the highest priority interrupt request from a slave to be recognized by the slave while it is processing another interrupt from a slave. Only one interrupt request is processed at a time

and others are ignored until the process is complete. If D4=0 then the system is not special fully nested mode. Bits D5, D6, D7 will be zero always which is not used for any special purpose.

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 SFNM BUF M/S AEOI μ PM

1 = 8086/8088 Mode

0 = MCS_80/85 Mode

1 = Auto EOI

0 = Normal EOI

1 = Special fully

nested mode

0 = Not special fully

Nested mode

Fig 3.9: OCW1 format

Operation Command Words: The operation command words (OCWs) are used to direct the operation of the 8259A after it is programmed with ICW. The OCW is selected when the A0 pin is at logic 0 level except for OCW1.

Operation Command Word 1 (OCW1):

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 M7

M6

M5

M4

M3

M2

M1

M0

Interrupt Mask

1 = Mask Set

0 X Non Buffered Mode

1 0 Buffered Mode/Slave

1 1 Buffered Mode/Slave

0 = Mask Reset

Fig3. 10: OCW1 format

This operation command word is used to set and read the interrupt mask register. When a mask bit is set then it will turn off or mask the corresponding interrupt input. The mask register is read when OCW1 is read. OCW1 must be programmed after programming the ICW because the states of mask bits are not known initially.

Bits D0 – D7 denoted as M0 – M7 will indicate the interrupt mask when they are equal to 1, A0 must be equal to 1 in this operational command word.

Operation Command Word 2 (OCW2):

A0 D7 D6 D5 D4 D3 D2 D1 D0

0 R SL EOI 0 0 L2 L1 L0

IR level to be acted upon

0 1 2 3 4 5 6 7

0 1 0 1 0 1 0 1

0 0 1 1 0 0 1 1

0 0 0 0 1 1 1 1

0 0 1 Non Specific EOI CommandEnd of Interrupt

0 1 1 Specific EOI Command

1 0 1 Rotate on Non Specific EOI Command

Automatic Rotation

1 0 0 Rotate in Automatic EOI Mode (set)

0 0 0 Rotate in Automatic EOI Mode (Clear)

1 1 1 * Specific EOI Command

1 1 0 * set priority command Specific Rotation

0 1 0 No Operation

Fig 3.11: OCW2 format

OCW2 is selected only when AEOI of ICW4 is not selected. By using OCW2, 8259A decides in what way it has to respond to an interrupt.

D0 – D2 bits denoted as L0 L1 L2 are used to select the lowest priority interrupt that is if D2 D1 D0 =000 then IR0 is activated if D2 D1 D0=001, then IR1 is activated. Bits D3 and D4 must be always ‘0’.

Bits D5D6D7 are used to indicate various ends of interrupt EOI options. If D7D6D5 equal to 001 then it is non-specific EOI command. In this case 8259A automatically determines which interrupt level was active and resets the bits of interrupt status register. If this bit is set again then the interrupt action takes place again then the interrupt action takes place again otherwise a lower priority interrupt takes the effect.

If D7D6D5=011 then it is specific end of interrupt. This state allows to resetting a specific interrupt. The exact position of the interrupt bit is indicated by the values of D0D1D2 (L0 – L2) of OCW2.

If D7D6D5=101 then it is rotate on non-specific EOI. This is similar to Non-specific end of interrupt command bit rotates interrupt priorities after resetting the interrupt status registers bit. The level reset by this command becomes the lowest priority interrupt. If IR2 was just serviced by this command then IR3 will by the highest priority and IR2 will be the lowest.

If D7D6D5=100 then it rotates in automatic EOI mode, this state is also known as SET state. In this state automatic EOI is selected with rotating priority but this command must be given only once. If this mode must be turned off we have to give clear command. Clear is possible if D5D6D7=000 which also known as rotate in automatic EOI mode (clear).

If D7D6D5=111 then the state is rotate on specific EOI command bit selects rotating priority. The exact position is determined by the values of bits D0D1D2 that is L0 L1 L2.

If D7D6D5=110 then it is known as set priority command. This command allows the programmer to select and set the lowest priority interrupt input using L0 – L2 bits.

If D7D6D5=010 then the command is no operation. The first three states that is D5D6D7=001, 011, 101 are known as end of interrupt states similarly next three states are known as automatic rotation states, and last three are known as specific rotation.

Operation Command Word 3 (OCW3):

A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 ESMM SMM 0 1 P RR RTSRead register command

0 1 0 1

0 0 1 1

No

action

Read IR

register

on next

RD pulse

Read IS

register

on next

RD pulse

1 = Poll command

0 = No Poll command

Fig 3.12:OCW3 format

This command word is used to select the register read, the operation of the special mask register and the poll command. The bits D0 D1 are used for read register command. They are denoted by RR, RIS.

D0 D1=00 or 10 no action takes place. If D0=0 and D1=1 then the 8259A reads the IRR on next RD pulse.

If D0=1 and D1=1 then 8259A reads the ISR on next RD pulse.

Special Mask Mode

0 1 0 1

0 0 1 1

No action

Reset

Special

mask

Set

special

mask

The bit D2 is used for polling purpose. If p=1 then polling is selected. If p=0 then there is no polling. The next read operation will read the poll word. The right three bits will indicate the active interrupt request with the active interrupt request with the highest priority. The left most bit indicates whether there is an interrupt or not.

D3 must be 1 and D4 must be 0 always. Bits D5 and D6 are used for special mask mode.

If SMM, ESMM=00 or 10 then no action takes place. If SMM (D5)=0 and ESMM (D6)=1 the state is reset special mask. If SMM, ESMM both are equal to 1 then it is known as set special mask state. D7 must be 0 and as already indicated A0=0.

From the above operational command words we can come to the conclusion that IRR and IST are read by programming OCW3. IMR is read through OCW1. D0 and D1 of OCW3 will indicate which register is to be read out of the two IRR and ISR when A0=0. To read IMR, A0 must be 1 to read either IRR or ISR, A0=0.

The Special Features Of 8259:

8259 can manage 8 interrupts according to instructions written into its control registers.

all interrupts are spaced at either 4 or 8 locations hence it can vector as interrupt anywhere in the memory map.

8259 can resolve 8 levels of interrupts in different modes.

8259 can mask each interrupt individually.

It can read states pending interrupts, in service interrupts and masked interrupt.

It can accept level or edge triggered interrupts.

Cascading allows up to 64 instructions.

Interrupt Operation Sequences In 8259A:

When an interrupt line goes high the following sequences of events takes place.

The IRR gets the interrupt signal which is stored.

The priority resolver checks the priority after verifying IMR, IRR and ISR and sets the INT high when appropriate.

The microprocessor acknowledges the interrupt by sending INTA.