3dcob: a new design approach for monolithic 3d integrated circuits h. sarhan, s. thuries, o....

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3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Bil loint and F. Clermidy CEA-LETI, Minatec Campus, Fra nce ASPDAC 2014

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Page 1: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

3DCoB: A new design approach for Monolithic 3D Integrated Circuits

H. Sarhan, S. Thuries, O. Billoint and F. Clermidy

CEA-LETI, Minatec Campus, France

ASPDAC 2014

Page 2: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

Outline

Introduction Monolithic 3D ICs 3D Cell-on-Buffer (3DCoB) Design Flow Experimental Results Conclusions

Page 3: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

Introduction

3D monolithic integration is a methodology to fabricate the 3D IC where a second transistor layer is directly fabricated on top of the first one.

The two transistors layers are connected through high-density inter-tier vias (about 100 times smaller compared to the TSVs).

Page 4: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

Monolithic 3D ICs

Monolithic 3D integration approaches: Transistor-level (N/P) Gate-level (Cell on cell)

Transistor-level Gate-level

Page 5: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

Monolithic 3D ICs

Transistor-level (N/P)

Gate-level (Cell-on-cell)

Page 6: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

3D Cell-on-Buffer (3DCoB)

The main idea of the 3DCoB is to split the non-minimum drive 2D cells into a logical function stage and a drive stage.

One tier contains the equivalent minimum-drive gate.

The other tier contains a buffer to maintain the same driving capabilities of the cell.

The 3DCoB cell has internally two inter-tier vias.

Page 7: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

3D Cell-on-Buffer (3DCoB)

Page 8: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

3D Cell-on-Buffer (3DCoB)

Page 9: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

3D Cell-on-Buffer (3DCoB)

The advantage of the 3DCoB 3DCoB cells can be used by the conventional 2D place

and route tools.

No need for inter-tier routing metal layers between cells.

Improve the overall performance by decreasing the input gate capacitance of the cells.

Page 10: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

Design Flow

3DCoB generation process

Page 11: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

Design Flow

For example 2-input AND gate (AND2) with drive 42

(AND2x42) Minimum drive for all the 2-input AND gate is 4

(AND2x4) 3DCoB cell will be the min-drive AND2 cell

(AND2x4) connected to the equivalent drive buffer (BUFx42)

Page 12: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

Design Flow

Page 13: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

Design Flow

Full design flow for 3DCoB approach

Page 14: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

Experimental Results

Page 15: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

Experimental Results

Page 16: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

Experimental Results

Page 17: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

Experimental Results

Page 18: 3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France

Conclusions

3D monolithic integration technology offers a fine grain integration level thanks to high density and low-parasitics inter-tier vias.

This paper introduced 3DCoB as a new design approach which is fully compatible with the conventional 2D implementation design flow tools.