3d tsv product qualification challenges - sematech tsv product qualification challenges product...

3D TSV Product Qualification ChallengesProduct Level Reliability

Presented by: Mark NakamotoQualcomm Inc 5775 Morehouse Dr San Diego CA 92128

PAGE 1 QUALCOMM CONFIDENTIAL AND PROPRIETARY

Qualcomm Inc., 5775 Morehouse Dr., San Diego, CA, 92128, [email protected] tel 858 651 8927

Outline : 3D Product Level Reliability

3D Structures and RisksWhat is Product Level Reliability? Parts vs. Whole The Bottom Line Requirements and Use Conditions

Roles and Responsibilities by Levelp y

Fundamental Challenges to Success Reliability Test Method Limits Old Standards and New Risks Old Standards and New Risks

3D Reliability – 30,000 ft View Reliability over the lifetime Some Observations Some Observations

The Challenge


3D Structures and Risks

A Look at 3D StucturesTier 2

Thickness ~ 100 umUnderfill

Gap ~ low 10’s of umActive Face Down

Tier 2 FEOLThickness ~ 1’s of um

p

u-BumpSize ~ 10’s of umPitch ~ 10’s of um

BackSide MetalWidth ~ 1’s of um

TSV

Width ~ 1 s of umPitch ~ 10’s of um

Tier 1Thickness ~10’s of umActive Face Down

TSVSize ~ 1’s of umPitch ~ 10’s of um

UnderfillGap ~ hi 10’s of um

Tier 1 FEOLThickness ~ 1’s of um

Flip Chip BumpSize ~ <100 umPitch ~ 100 um

Package Substrate

~ mm

Thickness ~ 100’s of um



3D Reliability – What’s New?

N F t New Features TSV’s and ubumps

New(ish) Materials and ProcessesV hi h t ti li id d b i f TSV Very high aspect ratio liner oxide and barriers for TSVs Very large and high aspect Cu TSVs Variety of ubump configurations and compositions Backside isolations with low temperature depositionac s de so a o s o e pe a u e depos o Chip Stacking Processes

Not new but extended/leading effects Very Thin Die By Permission: Amkory Small Hard Bumps Chip Package Interaction (CPI) 300mm wafer,

Disco, G.Klug EMPC 2009


50um thick


3D Risks – Few Examples TSV risks TSV risks Cu Pumping, cracking EM, liner ox, barrier, stress

uBump risks

S.Cho RTI Workshop

uBump risks EM, mis-align, stress

Thin Die risks Warpage, stressp g ,

Backside Metal and Iso/Pass Cu contamination, EM, PID, TDDB

Other

ubumpMobility near TSV

Other Thermal, ESD, etc

Heat Maps IMEC

300mm wafer, Disco, G.Klug EMPC 2009


Tier 1 Die Tier 2 DieYM Lin ITRI/UCLA 50um thick


3D Risks – Perspective

No 5th Horseman for 3D Qualification

The 4 Horsemen of 3D ICPhil Garrou, October 16, 2009Semiconductor International


What is product Reliability?

Product Reliability – Parts vs. WholeWhat is Product Level Reliability?at s oduct e e e ab ty Sometimes it depends on who you ask

Product Reliability for our Industry is: “Component Level Reliability” Sum of the Parts + IntegrationSum of the Parts + Integration

It’s a 2000 hr HTOL

It’s 500 Temp Cyclesl i i TCyclesElectromigration

TestTemp

Humidity Bias


TDDB Test

Drop Shock


Product Reliability – The Bottom Line How do we measure it? Failure Rates!

EarlyLife

End ofLife

Useful Life

Bathtub

Defect Driven Wear Outat

e

BathtubCurve

Wear Out

Failu

re R

a

ConstantRandomF

Infant Mortality


Time


Product Reliability – Use Conditions, Lifetime and Targets Product Reliability only makes sense in the context of an environment Product Reliability only makes sense in the context of an environment Use conditions specify the expected range of conditions

– Electrical: Voltage, Currents, ESD, etc.– Thermal/Mechanical: Temperature(average, range, cycles), Shock, Vibration, etc.– Other: Humidity, Chemical Exposure, etc.

Lifetime expectations are key to wear out lifetime– Telecom, Avionics, etc often have long lifetimes (eg. 10-20 years)– Commercial products often have middle lifetime expectations (eg. 5 years)– Consumer products often have short expected lifetimes (eg. 2 or 3 years)

Failure Rate Expectations and Tolerances also vary by product– Medical (Time To First Fail vs. Mean Time To Fail)– Critical Applications (Nuclear, Avionics, etc.)– Consumer (Cost vs. Risk trade-offs)


Roles and Responsibilities by Level

Roles and Responsibilities

al

System Qualified Product Customer

P d Lif

Failure Rate Requirements

mpo

nent

Qu Product Lifetest

(HTOL, HTSS, etc)Use Conditions

System Lifetest

F il A l i

Com

Component

Tests and Screens•Fault Coverage•Sub component tests

Failure Analysis•Fault Isolation•Root Cause identification

Bumps, ubumps, underfill, warpage,

CPI,

TSVs, Liner Ox, Backside Metal,

Backside Iso/pass, thin die etc

OSATFab/Foundry

Mechanical & Environmental Tests(Temp Cycle, THB, etc)

thin die, etc.


Failure Mechanism Accelerated Tests(EM, SM, TDDB, etc.)

Roles and Responsibilities by Level

3D Reliability – The Putting It Together

Design Rules

Tier 2 Si

• 3D drives interactions• More complexity• More features

M bi ti

Whose Assembly Process and What Interactions?

• More combination• Thin die

• Component House owns:D i I t ti

Design Rules

Tier 1 Si Die

• Design Interactions• Integration• Final Responsibility

Whose Assembly Process and What Interactions?

Design RulesPCB Package Substrate


Fundamental Challenges

Failure Mechanism – Accelerated Test Limitations How much acceleration can we get?o uc acce e at o ca e get Too much stress often changes mechanism and acceleration factors

– Examples:» High currents in EM testing heats samples often non-uniformly» High voltages in HCI or NBTI often change the ratio of charge generation to charge trappingg g g g g g pp g

% S

hift

Trap Generation

Trap Fill Rate Limited

Rate Limited


S.Chiu, Natl Chiao Tung Unv TW

Time on Stress


Failure Mechanism – Accelerated Test Limitations Accelerated Test Structures by nature are smally High Acceleration and Fault Isolation requirements drive small feature count Feature variations are also limited

Wh t Fl f C t t Ch i ?2B What Flavor of Contact Chain?

Wgsimon

vsTypical Test Structures:10s to 1000s of contacts or vias100s to 1000s of um of routing

vs.


100s to 1000s of um of routing10s to 1000s of um^2 of oxide


Component Lifetests – Accelerated Test Limitations

Actual Product or “Product Like” Test Vehicles have several advantages Visibility into Design interactions Higher Feature counts and more feature variety Testing is closer to use mode of operation Testing is closer to use mode of operation

There are however limits and a few disadvantages Design, test set-up and materials limit accelerationg

– Designs often function in a limited voltage and temp. range– Lifetest systems are often limited to a few MHz– Materials often limit maximum temperatures

Product level tests are also limited in sample size and require significant test and Failure Analysis resources Product Level ATE test support

F lt I l ti i l Fault Isolation is more complex

Acceleration = T x V x FT V F



Old Tests vs. New Risks Semiconductor Reliability has a long history and encompass many Semiconductor Reliability has a long history and encompass many

standards and methods: JEDEC, MIL-SPEC, etc. Valuable empirical and theoretical knowledge base

Standards and Methods are slo and diffic lt to change Standards and Methods are slow and difficult to change Decisions by industry consensus Reliability and Quality teams are a naturally conservative population

D li ith t i l d t t i h ll Dealing with new processes, materials and structures is a challenge For example; harder bumps, large die and weaker low-K dielectrics have

driven changes in package substrates, underfills and mold compounds– A few years ago a company suffered a write-off of 100s of $M due to a bump– A few years ago a company suffered a write-off of 100s of $M due to a bump

related issue which was not caught by the existing test methods during qualification


SPECs MethodsSPECs Methods

3D Reliability – 30,000ft View

3D Reliability – Back to the Bathtub: Early Life

Infant Mortality is Defect Driven Screens/Tests to weed out marginal parts

– KGD and pre-stack testing– Test Coverage and Margin TestingTest Coverage and Margin Testing– Voltage Stress Test, etc.– Burn-in (expensive, only special cases)

Infant Mortality is tied to Process Maturity Infant Mortality is tied to Process Maturity Tracks with Yield improvement Requires learning cycles and part volumes

Defect Driven Wear Out

e

EarlyLife

End ofLife

Useful Life

BathtubCurve


WearOut

Failu

re R

ate

ConstantRandom

Wear Out


Time

Infant Mortality


3D Reliability – Back to the Bathtub: Useful Life Useful Life Failure Rate is Defect Driven Useful Life Failure Rate is Defect Driven 3D has a limited number of features and limited feature variations

– 1000’s of components not millions or billions Traditionally this is covered by Product Level Tests such as HTOL

Li i d b 3D f hi b b h dl d b i l– Limited by 3D feature count per part means this may be better handled by simpler test vehicles and larger sample sizes

HTOL like tests are still needed to look at interactions of 3D with base silicon process and circuits

EarlyLife

End ofLife

Useful Life


Rat

e

BathtubCurve

Wear Out

Failu

re R

Infant

ConstantRandom


Time

Infant Mortality


3D Reliability – Back to the Bathtub: End of Life Wearout is the domain of Fab and Assembly Process QualificationWearout is the domain of Fab and Assembly Process Qualification Highly accelerated mechanism tests: EM, TC, TS, TDDB, ….. Models are needed to relate test results to product application

– Design InteractionsU di i– Use conditions

Rules for layout and use Small feature count/variety on product matches well with test structures

EarlyLife

End ofLife

Useful Life

Bathtub


e R

ate

BathtubCurve

Wear Out

Failu

re

Infant Mortality

ConstantRandom


TimeMortality


3D Reliability – Rethinking Methodology New structures materials and process flows in 3D will require us to New structures, materials and process flows in 3D will require us to

rethink our traditional test methods Example: Will a Standard Temperature Cycle capture the critical effects?

Do we need to change test conditions such as end points ramp rates dwell times– Do we need to change test conditions such as end points, ramp rates, dwell times.– Non-uniform heating on product may require power cycling

Component Tests like HTOL often considered a “Catch All”Component Tests like HTOL often considered a Catch-All Large feature counts/variety and product circuitsFor 3D it mainly serves as a check for 3D interacting with the 2D process



3D Qualification – Perspective

3D Chi St ki Q lifi ti i t th Si P 3D Chip Stacking Qualification is not the same as a new Si Process New Features and Processing but …. Limited number of features and limited feature variety

Qualification thus has two focuses Qualify new features Qualify interaction with base silicon process

Bottom DieLogic

Top DieTop DieWide-IO Memory

TSVs, ubumps

AMD 45nm


The Challenge

3D Reliability – The Challenge

3D Reliability from the Product Perspective3D Reliability from the Product Perspective Product Reliability is an intelligent integration of goals and methods Fab and Assembly Process Qualificationsy

– Characterize and Model Failure Mechanisms– Define Reliability Rules

Product/Design Qualificationsg– Insure Product/Design is covered by Process Qualification

» Use conditions, build configurations, non-uniform temp. distributions, etc.

– Evaluate interactions between design and process» Sensitive IP, Reliability Rule compliance, etc.

– Failure Rate Estimation and Budgeting3D Reliability

Today let us start the journey to define 3D Qualification Requirements


Today let us start the journey to define 3D Qualification Requirements Review 3D Failure Mechanisms, Test Methods and Models vs Product Goals

3d tsv product qualification challenges - sematech tsv product qualification challenges product...

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